Abstract: A non-volatile memory having a gate all around thin film transistor includes a multi-layer structure, an elongated plug structure, a first conductive plug, and a second conductive plug. The multi-layer structure includes a plurality of gate electrode layers stacked on a substrate separately from each other. The elongated plug structure penetrates through the multi-layer structure, and a cross-section of the elongated plug structure has an elongated contour. The elongated plug structure includes an insulating pillar, a channel layer, and a gate dielectric layer. The channel layer surrounds the insulating pillar. The gate dielectric layer surrounds the channel layer. The gate electrode layers surround the gate dielectric layer. The first conductive plug is disposed between the channel layer and the substrate and between the insulating pillar and the substrate. The second conductive plug is disposed on the insulating pillar and is covered by the channel layer.

Abstract: A non-volatile memory having a gate all around thin film transistor includes a multi-layer structure, an elongated plug structure, a first conductive plug, and a second conductive plug. The multi-layer structure includes a plurality of gate electrode layers stacked on a substrate separately from each other. The elongated plug structure penetrates through the multi-layer structure, and a cross-section of the elongated plug structure has an elongated contour. The elongated plug structure includes an insulating pillar, a channel layer, and a gate dielectric layer. The channel layer surrounds the insulating pillar. The gate dielectric layer surrounds the channel layer. The gate electrode layers surround the gate dielectric layer. The first conductive plug is disposed between the channel layer and the substrate and between the insulating pillar and the substrate. The second conductive plug is disposed on the insulating pillar and is covered by the channel layer.

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.