Patents by Inventor Zuxu Qin
Zuxu Qin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11334109Abstract: A clock stretcher includes a delay line, a control unit, and a combiner. The delay line outputs a series of delayed phases of an input clock. The control circuit is clocked by the input clock. It outputs a series of delayed phase enable signals. The combiner circuit receives the delayed phases from the delay line and the delayed phase enable signals from the control circuit, and outputs a modified clock. The control circuit determines if stretching has started, if wraparound must occur, and if a next phase must be enabled. The combiner retimes a delayed phase enable signal for a first delayed phase using a flipflop clocked by a second delayed phase to generate a retimed phase enable signal. The combiner uses the retimed phase enable signal to pass a pulse of the first delayed phase to the output as a pulse of the modified clock.Type: GrantFiled: August 18, 2021Date of Patent: May 17, 2022Assignee: SambaNova Systems, Inc.Inventors: Fahim ur Rahman, Mahmood Khayatzadeh, Zuxu Qin, Jin-uk Shin
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Patent number: 11323124Abstract: A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The DLL has a phase error because of its finite bandwidth. The clock stretcher measures the phase error and corrects for a glitch in the modified clock signal by using the phase error when phase selection wraparound occurs. The clock stretcher may operate from a power supply that has droops, without intervening voltage regulation.Type: GrantFiled: June 3, 2021Date of Patent: May 3, 2022Assignee: SambaNova Systems, Inc.Inventors: Fahim ur Rahman, Mahmood Khayatzadeh, Zuxu Qin, Jin-Uk Shin
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Patent number: 10712769Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.Type: GrantFiled: August 16, 2017Date of Patent: July 14, 2020Assignee: Oracle International CorporationInventors: Dabin Zhang, Philip P. Kwan, Zuxu Qin
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Patent number: 10257121Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.Type: GrantFiled: October 2, 2017Date of Patent: April 9, 2019Assignee: Oracle International CorporationInventors: Zuxu Qin, Baoqing Huang, Dawei Huang, Kuai Yin, Maoqing Yao, Philip Kwan
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Publication number: 20190104088Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.Type: ApplicationFiled: October 2, 2017Publication date: April 4, 2019Inventors: Zuxu Qin, Baoqing Huang, Dawei Huang, Kuai Yin, Maoqing Yao, Philip Kwan
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Publication number: 20190056760Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.Type: ApplicationFiled: August 16, 2017Publication date: February 21, 2019Inventors: Dabin Zhang, Philip P. Kwan, Zuxu Qin
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Patent number: 10135643Abstract: An embodiment includes a first feedback tap, a second feedback tap, and a summation circuit. The summation circuit may include a first load and a second load coupled to each other at an internal circuit node, and coupled in series between a power supply node and an output node. The summation circuit may be configured to receive, via a serial communication link, an input signal indicative of a series of data symbols, and to generate an output voltage level on the output node based upon a current data symbol. The first feedback tap, coupled to the output node, may be configured to sink a first current from the output node based upon a first previously received data symbol. The second feedback tap, coupled to an intermediate circuit node, may be configured to sink a second current from the intermediate circuit node based upon a second previously received data symbol.Type: GrantFiled: July 20, 2017Date of Patent: November 20, 2018Assignee: Oracle International CorporationInventors: Long Kong, Ranjan Vaish, Muthukumar Vairavan, Zuxu Qin
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Patent number: 9893878Abstract: Embodiments include systems and methods for on-chip random jitter (RJ) measurement in a clocking circuit (e.g., in a phase-locked loop of a serializer/deserializer circuit). Some embodiments determine a reference delay code sweep window to capture at least a candidate RJ range of a feedback clock signal, the reference delay code sweep window comprising a sequence of reference delay codes. A distribution of one-scores can be computed over the reference delay code sweep window, so that the distribution indicates a relatively likelihood, for each reference delay code, of obtaining a ‘1’ sample when sampling the feedback clock signal according to the delayed clock signal (delayed by an amount according to the reference delay code). The distribution can be transformed into a time domain by computing code offset times for the reference delay codes. A RJ output can be computed as a function of the distribution in the time domain.Type: GrantFiled: March 15, 2017Date of Patent: February 13, 2018Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Long Kong, Ben Li Chen, Philip Kwan, Zuxu Qin, Dawei Huang
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Patent number: 9832013Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.Type: GrantFiled: February 1, 2016Date of Patent: November 28, 2017Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Ben Li Chen, Zuxu Qin, Nima Edelkhani
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Publication number: 20170222796Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.Type: ApplicationFiled: February 1, 2016Publication date: August 3, 2017Inventors: Ben Li Chen, Zuxu Qin, Nima Edelkhani
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Patent number: 9036757Abstract: Embodiments include systems and methods for applying post-cursor locking point adjustment to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). In one embodiment, a training routine is used to determine an optimal post-cursor target level. Increasing or decreasing the post-cursor target level can cause the CDR clocking to shift right or left, which can be seen as a shift of the channel impulse response with respect to the CDR sampling locations. In some implementations, the post-cursor can be locked to the determined target level. In other implementations, the determined target level can be compared to a fully-adapted post-cursor to tune adaptations performed by transmitter and/or receiver equalizers.Type: GrantFiled: September 23, 2014Date of Patent: May 19, 2015Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Jianghui Su, Francis Schumacher, Zuxu Qin, Dawei Huang
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Patent number: 8994427Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.Type: GrantFiled: July 9, 2013Date of Patent: March 31, 2015Assignee: Oracle International CorporationInventors: Zuxu Qin, Dawei Huang, Deqiang Song, Jianghui Su, Baoqing Huang, Yan Yan
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Publication number: 20150015315Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.Type: ApplicationFiled: July 9, 2013Publication date: January 15, 2015Inventors: Zuxu Qin, Dawei Huang, Deqiang Song, Jianghui Su, Baoqing Huang, Yan Yan
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Patent number: 8634500Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.Type: GrantFiled: March 27, 2012Date of Patent: January 21, 2014Assignee: Oracle International CorporationInventors: Zuxu Qin, Rajesh Kumar, Dawei Huang, Jing Shi, Deqiang Song
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Publication number: 20130259162Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Inventors: Zuxu Qin, Rajesh Kumar, Dawei Huang, Jing Shi, Deqiang Song
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Patent number: 8452829Abstract: A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.Type: GrantFiled: June 23, 2008Date of Patent: May 28, 2013Assignee: Oracle America, Inc.Inventors: Dawei Huang, Dong J. Yoon, Osman Javed, Zuxu Qin, Deqiang Song, Daniel J. Beckman, Drew G. Doblar, Waseem Ahmad, Andrew Keith Joy, Simon Dennis Forey, William Franklin Leven, Nirmal C. Warke
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Patent number: 8243866Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.Type: GrantFiled: May 7, 2008Date of Patent: August 14, 2012Assignee: Oracle America, Inc.Inventors: Dawei Huang, Zuxu Qin, Drew G. Doblar, Waseem Ahmad, Dong Joon Yoon, Osman Javed
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Publication number: 20100283535Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.Type: ApplicationFiled: April 30, 2010Publication date: November 11, 2010Applicant: FutureWei Technologies, Inc.Inventors: Minsheng Li, Gong Tom Lei, Song Liu, Jun Xiong, Yincai Liu, Feiqin Yang, ZuXu Qin
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Publication number: 20090316727Abstract: A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.Type: ApplicationFiled: June 23, 2008Publication date: December 24, 2009Applicant: Sun Microsystems, Inc.Inventors: Dawei Huang, Dong J. Yoon, Osman Javed, Zuxu Qin, Deqiang Song, Daniel J. Beckman, Drew G. Doblar, Waseem Ahmad, Andrew Keith Joy, Simon Dennis Forey, William Franklin Leven, Nirmal C. Warke
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Publication number: 20090224806Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.Type: ApplicationFiled: May 7, 2008Publication date: September 10, 2009Applicant: Sun Microsystems, Inc.Inventors: Dawei Huang, Zuxu Qin, Drew G. Doblar, Waseem Ahmad, Dong Joon Yoon, Osman Javed