Abstract: A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.

Abstract: A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the transmitted overall coded signal. Despread instructions are included in the digital signal processor functionality.

Abstract: A cache memory preprocessor prepares a cache memory for use by a processor. The processor accesses a main memory via a cache memory, which serves a data cache for the main memory. The cache memory preprocessor consists of a command inputter, which receives a multiple-way cache memory processing command from the processor, and a command implementer. The command implementer performs background processing upon multiple ways of the cache memory in order to implement the cache memory processing command received by the command inputter.

Abstract: A method for caching specified data in an n-way set associative memory with a copy-back update policy consists of the following steps. First, a row of the associative memory, organized as a plurality of rows and having n ways per row, is selected according to the main memory address of the specified data. The main memory provides primary storage for the data being cached. If one of the ways of the selected row holds invalid data, the specified data is cached in the way holding the invalid data and the data caching process is discontinued. If all n ways of the selected row hold valid data, the following steps are performed. First, a replacement strategy is used to select a way from the selected row. If the way selected in accordance with the replacement strategy holds unmodified data, the specified data is cached in the way selected by the replacement strategy and the data caching process is discontinued.

Abstract: A prefetcher performs advance retrieval of data from a main memory, and places the retrieved data in an intermediate memory. The main memory is accessed by vector addressing, in which the vector access instruction includes a main memory address and a direction indicator. Main memory data is cached in an associated cache memory. The prefetcher contains a direction selector and a controller. The direction selector selects a direction of data access according to the direction indicator of a single data access transaction. The direction indicator is supplied by the processor accessing the main memory, and incorporates the processor's internal knowledge of the expected direction of future data accesses. The controller retrieves data items from the main memory, in the direction of access selected by the direction selector, and places the retrieved data items in the intermediate memory.

Abstract: A data storage and distribution apparatus provides parallel data transfer between a segmented memory and the apparatus outputs. The apparatus consists of a segmented memory and a switching grid-based interconnector. The segment memory is formed from a group of memory segments, which each have a data section and an associative memory section. A switching grid-based interconnector is connected to the segmented memory, and provides parallel switchable connections between each of the outputs to selected memory segments.

Abstract: A CPU includes a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each of which is connected to an associated internal bus. All of the functional units are connected to each of the internal busses so that each of the functional units can read from and write to all memory locations. To conduct a transaction with memory, a functional unit determines which memory location it requires, and then arbitrates for mastership of the bus associated with the section of memory containing that memory location. By providing two or more internal busses, two or more bus transactions can occur simultaneously. A virtual bus is provided to facilitate transactions between functional units. The virtual bus is a bus arbiter without an associated physical bus.

Abstract: A digital signal processor performs path search calculations for a Rake receiver. Despread operations are performed for multiple relative delays over a subcorrelation length by shifting either received chips or code chips for each relative delay. The result of a despread operation for a relative delay is added to the result of previous despread operations of the same delay performed on prior subcorrelation lengths. These calculations are performed in response to a single instruction. By issuing multiple instructions, path search calculations are performed for the entire correlation length.

Abstract: A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.

Abstract: A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. Since each local arbitrator is of common configuration with the other local arbitrators, is operating synchronously with the other arbitrators, and is provided with a similar set of inputs, each arbitrator will arrive at the same conclusion as to which processor is to become bus master. Accordingly, an external bus arbitrator is not required and acknowledge lines are not required to communicate signals indicative of the result of the bus arbitration to the processors.

Abstract: A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.