Circuit edit and obfuscation for trusted chip fabrication
Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.
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This application is a National Stage Application, filed under 35 U.S.C. 371, of International Application No. PCT/US2017/037758, filed Jun. 15, 2017, which claims the benefit of U.S. Provisional Patent Application Ser. No. 62/351,490, filed Jun. 17, 2016, which are incorporated herein by reference in their entirety, including any figures, tables, and drawings.
GOVERNMENT SUPPORTThis invention was made with government support under Grant No. FA9550-14-1-0351 awarded by the U.S. Air Force Office of Scientific Research (USAF/AFSOR). The government has certain rights in the invention.
BACKGROUND OF THE INVENTIONThe integrated circuit (IC) business scheme has changed over the last few decades as semiconductor scaling has reached a submicron level. A facility to manufacture a submicron semiconductor device requires an investment of several billion dollars, and this business condition leads to a division between semiconductor companies to design the IC and foundry companies to manufacture the IC designed by the semiconductor company. Under this divided business model, though the semiconductor company designing the IC can reduce the manufacturing costs and respond quickly to the market needs, the risk of security increases because the IC design company cannot control the whole process, particularly the manufacturing process. An untrusted third party foundry could reverse-engineer a layout for the IC design, or a hacker could pirate the intellectual property (IP). Camouflaging circuits including dummy contacts or a split manufacturing process have been developed. However, these methods have considerable drawbacks in terms of design overhead, cost, and security.
BRIEF SUMMARYEmbodiments of the subject invention provide novel and advantageous circuits and semiconductor devices that include one or more obfuscated circuits corrupting a correct output of an intended original circuit for protecting intellectual property (IP) piracy or integrated circuit (IC) piracy from an untrusted third party, as well as methods of fabricating and using the same.
In an embodiment of the present invention, a circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing an output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit.
In another embodiment of the present invention, a semiconductor device can include a substrate, an original circuit formed on the substrate, and an obfuscated circuit formed on the substrate and configured to change an output of the original circuit, wherein the obfuscated circuit includes a pad for recovering the output of the original circuit by modifying the obfuscated circuit.
In another embodiment of the present invention, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.
In another embodiment of the present invention, a method for designing a chip can include forming a netlist for an integrated circuit, and modifying the netlist, wherein the modifying of the netlist corrupts an intended output of the integrated circuit.
Embodiments of the subject invention provide novel and advantageous circuits, semiconductor devices, and methods for protecting from intellectual property (IP) piracy and integrated circuit (IC) piracy from one or more untrusted third parties. In the business condition that a semiconductor company, especially a design house, uses an off-site foundry company to fabricate an IC chip, the risk of IP piracy and IC piracy increases considerably. It is possible that the untrusted foundry company will overproduce the IC chip or insert a malicious circuit (e.g., hardware Trojan). IP piracy is a serious issue to design houses that not only wish to use off-site foundry companies having technological expertise but also want to protect their IP.
One technology to address this issue is split manufacturing. Split manufacturing divides a full design into Front End of Line (FEOL) and Back End of Line (BEOL) portions for fabrication by different foundry companies. Referring to
Also, logic encryption can enable a designer to controllably corrupt output of an original intended IC.
IC camouflaging can provide dummy contacts in an original layout.
In embodiments of the subject invention, trusted development and fabrication of integrated circuits (ICs) can be ensured by an obfuscation technique leveraging circuit edit. The technique relies on inserting additional logic components (e.g., gates, nets) into an integrated circuit design and/or modifying preexisting IC designs. The added/modified components can be inserted to corrupt the intended functional and structural information of the integrated circuit design. This obfuscated design can then be sent to a design-for-test (DFT) facility and, later, to a semiconductor fabrication facility, both off-site (and often overseas), which offer high-end fabrication/test infrastructures but are untrusted. Here, untrusted implies that the DFT/foundry entities could engage in IP and/or IC piracy, illicitly claiming/stealing the IP and/or IC design. Once the obfuscated design has been inserted with DFT infrastructure, it comes back to the original designer who can remove or bypass the obfuscation to retrieve the intended structure/function. In case of an IC fabricated through an untrusted foundry, the designer can leverage focused-ion-beam (FIB) technology or laser ablation technology (or other methods to remove layers of a chip or deposit metal or insulator contacts) to modify the obfuscated design and retrieve the original functionality, because he/she knows the exact location and identity of the gates or interconnects added/modified by him/her for obfuscation. The designer can also use special cell to create the integrated circuit IP at the layout level, and these can be modified with special pads and extra space to accommodate post-fabrication edit. Additionally, to ensure strong obfuscation, the designer can apply the modified cell design to several other pre-existing gates in the layout of the circuit, in order to obfuscate the identity and/or location of the modifications made by the designer for obfuscation. In case of integrated circuit intellectual property (e.g., in the form a netlist) returned from a DFT facility, the designer can remove and/or modify the gates and/or interconnects at the netlist level to retrieve the original structure/function of the IP.
Embodiments of the subject invention will aid in preventing or inhibiting IP piracy of ICs that have been fabricated at untrusted semiconductor foundries and/or have been put through DFT insertion at an untrusted site. More specifically, adversaries looking to pirate the IP will have a non-functional and obfuscated version of the design that cannot be used illicitly.
Embodiments of the subject invention can enable trusted fabrication and, consequently, intellectual property protection for ICs. In the case of fabrication by an untrusted foundry, the technology of embodiments of the subject invention offers secure manufacturing of ICs for entities such as the Department of Defense (DoD), the space industry, and the military, although it may be at a reduced volume. The low volume, if applicable, is attributed to FIB circuit edit technology, because an FIB can only edit and “de-obfuscate” ICs on a one-by-one basis. However, embodiments of the subject invention alleviate the need for key management/security, which is a primary concern in the case of integrated circuit locking or encryption technologies. They also do not require a designer to maintain a separate foundry (which is the scenario for split-manufacturing, where partitions of a design are fabricated at different foundry sites) and only require a moderate-cost FIB facility.
The location of the obfuscation circuit in the gate-level design is determined in consideration of fan-out and observability of the original circuit. For example, the final score (S1) for judging suitable obfuscation net can be expressed as the following formula:
Here, FO stands for fan-out and Obs refers to the observability of each net. The observability number for each net i is subtracted from the maximum observability, as Obsi =1 is the most observable net and Obsi >1 implies that the net is more difficult to observe. Si for each net i=1, . . . , n is calculated and each net i with Si>λ (where λ is a pre-defined threshold) is noted. Out of these nets, the desired number of nets can be chosen randomly and stored for obfuscation. It should be noted that this is an example formula, and the weights and/or metrics can be modified depending on the specific circuit.
In the case of insertion of an additional gate, algorithm 1 is considered as shown below. Algorithm 1 describes the procedure for determining the type and structure of the gate inserted. The first step in this process is to analyze the static probability of each net and then, accordingly, insert an AND/OR gate (Lines 1-9). Static probability for a node is defined as the proportion of time for which the node is at logic ‘1’ (P(1)) or ‘0’ (P(0)) and can be readily obtained from gate-level simulation. After this step, the gates go through placement (Line 8). This step is necessary because as seen from
The protection using these edit back processes including the obfuscated design includes Hard/Firm IP protection geared for digital/mixed-signal circuits. In addition, it also protects overproduction and is effective for low volume IC production for research labs, defense applications, or space applications. Circuit edit methods such as edit back can cost on the order of $100,000 to $1 million and is therefore very attractive compared to the cost of maintaining a foundry facility, which can be more than $1 billion. Though certain examples of circuit editing according to embodiments of the subject invention have been shown and discussed, these are for exemplary purposes only and should not be construed as limiting. Various other types of edits can be made to the circuit(s) within the spirit of embodiments of the subject invention.
The subject invention includes, but is not limited to, the following exemplified embodiments.
Embodiment 1A circuit comprising:
an original circuit configured to become an obfuscated circuit with a different output from the original circuit,
wherein the obfuscated circuit is configured to recover the output of the original circuit upon modification of the obfuscated circuit.
Embodiment 2The circuit according to embodiment 1, wherein the obfuscated circuit includes a logic gate, a rerouted connection, or both.
Embodiment 3The circuit according to embodiment 2, wherein the logic gate is at least one selected from an inverter, NAND, NOR, XOR, AND, and OR.
Embodiment 4The circuit according to any of embodiments 1-3, wherein the output of the original circuit is recovered by disconnecting the obfuscated circuit (e.g., added logic gates of the obfuscated circuit).
Embodiment 5The circuit according to any of embodiments 1-4, wherein the output of the original circuit is recovered by rerouting so as to bypass the obfuscated circuit.
Embodiment 6The circuit according to any of embodiments 1-5, wherein the obfuscated circuit includes a connection to a voltage source or a ground.
Embodiment 7A semiconductor device comprising:
a substrate;
an original circuit formed on the substrate and configured to become an obfuscated circuit with a different output from the original circuit;
and
a pad for recovering the output of the original circuit upon modification of the obfuscated circuit.
Embodiment 8The semiconductor device according to embodiment 7, wherein the pad is a cut pad for disconnecting the obfuscated circuit from the original circuit.
Embodiment 9The semiconductor device according to embodiment 7, wherein the pad is a contact pad for rerouting the original circuit.
Embodiment 10The semiconductor device according to embodiment 9, wherein the contact pad is connected with the original circuit via a metal contact (e.g., tungsten contact or a platinum contact).
Embodiment 11The semiconductor device according to any of embodiments 7-10, wherein the obfuscated circuit comprises a first logic gate including at least one selected from AND, OR, and XOR.
Embodiment 12The semiconductor device according to embodiment 11, wherein the first logic gate is configured such that a first input of the first logic gate is disconnected from the original circuit and the disconnected first input is connected to a voltage source VDD or a ground GND.
Embodiment 13The semiconductor device according to any of embodiments 11-12, wherein a second input of the first logic gate is connected to the original circuit.
Embodiment 14The semiconductor device according to any of embodiments 7-13, wherein the obfuscated circuit comprises a second logic gate including at least one selected from NAND and NOR.
Embodiment 15The semiconductor device according to embodiment 14, wherein the second logic gate is configured such that an input of the second logic gate is disconnected from the original circuit and the original circuit bypasses the second logic gate.
Embodiment 16A method of manufacturing a semiconductor device comprising:
designing an original circuit configured to become an obfuscated circuit with a different output from the original circuit; and
fabricating the original circuit,
wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit upon modification of the obfuscated circuit.
Embodiment 17The method according to embodiment 16, wherein the designing the circuit includes inserting a logic gate or modifying the original circuit.
Embodiment 8The method according to any of embodiments 16-17, further comprising editing the circuit.
Embodiment 19The method according to embodiment 18, wherein the editing of the circuit includes milling by a focus-in-beam (FIB) and/or depositing by the FIB.
Embodiment 20The method according to any of embodiments 18-19, wherein the editing of the circuit comprises editing a back side or a front side of a wafer on which the circuit is fabricated.
Embodiment 21The method according to embodiment 20, further comprising thinning the wafer before the editing the circuit on the back side of the wafer.
Embodiment 22The method according to any of embodiments 20-21, further comprising dicing the wafer and packaging the diced wafer.
Embodiment 23The method according to any of embodiments 16-22, wherein the designing of the circuit includes forming a netlist, analyzing obfuscation, and forming a list of suitable nets.
Embodiment 24A method for designing a chip comprising:
forming a netlist for an integrated circuit; and
modifying the netlist,
wherein the modifying of the netlist corrupts an intended output of the integrated circuit.
Embodiment 25The method according to embodiment 24, further comprising inserting a design-for-test (DFT) into the modified netlist.
Embodiment 26The method according to any of embodiments 24-25, further comprising editing the netlist or the modified netlist.
Embodiment 27The method according to embodiment 26, further comprising generating a layout based on the edited netlist.
Embodiment 28The method according to any of embodiments 24-27, wherein the modifying of the netlist includes inserting a logic gate into the netlist or rerouting a pre-existing net.
Embodiment 29The method according to any of embodiment 24-28, further comprising analyzing obfuscation and forming a list of suitable nets between the forming of the netlist and the modifying of the netlist.
It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be inclined within the sprit and purview of this application.
All patents, patent applications, provisional applications, and publications referred to or cited herein (including those in the “References” section, if present) are incorporated by reference in their entirety, including all figures and tables, to the extent they are not inconsistent with the explicit teachings of this specification.
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Claims
1. A method of manufacturing a semiconductor device comprising:
- designing an original circuit configured to become an obfuscated circuit with a different output from the original circuit, wherein configuring the original circuit to become the obfuscated circuit comprises adding an element to the original circuit to obfuscate the original circuit, and wherein the element comprises at least one of a logic gate or a net;
- fabricating the obfuscated circuit; and
- editing the fabricated obfuscated circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit upon the editing of the fabricated obfuscated circuit, and wherein the editing of the fabricated obfuscated circuit comprises removing the added element from the fabricated obfuscated circuit.
2. The method according to claim 1, wherein the editing of the fabricated obfuscated circuit comprises at least one of milling by a focused-ion-beam (FIB) or depositing by the FIB.
3. The method according to claim 2, wherein the editing of the fabricated obfuscated circuit comprises editing a back side or a front side of a wafer on which the obfuscated circuit is fabricated.
4. The method according to claim 3, further comprising thinning the wafer before the editing of the fabricated obfuscated circuit on the back side of the wafer.
5. The method according to claim 3, further comprising dicing the wafer and packaging the diced wafer.
6. The method according to claim 1, wherein the designing of the original circuit configured to become the obfuscated circuit comprises forming a netlist, analyzing obfuscation, and forming a list of suitable nets.
7. The method according to claim 1, wherein the element is a logic gate.
8. The method according to claim 7, wherein the logic gate is at least one selected from a group consisting of an inverter, NAND, NOR, XOR, AND, and OR.
9. The method according to claim 1, wherein the element is a first net.
10. The method according to claim 9, wherein the first net couples a second net of the original circuit to a voltage source or a ground.
11. The method according to claim 1, wherein the fabricated obfuscated circuit comprises a pad for recovering the output of the original circuit upon the editing of the obfuscated circuit.
12. The method according to claim 11, wherein the pad is a cut pad for disconnecting the element from the original circuit or a contact pad for rerouting the original circuit.
13. The method according to claim 12, wherein the contact pad is connected with the original circuit via a tungsten contact or a platinum contact.
14. The method according to claim 1, wherein the obfuscated circuit comprises a first logic gate selected from a group consisting of NAND, NOR, AND, OR, and XOR.
15. The method according to claim 14, wherein the first logic gate is configured such that a first input of the first logic gate is disconnected from the first logic gate and the disconnected first input is connected to a first input of a second logic gate of the device, and wherein the second logic gate is configured such that a second input originally connected to the first input of the second logic gate is disconnected from the second logic gate and the disconnected second input is connected to the first input of the first logic gate.
16. The method according to claim 15, wherein remaining inputs of the first logic gate and the second logic gate remain connected to the original circuit.
17. The method according to claim 1, wherein the obfuscated circuit comprises a second logic gate selected from a group consisting of an inverter, AND, OR, XOR, NAND and NOR.
18. The method according to claim 17, wherein the second logic gate is configured such that an input of the second logic gate is disconnected from the second logic gate and the original circuit bypasses the second logic gate by making a direct connection to the input.
19. A method for designing a chip comprising:
- forming a netlist for an integrated circuit;
- modifying the netlist, wherein the modifying of the netlist comprises adding an element to the netlist to obfuscate the integrated circuit and to corrupt an intended output of the integrated circuit, and wherein the element comprises at least one of a logic gate or a net;
- fabricating the chip based on the modified netlist; and editing the fabricated chip, wherein the modified netlist is configured to recover the intended output of the integrated circuit upon the editing of the fabricated chip, and wherein the editing of the fabricated chip comprises removing the added element from the fabricated chip.
20. The method according to claim 19, further comprising inserting a design-for-test (DFT) into the modified netlist.
21. The method according to claim 19, wherein the removing of the added element comprises at least one of milling by a focused-ion-beam (FIB) or depositing by the FIB.
22. The method according to claim 21, further comprising generating a layout based on the modified netlist.
23. The method according to claim 22, wherein the modifying of the netlist comprises inserting a logic gate into the netlist or rerouting a pre-existing net.
24. The method according to claim 23, further comprising analyzing obfuscation and forming a list of suitable nets between the forming of the netlist and the modifying of the netlist.
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Type: Grant
Filed: Jun 15, 2017
Date of Patent: Jun 8, 2021
Patent Publication Number: 20190311156
Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED (Gainesville, FL)
Inventors: Mark M. Tehranipoor (Gainesville, FL), Domenic J. Forte (Gainesville, FL), Bicky Shakya (Gainesville, FL), Navid Asadizanjani (Gainesville, FL)
Primary Examiner: Malcolm Cribbs
Assistant Examiner: Stephanie S Ham
Application Number: 16/309,239
International Classification: G06F 21/75 (20130101); G06F 21/76 (20130101); H01L 21/762 (20060101); H01L 23/00 (20060101); G06F 30/39 (20200101); G06F 30/327 (20200101); G06F 30/394 (20200101); G06F 30/333 (20200101);