Circuit and method for sensing an over-current condition of a dual mode voltage converter

Abstract

A current sense circuit (14) is provided which receives a signal indicative of output current flow of an up/down DC-DC converter during up-conversion and down-conversion modes. The current sense circuit provides a logic signal (CS) indicative of the rate of change of the current flow for both modes of operation. A comparator (42) receives a selectable voltage reference generated by voltage reference (36,38,50). A first voltage reference is selected during an increasing current flow (CS=logic high) and a second voltage reference is selected during a decreasing current flow (CS=logic low), thereby regulating the output current (IL) to a fixed average value. If the length of time during continuous current flow of converter (10) exceeds a predetermined amount of time, a signal (FAULT) is issued and externally processed, which subsequently disables converter (10) by an external signal (ENABLE).

Description

FIELD OF THE INVENTION

[0001] The present invention relates, in general, to current sensing devices, and more particularly, to current sensing devices used in continuous current mode, up/down DC-DC converters.

BACKGROUND OF THE INVENTION

[0002] DC to DC converters are essential to providing accurate power delivery to sensitive electronic devices. In particular, devices which are designed to operate from a battery. Virtually all mobile devices such as cellular telephones, pagers and laptop computers, for example, require a regulated power supply, which is usually generated from a battery source, such as a NiCad (nickel-cadmium) or Lithium Ion battery source, for example. The amount of time that a battery is able to supply power to a particular device is directly proportional to the charge storage capacity of the battery and the amount of current required by the device. An imperative feature of any DC to DC converter operating from a battery, therefore, is the capability to not only monitor the amount of current delivered to the device by the converter, but the ability of the converter to detect an over-current or short circuit condition. An over-current condition is an anomaly, usually caused by a short circuit condition at the output of the converter, requiring the converter to detect the anomaly and subsequently shut down the converter in order to preserve battery life. High current peaks can damage batteries such as a lithium ion battery, therefore, current peaks must be limited, not only during normal operation, but during start up as well. DC-DC converters operating from battery power supplies must also have the ability to either provide up conversion or down conversion, depending on the voltage of the battery. Up conversion, for example, is needed for a weak battery which is supplying only 2.7 volts, for example, to a DC-DC converter, which is supplying power to a 5 volt load. Down conversion is needed for a fresh battery delivering 6 volts, for example, to the DC-DC converter supplying power to the 5 volt load.

[0003] Prior art current detectors for up/down DC-DC converters generally are positioned within the converter circuit, such that only high side current detection is possible. High side current detection occurs only for the up conversion state of the DC-DC converter, whereas, current detection is not performed for the low side, or down conversion, mode. A need exists, therefore, to provide current detection and over-current protection in an up/down DC-DC converter, for both high and low side conversion. Over-current limitation must also be provided during the start up phase of the converter. Additionally, average current detection is preferred over peak current detection, to prevent converter shut down during momentary output current surges.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 illustrates a schematic diagram of an up/down, DC-DC converter;

[0005] FIG. 2 illustrates the current sense circuit of FIG. 1; and

[0006] FIG. 3 illustrates the over-current protection of the regulation control circuit of FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 illustrates an up/down, DC-DC converter 10 utilizing Metal Oxide Semiconductor Field Effect Transistors (MOSFET) 24 and 22, in conjunction with inductor 16 and associated regulation control circuits. In general, converter 10 regulates the output voltage Vout to a substantially constant voltage level, while accepting the input voltage Vbatt from a battery. Vout is either regulated to a potential lower than the battery voltage, down conversion, or is regulated to a potential higher than the battery voltage, up conversion.

[0008] In operation, converter 10 accepts an input voltage from a battery at node Vbatt. The battery voltage is typically in the range of approximately 2.7 volts to 6 volts. The output voltage, Vout, is regulated to, for example, 5 volts. Converter 10 is in up-conversion mode for battery voltage, Vbatt, less than 5 volts. Converter 10 is in down-conversion mode for battery voltage, Vbatt, greater than 5 volts. Converter 10 automatically detects the potential relationship between Vbatt and Vout, through the operation of comparator 34. Comparator 34 receives the output voltage at the non-inverting input, from terminal Vout. Comparator 34 receives the battery voltage at the inverting input from terminal Vbatt. Comparator 34 has a built-in input offset voltage equal to approximately 200 millivolts (mV). The offset voltage is required to assure continuous function of converter 10 when Vbatt and Vout are approximately at the same potential. Down-conversion mode requires at least a 200 mV differential between Vbatt and Vout in order to properly function while up-conversion mode can overlap the 200 mV differential range. Comparator 34, in addition, has built in hysteresis, for example 20 mV, which prevents the MODE signal from oscillating between logic high and low voltages when Vbatt and Vout are approximately the same. The conversion mode represented by the MODE signal presented by comparator 34, therefore, is related to input voltages Vbatt and Vout according to Table 1. 1 TABLE 1 Input Voltage Mode Vout >= Vbatt − 200 mV UP-Conversion (Logic High) Vout < Vbatt − 200 mV DOWN-Conversion (Logic Low)

[0009] Down conversion mode of converter 10 exists when the battery voltage, Vbatt, is at a higher potential than Vout. Internal circuitry to switch control logic 20, determines the maximum of the two voltages, Vbatt or Vout, and provides the maximum voltage as logic high levels for signals G1 and G2. At startup, Vout is at ground potential and Vbatt is at, for example, 6 volts. Comparator 34 sets the MODE signal to a logic low value, selecting switch control logic 20 to down-conversion mode. NMOS transistor 24 does not enter into a conductive state while converter 10 is in down conversion mode. PMOS transistor 22 is rendered conductive by switch control logic 20, by selecting G2 to be logic low. The voltage present at the source terminal of PMOS transistor 22 exceeds the threshold voltage of PMOS transistor 22 making PMOS transistor 22 conductive. PMOS transistor 22 is said to be in a first mode of conduction when signal G2 is at a logic low value. The first mode of conduction, or first phase of inductor current, is also indicated by signal CS asserted to a logic high value, indicating an inductor current, IL, lower than a predetermined threshold current Imax, for example, 100 milliamps (mA). Current is conducted by inductor 16, through sense resistor 12 and PMOS transistor 22, to charge capacitor 26. At the beginning of the first phase, the inductor current, IL, is zero. In the first phase, the current in the inductor varies according to the applied voltage VL across the inductor. The inductor current, IL, starts to increase as di/dt=VL/L, where L is the value of inductance associated with inductor 16 and di/dt is the rate of change of current flow through inductor 16. The applied voltage across inductor 16 is approximately equal to VL=VBATT−VOUT−V12−V22, where V12 and V22 are voltages developed across sense resistor 12 and PMOS switch 22, respectively. Capacitor 26 is relatively large, for example, 10uF, so the variation of Vout during one cycle of inductor current is negligible. Current sense 14 senses the current flow through resistor 12, which is equivalent to the current flow through inductor 16, and at a predetermined amount of current flow, Imax, detects a maximum current value. The maximum current value, for example, is predetermined to be 100 mA. Once Imax is detected by current sense 14, signal CS is set to a logic low value by current sense 14, indicating that the predetermined maximum inductor current, Imax, is obtained and a second phase of inductor current begins. Signal G2 is set to a logic high value, approximately equal to Vbatt, since Vbatt is at a potential greater than Vout.

[0010] A logic high value for signal G2, changes the conduction mode of PMOS transistor 22 to a second mode. PMOS transistor 22 is momentarily rendered non-conductive by the mode change. Inductor 16, however, contains stored magnetic energy, which inverts the voltage polarity across inductor 16 to create a voltage rise from node 28 to node 30. The potential at node 30, the source terminal of PMOS transistor 22, exceeds the threshold voltage of PMOS transistor 22, since the gate terminal of PMOS transistor 22 is set to approximately Vbatt by signal G2 and the source terminal exceeds Vbatt by at least the threshold voltage of PMOS device 22. The polarity of the inductor voltage inverts, which changes the sign of the di/dt term for the equation of VL above, creating a decreasing inductor current. The second mode of operation renders PMOS transistor 22 conductive once again, but the inductor current is now decreasing from the predetermined maximum value of current flow, Imax, toward a predetermined minimum value of current flow, Imin. Once the current flow has decreased to Imin, for example 50 mA, current sense 14 asserts signal CS to a logic high value and switch control logic 20, de-asserts signal G2 (becoming again logic low), rendering PMOS transistor 22 conductive in the first conduction mode. It can be seen, therefore, that PMOS transistor 22 alternates between two modes of conduction states. The first mode of conduction of PMOS transistor 22 creates an increasing inductor current, IL, indicating a first phase of the inductor current waveform and the second mode of conduction of PMOS transistor 22 creates a decreasing inductor current, indicating a second phase of the inductor current waveform. The inductor current waveform increases from Imin to Imax during a first phase of the current waveform and decreases from Imax to Imin during a second phase of the current waveform. While converter 10 is supplying drive current to the load connected to terminal Vout (not shown), during first or second phases of the inductor current waveform, converter 10 is said to be in a constant current mode of operation. Signal RUN is asserted to a logic high value by regulation control 18 during the constant current mode of operation.

[0011] Since converter 10 is in a down-conversion mode, Vout is regulated to some potential below Vbatt-200 mV. Converter 10, for example, regulates from voltage Vbatt approximately equal to 6 volts to voltage Vout approximately equal to 5 volts. Once the output voltage Vout has reached the predetermined output voltage of 5 volts, for example, converter 10 changes to a skip mode of operation. Skip mode of operation is defined to be a mode of operation whereby no current is conducted by inductor 16 and the inductor current, IL, falls to 0 amps. The energy stored in capacitor 26 supplies power to the load (not shown) connected to node Vout. The skip mode of operation is set by regulation control 18, via signal RUN, when Vout has obtained a predetermined voltage value. Signal RUN is set to a logic high value to enable constant current mode of operation for converter 10 and is set to a logic low value to enable skip mode operation.

[0012] As discussed above, Vbatt is a voltage supply potential derived from a battery. The magnitude of Vbatt decreases as the amount of charge contained within the battery decreases. As the magnitude of Vbatt decreases below the voltage required at terminal Vout, converter 10 automatically changes conversion mode from down-conversion to up-conversion. Comparator 34 asserts signal MODE to a logic high value and switch control logic 20 activates signals G1 and G2 accordingly as needed for up-conversion. Internal circuitry to switch control logic 20 determines Vout is the maximum voltage as compared to Vbatt and asserts signals G1 and G2 with logic high voltage levels equal to Vout, as opposed to Vbatt, accordingly.

[0013] Up-conversion mode engages both NMOS transistor 24 and PMOS transistor 22. At startup, Vout is at ground potential and Vbatt is at, for example, 3 volts. Since Vout is at a potential lower than Vbatt, the MODE signal is at a logic low value, which indicates down-conversion mode. The voltage at Vout increases as described earlier for down-conversion mode at start up. As the output voltage at node Vout increases to a voltage approximately equal to Vbatt-200 mV, the MODE signal reverses from indicating down-conversion mode to indicating up-conversion mode, or a logic high value. Regulation control 18 maintains the RUN signal to a logic high value, since the output voltage has not yet reached the predetermined value of, for example, 5 volts. Once the MODE signal has transitioned to indicate up-conversion mode, switch control logic 20 asserts signal G1 accordingly. As converter 10 transitions from down to up-conversion mode, the voltage at terminal Vout approximates Vbatt-200 mV. Signals G1 and G2 are asserted to a logic high, or Vout, rendering NMOS transistor 24 conductive and PMOS transistor 22 non-conductive. Inductor 16 continues to store magnetic energy as the inductor current waveform continues to increase from Imin to Imax, which are predetermined values set by current sense 14 as described earlier. NMOS transistor 24 conducts the inductor current until the inductor current reaches Imax. Once the inductor current reaches Imax, NMOS transistor 24 is rendered non-conductive by switch control logic 20 by de-asserting signal G1 to a logic low value and PMOS transistor 22 is rendered conductive by de-asserting signal G2 to a logic low value. The voltage developed across inductor 16 inverts, maintaining a source voltage at PMOS transistor 22 which exceeds the threshold voltage of PMOS transistor 22. Since PMOS transistor 22 is conductive, inductor 16 continues to supply drive current to charge capacitor 26, with decreasing drive current towards Imin, consistent with phase two of the current waveform discussed above. Once the current waveform has reached Imin, phase one of the current waveform repeats to continue the continuous current mode of operation. The voltage across capacitor 26, Vout, continues to increase toward the predetermined value set by regulation control 18, for example, 5 volts. Once the output voltage has reached 5 volts, regulation control 18 de-asserts signal RUN, programming converter 10 to a skip mode of operation, whereby no current is conducted by either NMOS transistor 24 or PMOS transistor 22. The energy stored in capacitor 26 delivers the required power to the load connected to node Vout (not shown). Once the voltage at node Vout has transitioned below a predetermined value set by regulation control 18, signal RUN is asserted by regulation control 18 and continuous current mode resumes.

[0014] Over-current protection is provided by converter 10, in conjunction with microprocessor 32. Inductor current, IL, as discussed above, oscillates between phase one (increasing current) and phase two (decreasing current). Converter 10 is said to be operating in a continuous current mode of operation while the inductor current oscillates between first and second phases. Converter 10 is designed to prohibit a continuous current mode of operation, if the continuous current mode of operation persists longer than a predetermined amount of time. Regulation control 18 asserts signal RUN, when converter 10 is operating in the continuous current mode. A timer, located within regulation control 18, is enabled by a low to high transition of the signal RUN. The timer has a predetermined timeout value which is programmed to, for example, 4 milliseconds (mS). If the RUN signal is not de-asserted by regulation control 18 within the 4 mS time period, the timer expires and signal FAULT transitions from a low to a high logic value. Microprocessor 32 responds to the FAULT signal by de-asserting signal ENABLE. Once signal ENABLE has transitioned to a logic low value, signal RUN is de-asserted and converter 10 immediately transitions to stop mode. Signal FAULT is de-asserted to a logic low value and microprocessor 32 performs supervisory functions to report the fault condition. Restart by setting ENABLE logic high is possible, but if the overload condition, for example an output short persists after 4 ms, the FAULT flag is asserted once again.

[0015] FIG. 2 illustrates a detailed schematic of current sense 14. Current sense circuit 14 comprises a voltage reference implemented by resistors 36 and 38 coupled together in series at node 46. A first terminal of resistor 36 is coupled to the Vi terminal. A second terminal of resistor 36 is coupled to a first terminal of resistor 38 at node 46. A second terminal of resistor 38 is coupled to a first terminal of current source 50 at node 48. A second terminal of current source 50 is coupled to, for example, ground potential. A first input terminal of switch 40 is coupled to node 46 and a second input terminal of switch 40 is coupled to node 48. A control terminal of switch 40 is coupled to the Q output of flip-flop 44. The output of switch 40 is coupled to the inverting input of comparator 42. The non-inverting input of comparator 42 is coupled to terminal Vs. The output of comparator 42 is coupled to both the S and R inputs of flip-flop 44.

[0016] In operation, current sense circuit 14 compares the sense voltage at node Vs to one of two reference voltages at nodes 46 and 48. The reference voltage developed at node 46 is equal to VREF46=Vi−I50*R36, where Vi is equal to Vbatt, I50 is the current conducted by current source 50 and R36 is the resistance value of resistor 36. The reference voltage at node 48 is VREF48=Vi−I50*(R36+R38) where R38 is the resistance value of resistor 38. At start up, Vs is equal to Vbatt, since inductor current, IL, is zero. The voltage at the non-inverting input to comparator 42 is more positive than the inverting input to comparator 42, which causes the output of comparator 42 to transition to a logic high level. A logic high level at the S input to flip-flop 46 sets the Q output of flip-flop 46 to a logic high level at terminal CS. Switch 40 position as shown in FIG. 2 selects VREF48, which indicates that the inductor current is increasing and that the current waveform is in the first phase. As the inductor current increases, Vs decreases, since the voltage drop across resistor 12 increases. Once Vs falls below VREF48, the non-inverting input to comparator 42 is more negative than the inverting input to comparator 42, which causes the output of comparator 42 to transition to a logic low level, signaling phase 2 of the inductor current waveform. A logic low level activates the reset input of flip flop 44 and causes the Q output of flip flop 44 to transition to a logic low level at terminal CS. A logic low level at terminal CS causes switch 40 to select reference voltage VREF46, causing the inverting input to comparator 42 to be more positive than the non-inverting input, which maintains the logic low level at the output of comparator 42. Once the inductor current waveform transitions to phase 2, the voltage at terminal Vs has reached a minimum value and begins to increase, due to the voltage inversion across inductor 16 as discussed above. Once the voltage at terminal Vs increases above VREF46, the output of comparator 42 transitions to a logic high level, which sets the Q output of flip flop 44 at terminal CS to a logic high level. Switch 40 then selects VREF48, and phase 1 of the inductor current waveform repeats. It can be seen, therefore, that the appropriate selection of resistance values of R36 and R38 accurately sets the minimum inductor current, Imin, and maximum inductor current, Imax, values for continuous current mode of operation.

[0017] It should be noted that converter 10 provides a first mode of over-current protection utilizing current sense 14 in combination with switch control logic 20. As discussed above, current sense 14 provides a logic signal CS which indicates first and second phases of the inductor current waveform. A logic high value for CS indicates an increasing inductor current, IL, and a logic low value for CS indicates a decreasing inductor current. Switch control logic 20 controls current switches 22 and 24 according to the value of signal CS, causing the inductor current to reverse phases when logic signal CS reverses logic levels, regardless of the state of the load connected to Vout (not shown). In other words, the inductor current enters phase two, or decreases in magnitude, when the inductor current has reached a value equal to Imax, regardless of the logic level of signal RUN. Signal RUN, as discussed earlier, is asserted as long as voltage Vout has not obtained a predetermined magnitude set in regulation control 18. Current sense signal CS, therefore, overrides signal RUN to invoke over-current protection of converter 10 in all phases of operation of converter 10. By regulating the magnitude of the inductor current, IL, between minimum and maximum values, the inductor current is maintained at a fixed average value during the continuous mode of operation of converter 10.

[0018] FIG. 3 illustrates a detailed schematic diagram of regulation control 18, which contains over-current protection circuitry. One input of AND gate 54 is coupled to the ENABLE terminal and the EN input of regulator 52. A first terminal of resistor 56 is coupled to terminal FB and a second terminal of resistor 56 is coupled to a first terminal of resistor 58 and the inverting input of comparator 60. The non-inverting input to comparator 60 is coupled to the reference voltage output of regulator 52, VREF. The output of comparator 60 is coupled to a second input of AND gate 54. The output of AND gate 54 is coupled to the RUN terminal, the EN input of timer 62 and the RST input of timer 62. The output of timer 62 is coupled to terminal FAULT.

[0019] FIG. 3 provides a second mode of over-current protection for converter 10. In operation, the signal present at the ENABLE terminal is asserted by microprocessor 10 to a logic high value. The voltage at terminal Vout, is coupled to terminal FB and divided by resistor network 56 and 58. Reference voltage Vref is set by regulator 52 such that the output of comparator 60 is at a logic high value when the inverting input to comparator 60 is at a voltage less than Vref. The output of comparator 60 is at a logic low value when the inverting input of comparator 60 is at a voltage greater than Vref. Vref is set such that the output voltage, Vout, is regulated to, for example, 5 volts. Signal RUN is asserted by regulation control 18 when both the ENABLE signal and the output of comparator 60 are at logic high levels. In other words, converter 10 is in RUN mode, when microprocessor 32 has enabled converter 10 and the regulated voltage at terminal Vout is lower than the predetermined output voltage set by Vref, for example, 5 volts. Conversely, converter 10 is not in RUN mode for one of two reasons:

[0020] 1.) Normal regulation has sufficiently charged capacitor 26 to the required regulated voltage causing the output of comparator 60 to transition to a logic low value, which causes the RUN signal to be de-asserted and causes converter 10 to transition to skip mode; or

[0021] 2.) Timer 62 has expired and has asserted signal FAULT which is read by microprocessor 32. Microprocessor 32, subsequently de-asserts the ENABLE signal, thereby programming converter 10 to stop mode. Microprocessor 32 has the ability to program the converter to stop mode for a multitude of conditions, depending upon the application.

[0022] Timer 62 receives signal RUN at the EN and RST terminals. A low to high transition at terminal EN, enables a countdown sequence of timer 62 to commence. A predetermined timer value is set to, for example, 4 mS. If converter 10 has not achieved an acceptable potential at terminal Vout through continuous current regulation as discussed above within 4 mS, timer 62 expires, asserting signal FAULT. Microprocessor 32 reacts to signal FAULT by de-asserting signal ENABLE, thereby programming converter 10 to stop mode. Stop mode, as discussed above, prohibits current conduction through either transistors 22 or 24. The inductor current, IL, then reduces to zero in response to the stop mode of operation. Re-assertion of signal ENABLE by microprocessor 32 causes converter 10 to transition to start up mode as discussed above. An over-current condition is therefore predetermined to be any condition which causes continuous current regulation for longer than the predetermined timer value, for example, 4 mS.

[0023] By now it should be appreciated that a current sense circuit and over-current protection for an up/down DC-DC converter has been provided. An advantage of the current sense circuit provides a method to accurately set a minimum and a maximum value of inductor current during a continuous current mode of regulation. An advantage of the over-current protection is to preserve the life span of batteries such as lithium ion batteries, which exhibit shortened life spans due to current surges. An additional advantage of the over-current protection is the external detection of the over-current condition which allows a device, such as a microprocessor, to report the condition.

Claims

1. In a power supply, a regulator circuit operating in a continuous mode of operation to provide an output signal operating between minimum and maximum values in response to a sense signal, the regulator circuit comprising:

a sense circuit coupled to receive an input signal and coupled to provide the sense signal; and

a control circuit coupled to receive the sense signal and a feedback signal and coupled to provide a fault signal indicative of the duration of the output signal and a run signal in response to the feedback signal.

2. The regulator circuit of claim 1 wherein the sense circuit comprises:

a reference circuit coupled to receive the input signal and coupled to provide first or second reference signals in response to the sense signal; and

a reference control circuit coupled to receive the first or second reference signals and an output coupled to provide the sense signal.

3. The regulator circuit of claim 2 wherein the reference circuit comprises:

a resistive network coupled to receive the input signal and having first and second nodes coupled to provide the first and second reference signals; and

a switch having first and second inputs coupled to receive the first and second reference signals and a control input coupled to receive the sense signal.

4. The regulator circuit of claim 2 wherein the reference control circuit comprises:

a comparator having a first input coupled to receive the first or second reference signals in response to the sense signal and a second input coupled to receive a signal indicative of current flow; and

a memory storage device having first and second inputs coupled to receive an output of the comparator and an output coupled to provide the sense signal.

5. The regulator circuit of claim 4 wherein the memory storage device includes an RS flip flop.

6. The regulator circuit of claim 1 wherein the control circuit comprises:

a regulation control circuit coupled to receive the feedback signal and coupled to provide the run and fault signals; and

a switch control circuit coupled to receive the sense and run signals and coupled to control the continuous mode of operation.

7. The regulator circuit of claim 6 wherein the regulation control circuit comprises:

a comparator having a first input coupled to receive the feedback signal and a second input coupled to receive a voltage reference signal;

a logic circuit having a first input coupled to receive an enable signal, a second input coupled to receive an output of the comparator and an output coupled to provide the run signal; and

a timer circuit having first and second inputs coupled to receive the run signal and an output coupled to provide the fault signal.

8. The regulator circuit of claim 7 wherein the logic circuit includes an AND gate.

9. A regulator operating in first and second modes receiving an input signal and providing an output control signal in response to a feedback signal, the regulator comprising:

a mode control circuit coupled to receive the feedback signal and an external control signal and coupled to provide a mode signal indicative of the first and second modes; and

a regulation circuit coupled to receive the mode signal and the input signal and coupled to provide the output control signal in response to the first mode of operation.

10. The regulator of claim 9 wherein the mode control circuit comprises:

a comparator having a first input coupled to receive the feedback signal and a second input coupled to receive a reference signal;

a logic circuit having a first input coupled to receive the external control signal, a second input coupled to receive an output of the comparator and an output coupled to provide the mode signal; and

a timer circuit having first and second inputs coupled to receive the mode signal and an output coupled to provide a fault signal indicative of the second mode of operation.

11. The regulator of claim 10 wherein the logic circuit includes an AND gate.

12. The regulator of claim 9 wherein the regulation circuit comprises:

a current sense circuit coupled to receive the input signal and a signal indicative of current flow; and

a switch control circuit coupled to receive the mode signal and an output of the current sense circuit and coupled to provide the output control signal.

13. The regulator of claim 12 wherein the current sense circuit comprises:

a reference circuit coupled to receive the input signal and coupled to provide a first and a second reference signal; and

a reference control circuit coupled to receive the first or second reference signal and an output coupled to provide a current sense signal.

14. The regulator circuit of claim 13 wherein the reference circuit comprises:

a resistive network coupled to receive the input signal and having first and second nodes coupled to provide the first and second reference signals; and

a switch having first and second inputs coupled to receive the first and second reference signals and a control input coupled to receive the current sense signal.

15. The regulator of claim 13 wherein the reference control circuit comprises:

a comparator having a first input coupled to receive the first or second reference signals in response to the current sense signal and a second input coupled to receive the signal indicative of current flow; and

a memory storage device having first and second inputs coupled to receive an output of the comparator and an output coupled to provide the current sense signal.

16. The regulator circuit of claim 15 wherein the memory storage device includes an RS flip flop.

17. A method of operating a continuous mode regulator, comprising:

sensing a phase of an output signal;

providing a signal indicative of the phase of the output signal; and

controlling the output signal in response to the phase of the output signal.

18. The method of claim 17 wherein sensing the phase of the output signal comprises:

providing first and second reference signals; and

comparing a signal indicative of current flow to the first and second reference signals.

19. The method of claim 17 wherein controlling the output signal comprises controlling the conduction state of a first switch and a second switch in response to the phase of the output signal.

20. A method of providing over-current protection in a continuous mode regulator, comprising:

initiating a first mode of operation;

monitoring the first mode duration; and

initiating a second mode of operation if the first mode duration exceeds a predetermined value.

21. The method of claim 20 wherein initiating a first mode of operation comprises:

comparing an output signal with a predetermined reference signal; and

initiating the first mode of operation when the output signal is less than the predetermined reference signal.

22. The method of claim 20 wherein monitoring the first mode duration comprises activating a timer after initiating the first mode of operation.

23. The method of claim 20 wherein initiating a second mode operation comprises:

activating a fault signal; and

receiving an external disable signal in response to the fault signal.

24. A method of providing over-current protection in a regulator, comprising:

measuring a duration of a continuous mode of operation;

maintaining an average output current during the continuous mode of operation; and

forcing the output current to a minimum value if the continuous mode of operation exceeds a predetermined maximum duration.

25. The method of claim 24 wherein maintaining the average output current comprises:

increasing the output current magnitude when the output current substantially equals a first value; and

decreasing the output current magnitude when the output current substantially equals a second value.

26. The method of claim 24 wherein forcing the output current to a minimum value comprises:

asserting a fault signal; and

receiving an external disable signal in response to the fault signal.