MICROPROCESSOR SELF-POWER DOWN CIRCUIT

Abstract

A self-power down circuit for a controller coupled to a battery to obtain power from the battery. The controller has a port, the state of which changes during powering up of the controller. The circuit includes a first switching device including a main current conducting path and a control terminal. The control terminal of the first switching device is coupled to the port for monitoring the state of the port. The circuit further includes a second switching device including a main current conducting path and a control terminal, and a switch. The port is coupled to the battery through the main current conducting path of the second switching device. The control terminal of the second switching device is coupled to the switch for actuation by actuation of the switch. The control terminal of the second switching device is also coupled to the main current conducting paths of the first and second switching devices through first and second voltage dropping elements, respectively.

Description

FIELD OF THE INVENTION

[0001] This invention relates to circuits for controlling the powering down of microcontroller-, microprocessor-, and microcomputer-controlled instruments.

BACKGROUND OF THE INVENTION

[0002] Several systems for regulating or controlling the supply of power to microcontrollers, microprocessors and microcomputers, sometimes collectively referred to hereinafter as &mgr;Cs, and other types of circuits in instruments for monitoring or testing the concentrations of medically significant components of body fluids and the like. Such systems are illustrated in, for example, U.S. Pat. Nos. 4,698,530; 4,713,555; 4,868,832; 4,951,171; 4,963,814; 5,010,469; 5,117,324; 5,341,034; 5,594,906; and, 5,792,944. There are also the systems described in Sherman, Len and Doug Vargha, “Optimize Microprocessor Supervisory Circuits,” Electronic Design, vol. 42, no. 18, 1994, pp. 67-76. No representation is intended that a complete search has been made of the prior art or that no better art references than those listed here exist, nor should any such representation be inferred. This listing shall not be construed to be an admission that the listed references are, or are considered to be, material to patentability, nor should any such admission be inferred.

[0003] &mgr;Cs that have power down modes typically draw a small amount of current when they are powered down. The lifetimes of batteries in battery operated devices of this type are compromised by this current drain during times of inactivity. Three commonly employed techniques for reducing the current drain on a battery during times of inactivity in this type of application are: the use of a toggle switch only, which requires the operator to turn the circuit off in order to be effective; the use of the &mgr;C power down mode, which consumes power, thus reducing the life of a battery used to power the instrument; and, the use of a power supervisor circuit which also consumes power, thus reducing battery life.

DISCLOSURE OF THE INVENTION

[0004] According to the invention, a self-power down circuit is provided for a circuit including a battery and a controller coupled to the battery to obtain power from the battery. The controller has a port, the state of which changes during powering up of the controller. The circuit includes a first switching device including a main current conducting path and a control terminal. The control terminal of the first switching device is coupled to the port for monitoring the state of the port. The circuit further includes a second switching device including a main current conducting path and a control terminal, and a switch. The port is coupled to the battery through the main current conducting path of the second switching device. The control terminal of the second switching device is coupled to the switch for actuation by actuation of the switch. The control terminal of the second switching device is also coupled to the main current conducting paths of the first and second switching devices through first and second voltage dropping elements, respectively.

[0005] Illustratively according to the invention, the first switching device includes a first field effect transistor (FET). The main current conducting path of first FET includes its drain and source terminals. The control terminal of the first FET is its gate terminal.

[0006] Further illustratively according to the invention, the main current conducting path of the first FET is coupled to a first terminal of the switch. A second terminal of the switch is coupled to the control terminal of the second switching device.

[0007] Additionally illustratively according to the invention, the main current conducting path of the first FET is coupled through the first voltage dropping element to the first terminal of the switch.

[0008] Illustratively according to the invention, the first voltage dropping element includes a first voltage dropping element resistor.

[0009] Illustratively according to the invention, the second switching device includes a second FET. The main current conducting path of the second FET includes its drain and source terminals. The control terminal of the second FET is its gate terminal.

[0010] Further illustratively according to the invention, the second voltage dropping element includes a second voltage dropping element resistor. The gate of the second FET is coupled through the second voltage dropping element resistor to one of the source and drain of the first FET.

[0011] Additionally illustratively according to the invention, the main current conducting path of the first FET is coupled to a first terminal of the switch. A second terminal of the switch is coupled to the gate of the second FET.

[0012] Illustratively according to the invention, the main current conducting path of the first FET is coupled through the first voltage dropping element to the first terminal of the switch.

[0013] Illustratively according to the invention, the port is coupled through a software switch, a voltage regulator and the main current conducting path of the second switching device to the battery.

[0014] Further illustratively according to the invention, the port includes a port of one of a microcontroller, microprocessor or microcomputer.

BRIEF DESCRIPTION OF THE DRAWING

[0015] The invention may best be understood by referring to the following detailed description and the accompanying drawing which illustrates the invention. The drawing illustrates a partly block and partly schematic diagram of a circuit incorporating the invention.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

[0016] In the description that follows, a circuit schematic and block diagram is described. Specific components, specific sources, and in some cases, specific terminal, pin and port names and numbers of those components will be provided. However, it is to be understood that other components capable of performing equivalent functions to those specifically identified components may be available from the same, or different, sources, and that the various terminals, pins and ports of any such equivalent components may have different names and numbers. Thus, this invention is not limited to the specifically identified components or the specifically identified sources.

[0017] The circuit of the present invention removes all power from the &mgr;C, under software control, such that the standby current is below the level of practical measurement. This circuit utilizes a series enhancement mode metal oxide semiconductor field effect transistor, or MOSFET, hereinafter more simply abbreviated FET, that breaks the path of power supply current to the voltage regulator. This is initialized by a toggle switch. If the user leaves the circuit active for a period of time, determined in the &mgr;C software, the microcontroller can break the circuit by activating a second FET which controls the gate of the first FET. The circuit must then be reset by deactivating the toggle switch.

[0018] Referring now to the FIGURE, an instrument 10 of the type described above is powered from a battery 100, for example, a 9V battery. The drain of an FET 102 is coupled to one terminal of battery 100. FET 102 illustratively is a type BSS110 FET. The other terminal of battery 100 is coupled to the instrument 10 common, or ground. The gate of FET 102 is coupled through a 1 M&OHgr; resistor to its drain. The gate of FET 102 is also coupled to the pole of a SPDT on/off switch 104. One throw of switch 104 is coupled through a 0.1 &mgr;F capacitor 106 to ground. The other throw of switch 104 is coupled through a 100 &OHgr; resistor to ground. The source of FET 102 is coupled to an input terminal of a voltage regulator integrated circuit (IC) 108, the output terminal of which is coupled to the power supply terminal, for example, the VDD terminal, of a &mgr;C 110 to supply operating voltage to the &mgr;C 110. IC 108 illustratively is a type 78L05 voltage regulator IC and &mgr;C 110 illustratively is a 5V type 8051 &mgr;C. In the illustrative example, a port 111 other than port 0 of &mgr;C 110 is coupled through a 1 K&OHgr; resistor to the gate of an FET 112. The gate of FET 112 is also coupled to ground through a 1 &mgr;F capacitor. The drain of FET 112 is coupled through a 100 &OHgr; resistor to the common terminal of switch 104 and capacitor 106. The source of FET 112 is coupled to ground. FET 112 illustratively is a type BSS98 FET.

[0019] In operation, if it is first assumed that the instrument 10 is off, switch 104 is operated to activate the instrument 10. The gate of FET 102 is coupled through capacitor 106 to ground. As a result, the potential on the gate of FET 102 is pulled negative with respect to its source, and FET 102 is rendered conductive. Voltage is supplied from battery 100 via FET 102 and voltage regulator 108 to &mgr;C 110. &mgr;C 110 is turned on, and its port P is raised to a positive potential. This positive potential is coupled to the gate of FET 112, rendering FET 112 conductive. This results in capacitor 106 being discharged, conditioning the instrument 10 for the next turn-on cycle. It further results in FET 102 being held in conduction. When &mgr;C 110 times out under software control, port P is returned to a potential that will not hold FET 112 in conduction. As a result, the gate of FET 102 is returned to its source potential, and FET 102 is rendered non-conductive, removing the VDD operating potential from &mgr;C 110. The circuit is turned off. Of course, it should be recognized that throwing switch 104 to the “off” position illustrated in the FIGURE will also result in the instrument 10 being turned off.

Claims

1. A self-power down circuit for a circuit including a battery, a controller coupled to the battery to obtain power from the battery, the controller having a port, the state of which changes during initialization of the controller, the circuit including a first switching device including a main current conducting path and a control terminal, the control terminal coupled to the port for monitoring the state of the port, a second switching device including a main current conducting path and a control terminal, and a switch, the port being coupled to the battery through the main current conducting path of the second switching device, the control terminal of the second switching device being coupled to the switch for actuation by actuation of the switch, the control terminal of the second switching device also coupled to the main current conducting paths of the first and second switching devices through first and second voltage dropping elements, respectively.

2. The apparatus of claim 1 wherein the first switching device includes a first field effect transistor (FET), the main current conducting path of which includes its drain and source terminals, and the control terminal of which is its gate terminal.

3. The apparatus of claim 2 wherein the main current conducting path of the first FET is coupled to a first terminal of the switch, a second terminal of the switch being coupled to the control terminal of the second switching device.

4. The apparatus of claim 3 wherein the main current conducting path of the first FET is coupled through the first voltage dropping element to the first terminal of the switch.

5. The apparatus of claim 4 wherein the first voltage dropping element includes a first voltage dropping element resistor.

6. The apparatus of claim 2 wherein the second switching device includes a second FET, the main current conducting path of which includes its drain and source terminals, and the control terminal of which is its gate terminal.

7. The apparatus of claim 6 wherein the second voltage dropping element includes a second voltage dropping element resistor, the gate of the second FET being coupled through the second voltage dropping element resistor to one of the source and drain of the first FET.

8. The apparatus of claim 7 wherein the main current conducting path of the first FET is coupled to a first terminal of the switch, a second terminal of the switch being coupled to the gate of the second FET.

9. The apparatus of claim 8 wherein the main current conducting path of the first FET is coupled through the first voltage dropping element to the first terminal of the switch.

10. The apparatus of claim 1 wherein the port is coupled through a software switch, a voltage regulator and the main current conducting path of the second switching device to the battery.

11. The apparatus of claim 2 wherein the port is coupled through a software switch, a voltage regulator and the main current conducting path of the second switching device to the battery.

12. The apparatus of claim 3 wherein the port is coupled through a software switch, a voltage regulator and the main current conducting path of the second switching device to the battery.

13. The apparatus of claim 4 wherein the port is coupled through a software switch, a voltage regulator and the main current conducting path of the second switching device to the battery.

14. The apparatus of claim 5 wherein the port is coupled through a software switch, a voltage regulator and the main current conducting path of the second switching device to the battery.

15. The apparatus of claim 6 wherein the port is coupled through a software switch, a voltage regulator and the source and drain of the second FET to the battery.

16. The apparatus of claim 7 wherein the port is coupled through a software switch, a voltage regulator and the source and drain of the second FET to the battery.

17. The apparatus of claim 8 wherein the port is coupled through a software switch, a voltage regulator and the source and drain of the second FET to the battery.

18. The apparatus of claim 9 wherein the port is coupled through a software switch, a voltage regulator and the source and drain of the second FET to the battery.

19. The apparatus of claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 or 18 wherein the port includes a port of one of a microcontroller, microprocessor or microcomputer.