Transistor structures and processes for forming same
Source drain on insulator (SDOI) transistors and methods of forming SDOI transistors are described. The SDOI transistors are formed to provide electrical isolation between the body and the channel of the transistor. The electrical isolation comprises either a depletion layer or a p-n junction formed below the SDOI transistor channel region that spans laterally between the SDOI insulators.
This application is a divisional to U.S. patent application Ser. No. 10/463,159, filed Jun. 17, 2003.
FIELD OF THE INVENTIONThis invention relates to a semiconductor device and fabrication thereof and, more particularly, to Source-Drain On Insulator (SDOI) transistor structures and fabrication methods thereof.
BACKGROUND OF THE INVENTIONSemiconductor devices utilize Source-Drain On Insulator (SDOI) transistors for various applications. An SDOI transistor is a high performance transistor that has a very low junction capacitance, comparable to that of a Silicon On Insulator (SOI) transistor, but doesn't possess a floating body effect that is prevalent in SOI transistors.
The floating body effect of an SOI transistor has some advantages and some disadvantages. On the positive side, it results in higher current drive and better substrate-threshold voltage (VT) swing (body effect is defined as VT sensitivity to body voltage drop (Vb)). On the negative side it can result in history effect and high off-state current leakage. It is advantageous to use SOI transistors on circuits that need high current drive and are tolerant to off-state current leakage. However, for other circuits, such as pass gate logic, the floating body effect will cause problems.
One example of the undesirable operations the floating body effect may cause in a pass logic gate may be seen in an example wherein: Vc equals the control voltage, Vt equals the transistor threshold voltage, and Vb equals the body voltage. During the “on” state the gate is at Vc, the source is at Vc, the drain is at Vc−VT, and the body is at approximately Vc−VT. When the device is switched to the “off” state, the gate goes to zero volts, the source stays at Vc and the body goes to Vb˜Vc/2 (i.e., the history effect). When the drain switches to zero volts, the n+junction between the source and the body becomes forward biased and will draw large bipolar current (i.e., undesirable high current drive).
The present invention addresses various characteristics of devices, such as an SOI transistor, and particularly addresses such issues as history effect and high current drive. A significant focus of the present invention comprises SDOI field effect transistor structures and fabrication methods thereof, which will become apparent to those skilled in the art from the following disclosure.
SUMMARY OF THE INVENTIONAn exemplary implementation of the present invention includes source-drain on insulator (SDOI) transistor structures (n-channel and p-channel transistor structures) comprising a buried depletion layer under the channel region, which provides electrical isolation between the body and the channel of each transistor structure.
Another exemplary implementation of the present invention include source-drain on insulator (SDOI) transistor structures (n-channel and p-channel transistor structures) comprising a buried p-n junction under the channel region, which provides substantial (if not complete) electrical isolation between the body and the channel of each transistor structure.
In one exemplary implementation, an SDOI transistor structure is formed by creating electrical isolation below the SDOI transistor channel region that spans completely between the SDOI insulators. The electrical isolation may be formed by implanting an appropriate conductive dopant to form a depletion layer below the channel region.
In an alternate exemplary implementation, the electrical isolation may be formed by implanting an appropriate conductive dopant to form a p-n junction below the channel region of an SDOI transistor structure that spans completely between SDOI insulators.
BRIEF DESCRIPTION OF THE DRAWING
The following exemplary implementations are in reference to SDOI transistor structures and the fabrication thereof in a semiconductor assembly. While the concepts of the present invention are conducive to the fabrication of an SDOI transistor for a semiconductor logic device the concepts taught herein may be applied to other semiconductor devices that would likewise benefit from the use of the SDOI transistor structure and processes disclosed herein. Therefore, the depictions of the present invention in reference to a pass SDOI transistor structure or a semiconductor logic device SDOI transistor structure and the manufacture thereof, are not meant to so limit the extent to which one skilled in the art may apply the concepts taught hereinafter.
In the following description, the terms “wafer” and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-saphire, germanium, or gallium arsenide, among others.
A first exemplary fabrication of an embodiment the present invention is depicted in
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After selective epi silicon deposition, amorphous silicon 61 is deposited to cover exposed oxide regions 40, epi silicon structures 60 and exposed nitride 31. An amorphous silicon deposition to form amorphous silicon layer 61 may be accomplished by decomposing SiH4 at approximately 500° C. A preferred amorphous silicon thickness is 2000 to 3000 Angstroms.
Referring now to
Next, photoresist 70 is placed and patterned to allow for a following n-depletion layer implant to form n-depletion layer 71 at the base of and extending between oxide regions 40. N-depletion layer 71 serves an important function in this exemplary embodiment of the present invention as it provides electrical isolation between the transistor body (resident in PWell 23) and p-region 72. P-region 72 will function as the channel for the SDOI transistor structure.
N-depletion layer 71 functions properly when the depth of the n-depletion is such that it completely spans between laterally spaced oxide regions 40 and yet is sufficiently deep to avoid hindering proper operation of an overlying channel region. As an example of a preferred implementation of the present invention, performing an n-depletion implant into PWell 23, with oxide regions 40 having a thickness of approximately 2800 Angstroms, a Phosphorus implant dose of approximately 5×1011 to 1×1012 Atoms/cm2, with an implant energy of approximately 180 KeV, will obtain the desired implant depth for the n-type depletion layer 71. In order to maintain an effective n-depletion layer 71, the thickness of oxide regions 40 should be in the order of 2500 Angstroms or greater.
The body to channel isolation provided by n-type depletion layer 71 improves the transistor's sub-threshold swing and reduces the substrate-bias coefficient. The improvement basically is accomplished by reducing the capacitive coupling between the transistor channel and the transistor body with the insertion of depletion capacitance therebetween by the depletion layer. The method is not dependent on channel length or the desired threshold voltage (VT) of the finished transistor as the method is independent of the horizontal dimension of the device. Therefore, the method does not require an angled implant to adjust VT although if so desired, one may be performed without altering the effectiveness of n-depletion 71 spanning between the bottoms of the shallow trench isolation 40.
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A second exemplary fabrication of an embodiment of the present invention is depicted in
The process steps depicted in
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The p-n junction functions properly when the depth of p-n junction 111 is such that it completely spans between laterally spaced oxide regions 40 and is also sufficiently deep to avoid hindering proper operation of an overlying channel region. For example, with oxide regions 40 having a thickness of approximately 2800 Angstroms, performing a PWell implant into NWell 23 requires a Boron implant dose of approximately 5×1012 Atoms/cm2, with an implant energy of approximately 30 KeV.
In the case of an n-type silicon substrate being selected (the NWell implant is not preformed), once the PWell implant is performed a p-n junction will be formed at the base of and extending between laterally spaced oxide regions 40. The desired effect of the p-n junction is attained and the NWell implant is not necessary (though it may be implemented if so desired).
The body to channel isolation provided by p-n junction 111 improves the transistor's sub-threshold swing and reduces the substrate-bias coefficient. The improvement basically is accomplished by reducing the capacitive coupling between the transistor channel and the transistor body with the insertion of depletion capacitance therebetween by the p-n junction. The method is not dependent on channel length or the desired threshold voltage (VT) of the finished transistor as the method is independent of the horizontal dimension of the device. Therefore, the method does not require an angled implant to adjust VT, although if so desired, one may be performed without altering the effectiveness of p-n junction 111 spanning between the bottoms of the laterally spaced shallow trench isolation regions (oxide regions 40).
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The exemplary embodiments have been discussed in reference to forming n-channel SDOI transistor structures. However, these concepts, taught in the exemplary embodiments, may be utilized by one of ordinary skill in the art to form p-channel SDOI transistor structures as well, by simply replacing the implants with the proper type of doping implant. For example, in exemplary embodiment of
The completed SDOI transistor structure and the fabrication method used therefor may be for various types of devices, such as embedded memory devices, and may be used in numerous semiconductor applications and particularly in, but not limited to, DRAMs. For example, the present invention may be applied to a semiconductor system, such as the one depicted in
It is to be understood that, although the present invention has been described with reference to a preferred embodiment, various modifications, known to those skilled in the art, may be made to the disclosed structure and process herein without departing from the invention as recited in the several claims appended hereto.
Claims
1. A transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.
2. The transistor structure of claim 1, wherein the transistor structure comprises a p-channel transistor with the conductive depletion region having a p-type conductivity.
3. The transistor structure of claim 1, wherein the transistor structure comprises an n-channel transistor with the conductive depletion region having an n-type conductivity.
4. A transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.
5. The transistor structure of claim 4, wherein the transistor structure comprises a p-channel transistor.
6. The transistor structure of claim 4, wherein the transistor structure comprises an n-channel transistor.
7. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-type conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.
8. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising an n-type conductive depletion region laterally spanning completely between the first and second laterally spaced insulative regions.
9. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.
10. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- an electrical isolation region at the base of the first and second laterally spaced insulative regions, the electrical isolation region comprising a p-n junction laterally spanning completely between the first and second laterally spaced insulative regions.
11. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having p-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that an transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- a boron doped conductive depletion region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
12. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having n-type source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- an arsenic or phosphorus doped conductive depletion region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
13. A p-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- a p-n junction comprising boron and arsenic doped region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
14. An n-channel Source-drain On Insulator (SDOI) transistor structure for a semiconductor assembly comprising:
- first and second laterally spaced insulative regions having source and drain regions residing above the first and second laterally spaced insulative regions respectively, such that a transistor channel region extends laterally between the first and second laterally spaced insulative regions; and
- a p-n junction comprising boron and arsenic doped region laying beneath the transistor channel region and laterally spanning completely between the bases of the first and second laterally spaced insulative regions.
Type: Application
Filed: Sep 30, 2004
Publication Date: Feb 24, 2005
Inventor: Zhongze Wang (Boise, ID)
Application Number: 10/956,196