Examination apparatus for biological sample and chemical sample
A wireless sensor chip suitable for the compact, high-sensitive, and low-cost examination apparatus for easily examining a biological material such as gene at low cost is provided. A sensor chip is formed on an SOI substrate, and an n type semiconductor layer on which a pMOS transistor is formed and a p type semiconductor layer on which an nMOS transistor is formed are isolated by a pn junction. Therefore, the p type semiconductor layer at the outermost portion (chip edge portion to be in contact with solution) is set to floating, and the maximum potential and the minimum potential of the chip are supplied to an n type semiconductor layer and a p type semiconductor layer inside the outermost portion, respectively. Also, the chip is covered with an ion impermeable insulating film for reducing the penetration of positive ions through the oxide layer.
The present application claims priority from Japanese Patent Application JP 2004-012596 filed on Jan. 21, 2004, the content of which is hereby incorporated by reference into this application.
TECHNICAL FIELD OF THE INVENTIONThe present invention relates to a sensor and a system, in which the sensor is put into or comes into contact with a sample and results thereof are transmitted wirelessly to an external device. As the examples of the system mentioned above, a system for detecting biological materials such as nucleic acid, protein, antigen, and antibody and a system for measuring physical and chemical quantity such as temperature, pressure, light, and ion concentration can be shown.
BACKGROUND OF THE INVENTIONJapanese Patent Laid-Open Application No. 2002-14072 discloses an integrated circuit device called an integrated sensor device, in which a sensor portion, a control unit for processing the signals representing the detection results of the sensor portion, and an antenna for receiving the energy required for the communication with outside and the circuit operation from outside are integrated on one chip. It also discloses that an ion sensitive field effect transistor (hereinafter, referred to as ISFET) and an organic film whose characteristics are changed when it contacts to gas or liquid containing a substance are used as the sensor portion of this integrated sensor device.
An extended gate structure disclosed in J. van der Spiegel, I. Lauks, P. Chan, D. Babic, “The extended gate chemically-sensitive field effective transistor as multi species microprobe, Sensors and Actuators” 4 (1983) pp. 291-298, and K. Tsukada, Y. Miyahara, Y. Shibata, H. Miyagi, “An integrated micro multi-ion sensor using platinum-gate field effect transistors”, Proc. Int. Conf. Solid-State Sensors and Actuators (Transducers '91), San Francisco, USA, 1991, pp. 218-221 is known as a structure suitable for the monolithic integration of the ISFET with the integrated circuit.
Also, the problem that the device characteristics and the electric insulation between devices are degraded due to the penetration of positive ions into the device forming region in a semiconductor integrated circuit device with the SOI structure is examined in Japanese Patent Laid-Open Application No. 6-177233, Japanese Patent Laid-Open Application No. 6-177242.
SUMMARY OF THE INVENTIONStarting with the gene test and the protein test, the system capable of easily measuring biological and chemical materials has been demanded in various fields. In order to meet such demands, the inventors of the present invention examine the wireless sensor chip (hereinafter, referred to as sensor chip) in which a sensor for measuring a biological material such as DNA, a chemical material, ion, and physical quantity and a mechanism for wirelessly transmitting the sensing data to the outside of a chip are integrated on a semiconductor chip. Japanese Patent Laid-Open Application No. 2002-14072 does not describe what type of device the integrated sensor device can be. Especially, it is desired that the device can be manufactured simply by the current semiconductor manufacturing process so as to realize the measurement system at low cost.
Also, it is also necessary that the device can maintain its reliability even when the sensor chip is used in a solution.
The method for solving the above-described problems is shown below.
A sensor chip is formed on an SOI substrate. However, the n type semiconductor region in which the pMOS transistor is formed and the p type semiconductor region in which the nMOS transistor is formed are isolated from each other by the pn junction. This can be achieved by applying the minimum potential of the sensor chip as the substrate potential of the p type semiconductor region and applying the maximum potential of the sensor chip as the substrate potential of the n type semiconductor region.
Also, the integrated circuit constituting the sensor chip is surrounded by an n type (p type) semiconductor region (guard ring) which reaches the buried insulating layer of the SOI substrate, and its outer periphery is made to be a p type (n type) semiconductor region. In addition, the maximum potential (minimum potential) of the sensor chip is applied to the guard ring, and the semiconductor region of its outer periphery is set to floating.
Furthermore, in order to prevent the penetration of positive ions through the oxide layer, the chip is covered with an ion impermeable insulating film.
It is possible to provide a sensor chip suitable for the detection of a biological material such as gene and a chemical material and the measurement of physical-chemical quantity such as temperature, pressure, and pH.
BRIEF DESCRIPTION OF THE DRAWINGS
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
After the sensing data is converted to the digital signal in the sensor analog block 151, it is converted to the radio frequency signal in the RF interface block 153 and is transmitted to the reader/writer 230 through an RF carrier wave. Also, the power consumed in the circuit blocks 150 to 153 mounted on the sensor chip is supplied by the inductive coupling of the reader/writer 230 and an antenna 221.
A measurement control device 231 controls the reader/writer 230 and collects the sensing data by using the sensor chip 200, and also, it processes the sensing data.
Hereinafter, an example of a sensor chip using an ISFET as a sensor will be described.
The constant current source 175 and the amplifier circuit AMP are provided in order to detect the above-described change. The drain voltage Vds of the ISFET 184 is controlled so as to be constant voltage given by the constant current source 179 and the resistance 181. Also, since a constant current source 175 and the ISFET 184 are connected in series, the drain current Ids of the ISFET 184 is constant current. The difference between the channel resistance depending on the hydrogen ion concentration and Vds/Ids is detected as the change of the potential of a node N1. The hydrogen ion concentration of the sample solution is measured by reading the potential of the node N1 from an output terminal 180 via a voltage follower amplifier 177.
Note that the bias circuit 174 supplies a predetermined bias potential to the potential of the reference electrode 173 in order to enhance the detection sensitivity by the ISFET 184. Also, in order to reduce the power consumption of the sensor chip, the power supply of the constant current source 174 and the bias circuit 174 is stopped by a sensor control circuit (not shown) when the sensor is not operated.
In order to detect the potential of the node N1 by using the circuit shown in
It is desired that the change for the standard CMOS process is reduced to minimum so as to achieve the cost reduction and the structure with high reliability capable of electrically isolating the substrate from the sample solution can be obtained. Therefore, an SOI (Silicon on Insulator) substrate is used as the semiconductor substrate to realize the electric isolation of the chip rear surface. In addition, with respect to the edge of the chip, a guard ring as an impurity diffusion layer which reaches the buried insulating layer (buried oxide layer: hereinafter, referred to as BOX layer) of the SOI substrate is formed on the periphery of the chip, and a p type or n type impurity diffusion layer is formed inside the guard ring. Also, the impurity diffusion layer on the outer periphery of the guard ring is set to floating potential and the potential of the impurity diffusion layer inside the guard ring is set to the reverse bias potential relative to the potential of the impurity diffusion layer of different conductivity type. By doing so, the insulation structure by the pn junction can be obtained.
Also, the reduction of the penetration of positive ions through the exposed portion of the oxide film is also important for the enhancement of the device reliability. When an exposed portion of the oxide film is present on the edge of the chip, positive ions such as sodium penetrate. For example, in the structure shown in
As described above, in order to satisfy the requirement to use the unpackaged chip in a solution, the following two conditions are important for the enhancement of the reliability of a sensor chip. That is, the first is to insulate the rear surface and the edge of the chip from the solution, and the second is to prevent the penetration of positive ions through the edge of the chip.
As shown in
The adjacent nMOS are isolated from each other by a field insulating film 114. In the example shown in
A first wiring layer 121 and a second wiring layer 123 are formed after forming the MOS transistors. Next, an ion impermeable insulating film 125 is deposited on an oxide insulating film 124. At this time, the oxide insulating films 120, 122, and 124 in the chip peripheral portion are removed to expose the silicon layer 109 before depositing the ion impermeable insulating film 125. Then, by depositing the ion impermeable insulating film 125, the ion impermeable insulating film 125 and the silicon layer 109 come into contact with each other at silicon layer exposed portions 127 and 128 in the chip peripheral portion, and the diffusion path of the positive ions of the oxide insulating films 120, 122, and 124 is shut.
Phosphosilicate glass (PSG) or silicon nitride (Si3N4) can be used as the ion impermeable insulating film 125. The PSG has a function to capture the positive ions diffused into the oxide insulating film by using phosphorus. In the example of
After forming the ion impermeable insulating film 125, an insulating film 126 is deposited and a metal layer for forming a connection portion 130 to the ion sensitive films 134 and 135, a coil 132, and a pseudo reference electrode 131 is formed. Copper of 10 μm is used as the metal layer. The pseudo reference electrode is an electrode for applying a reference potential to the gate of the ISFET with reference to the solution potential when sensor chips are put into the solution (reference electrode 173 in
For example, gold with a thickness of 100 nm is formed after forming an adhesive metal layer to copper. Before forming metal layers 130, 131, and 132, the insulating layers 123, 125, and 126 are processed to form through holes, and the necessary connection to the integrated circuit portion is made. After forming the metal layers 130, 131, and 132, an insulating film 133 is deposited and a through hole is formed in a part of the gate connection electrode 130 of the ISFET. Then, the ion sensitive films 134 and 135 connected to the gates of the first ISFET and the second ISFET are formed, respectively.
The electric isolation of the sensor chip will be described based on the sensor chip shown in
Therefore, even when the potential of the p type floating layer 109 is increased by the potential of the sample solution, since the guard ring layer 105R and the floating layer 109 are reversely biased, the insulation between the sensor chip and the solution can be maintained as far as within the power supply voltage. Also, the ground potential of the chip differs by only the bias potential 174 on the basis of the pseudo reference electrode 173. When the bias potential generated in the integrated circuit of the chip is set lower than the power supply potential, the insulation of the integrated circuit is not lost. Note that, for setting the floating layer 109 to n type, the guard ring is set to p type and the ground potential of the chip is set thereto.
Also, the polarity of the impurity diffusion layer is not limited to the description above. For example, even in the case where the sensor chip is formed on the n type SOI substrate, the same effects can be obtained by giving the suitable polarity of a diffusion layer and well potential.
Next, the reduction of diffusion of the positive ions from the chip edge will be described. First, the diffusion path of the positive ions will be described. In the portion above the main surface of the SOI substrate 100, the diffusion path of the positive ions through the oxide insulating film from the chip edge portion is shut by the ion impermeable film 127. In addition, the BOX layer 102 can be cited as a silicon oxide film formed below the main surface of the SOI substrate, and the BOX layer 102 can be the diffusion path of the positive ions. As described in the structure of
As described above, the structure of the MOS transistor and the ISFET shown in
In this modified example, the structure in which the field insulating films 118 and 119 reach the BOX layer is used, and such a structure can be achieved in the following manner. That is, (1) the silicon layer 103 on the BOX layer 102 is made thinner. For example, the thickness of the silicon layer 103 is set to 150 nm and that of the field insulating film is set to 450 nm (the thickness below the main surface of the SOI substrate is set to 200 nm). (2) The thickness of the silicon layer 103 is set to 2 μm and a deep trench is formed in the device isolation region and an insulating film is deposited thereon. (3) The thickness of the silicon layer 103 is set to 500 nm and that of the field insulating film is set to 1.5 μm. For example, when the method of (1) is used, the source and drain regions 111, 112, and 113 of the MOS transistor come into contact with the BOX layer 102, Therefore, it becomes possible to reduce the parasitic capacitance between the source and drain regions and the silicon layer or that between the wiring on the field insulating film and the silicon layer, and thus, the reduction of power consumption and the increase of the operation speed of the integrated circuit can be achieved.
Similar to the device of
The device structures of
Therefore, in order to further reduce the influence of the positive ions, the sensor circuit as shown in
As another circuit configuration, it is possible to use an amplifier with a differential pair as shown in
In the foregoing, the pH sensor is taken as an example in the description of the sensor chip according to the present invention. However, the sensor chip achieved by the present invention is not limited to the pH sensor. For example, the DNA sensor is also achieved in the same manner.
When forming the reference ISFET as shown in
Furthermore, it is also possible to detect an organic material such as protein by using the sensor chip according to the present invention. When protein does not have either of positive and negative charges, the preliminary process in which the protein to be detected is modified by the charge is performed in advance. By doing so, when the protein is specifically bonded to the ISFET due to the antigen-antibody reaction, the gate potential of the ISFET is changed. In this manner, it is possible to detect the organic material in the sample solution.
Further, not only the ISFET but also other sensors such as a temperature sensor, a photodiode, and a strain sensor are also available. The structure of the sensor chip using the photodiode as a sensor is shown in
An example of the light sensor circuit using the photodiode is shown in
The photodiode can be used as the sensor of a measurement using bioluminescence such as the SNPs (single nucleotide polymorphisms analysis) of the DNA based on the BAMPER (Bioluminometry) method. In the BAMPER (Bioluminometric Assay with Modified Primer Extension Reactions) method, it is designed that the 3′ end of the primer DNA is located at the position to detect the displacement and then the complementary strand synthesis is initiated. The complementary stand extension of the primer is significantly influenced by whether or not the 3′ end matches with the target, and when it matches with the target, the complementary strand extension occurs. However, when it does not match with the target, the complementary strand extension scarcely occurs. The discrimination in SNPs is performed by using this. The chemical equation thereof is shown in
More specifically, PPi (inorganic pyrophosphate) is formed as the by-product of the DNA complementary strand synthesis of the reaction substrate dNTP (deoxynucleotide triphosphoate) in the presence of the DNA polymerase. When this is reacted in the presence of APS (adenosine 5 phosphosulfate) and ATP sulfurylase, the ATP is produced. Since the ATP emits a light when it is reacted in the presence of luciferin and luciferase, the complementary strand extension is detected by measuring the light. Since the inorganic pyrophosphate is produced by the light-emitting reaction, the light emission is continued while consuming the APS. The light emission resulting from the complementary strand extension is detected by the photodiode.
An example of the process flow for forming the structure of
In the step of
In the step of
In the step of
In the step of
In the step of
In the step of
In the step of
The present invention can be applied to a sensor chip for easily examining a biological material such as gene and physical-chemical quantity and to a measurement system for performing the examination by using the sensor chip.
Claims
1. A semiconductor integrated circuit device formed on an SOI substrate, comprising:
- a first semiconductor region of second conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of first conductivity type are formed;
- a second semiconductor region of first conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of second conductivity type are formed;
- a plurality of wirings formed on said first and second semiconductor regions; and
- an oxide layer for electrically isolating said wirings or said wirings from said SOI substrate,
- wherein sidewalls of said oxide layer are covered with an ion impermeable insulating film.
2. The semiconductor integrated circuit device according to claim 1,
- wherein a first potential is supplied to said first semiconductor region and a second potential is supplied to said second semiconductor region, thereby applying reverse bias to a pn junction between said first semiconductor region and said second semiconductor region, and
- said first potential is one of maximum potential and minimum potential of said semiconductor integrated circuit device and said second potential is the other of maximum potential and minimum potential of said semiconductor integrated circuit device.
3. The semiconductor integrated circuit device according to claim 2, further comprising:
- a third semiconductor region of second conductivity type which is formed so as to reach a buried insulating layer of said SOI substrate and surround said integrated circuit; and
- a fourth semiconductor region of first conductivity type formed on an outer periphery of said third semiconductor region,
- wherein said second potential is supplied to said third semiconductor region and said fourth semiconductor region is set to floating.
4. The semiconductor integrated circuit device according to claim 1,
- wherein said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,
- said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and
- thickness of said first and second field insulating films is smaller than that from a main surface of said SOI substrate to a buried insulating layer.
5. The semiconductor integrated circuit device according to claim 1,
- wherein said ion impermeable insulating film covers also an outer periphery of a buried insulating layer of said SOI substrate.
6. The semiconductor integrated circuit device according to claim 5,
- wherein said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,
- said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and
- said first field insulating film and said second field insulating film reach the buried insulating layer of said SOI substrate.
7. The semiconductor integrated circuit device according to claim 1,
- wherein metal wirings and through hole patterns for preventing penetration and diffusion of ions from outer periphery of said oxide layer are provided.
8. The semiconductor integrated circuit device according to claim 1,
- wherein an ion sensitive field effect transistor is provided.
9. The semiconductor integrated circuit device according to claim 1,
- wherein a phosphosilicate glass layer or a silicon nitride layer is used as said ion impermeable insulating film.
10. A sensor chip, comprising:
- a sensor portion;
- a signal processing circuit for processing sensing signals from said sensor portion;
- a communication control circuit for controlling a communication with an external device;
- an interface circuit for converting said sensing signals processed in said signal processing circuit into radio frequency signals; and
- a coil and a resonant capacitor for transmitting said radio frequency signals to said external device,
- wherein said sensor portion, said signal processing circuit, said communication control circuit, said interface circuit, and said coil and resonant capacitor are integrated on a chip,
- said sensor chip is formed on an SOI substrate,
- a plurality of wirings formed on said SOI substrate and an oxide layer for electrically isolating said wirings or said wirings from said SOI substrate are formed, and
- sidewalls of said oxide layer are covered with an ion impermeable insulating film.
11. The sensor chip according to claim 10, further comprising:
- a first semiconductor region of second conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of first conductivity type are formed; and
- a second semiconductor region of first conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of second conductivity type are formed,
- wherein a first potential is supplied to said first semiconductor region and a second potential is supplied to said second semiconductor region, thereby applying reverse bias to a pn junction between said first semiconductor region and said second semiconductor region, and
- said first potential is one of maximum potential and minimum potential of said sensor chip and said second potential is the other of maximum potential and minimum potential of said sensor chip.
12. The sensor chip according to claim 11, further comprising:
- a third semiconductor region of second conductivity type which is formed so as to reach a buried insulating layer of said SOI substrate and surround said integrated circuit; and
- a fourth semiconductor region of first conductivity type formed on an outer periphery of said third semiconductor region,
- wherein said second potential is supplied to said third semiconductor region and said fourth semiconductor region is set to floating.
13. The sensor chip according to claim 11,
- wherein said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,
- said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and
- thickness of said first and second field insulating films is smaller than that from a main surface of said SOI substrate to a buried insulating layer.
14. The sensor chip according to claim 11,
- wherein said ion impermeable insulating film covers also an outer periphery of a buried insulating layer of said SOI substrate.
15. The sensor chip according to claim 10,
- wherein said sensor chip is used in contact with a sample solution in an unpackaged state,
16. A measurement system, comprising:
- reaction vessels;
- a reader/writer;
- an antenna connected to said reader/writer; and
- sensor chips put into said reaction vessels,
- wherein said sensor chip can receive signals from said antenna or transmit sensing data to said reader/writer via said antenna,
- said sensor chip is formed on an SOI substrate,
- a plurality of wirings formed on said SOI substrate and an oxide layer for electrically isolating said wirings are formed, and
- sidewalls of said oxide layer are covered with an ion impermeable insulating film.
17. The measurement system according to claim 16,
- wherein said sensor chip is used in contact with a sample solution in an unpackaged state.
18. The measurement system according to claim 16,
- wherein said sensor chip includes:
- a first semiconductor region of second conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of first conductivity type are formed; and
- a second semiconductor region of first conductivity type which is formed on said SOI substrate and in which a plurality of MOS transistors of second conductivity type are formed,
- a first potential is supplied to said first semiconductor region and a second potential is supplied to said second semiconductor region, thereby applying reverse bias to a pn junction between said first semiconductor region and said second semiconductor region, and
- said first potential is one of maximum potential and minimum potential of said sensor chip and said second potential is the other of maximum potential and minimum potential of said sensor chip.
19. The measurement system according to claim 18,
- wherein power of said sensor chip is supplied by inductive coupling of said antenna and a coil of said sensor chip.
20. The measurement system according to claim 18,
- wherein said sensor chip includes:
- a third semiconductor region of second conductivity type which is formed so as to reach a buried insulating layer of said SOI substrate and surround said integrated circuit; and
- a fourth semiconductor region of first conductivity type formed on an outer periphery of said third semiconductor region, and
- said second potential is supplied to said third semiconductor region and said fourth semiconductor region is set to floating.
21. The measurement system according to claim 18,
- wherein said sensor chip is characterized in that said plurality of MOS transistors of first conductivity type formed in said first semiconductor region are isolated by a plurality of first field insulating films,
- said plurality of MOS transistors of second conductivity type formed in said second semiconductor region are isolated by a plurality of second field insulating films, and
- thickness of said first and second field insulating films is smaller than that from a main surface of said SOI substrate to a buried insulating layer.
22. The measurement system according to claim 18,
- wherein said ion impermeable insulating film covers also an outer periphery of a buried insulating layer of said SOI substrate.
Type: Application
Filed: Sep 3, 2004
Publication Date: Jul 21, 2005
Inventors: Yoshiaki Yazawa (Tokyo), Kazuki Watanabe (Kokubunji), Masao Kamahori (Kokubunji), Yukinori Kunimoto (Kodaira)
Application Number: 10/933,339