Integrated circuit routing resource optimization algorithm for random port ordering
A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within the same routing track parallel to the closest portion of a primary bus route. All other blocks, termed secondary blocks, have ports that are positioned so that no two ports of any secondary block reside within the same routing track perpendicular to the closest portion of the primary bus route. A primary connection for each signal of the signal bus is then placed over each port of the primary block substantially along the length of the primary route. Each port of each secondary block then has a secondary track connecting it in a perpendicular fashion to the proper primary track.
As integrated circuit (IC) technology continues to evolve, the use within ICs of wide multi-signal buses, such as data buses, becomes more prevalent. Generally speaking, such buses consume large amounts of limited routing resources, causing routing problems for both the bus and other signal connections within an IC. Also, as the functional capacity of ICs increase, the interconnections required between circuit “blocks” of the IC increase as well, thus exacerbating the routing problem.
To help alleviate such routing congestion, IC designers sometimes force the placement of the ports within each block in an orderly fashion. An example of this port placement is shown in
However, such orderly port placement within each block often creates a burden on the IC designer in terms of time and effort to architect each block to minimize routing resources. Additionally, many block designs simply preclude such orderly port alignment.
From the foregoing, a need exists for the ability to optimize the routing of IC inter-block signals among blocks utilizing somewhat randomly placed ports. Such ability would reduce the substantial amount of routing resources typically required for signal buses while eliminating the burden of orderly port placement on the IC designer.
SUMMARY OF THE INVENTIONEmbodiments of the invention, to be discussed in detail below, provide a method for routing an IC signal bus efficiently while minimizing the routing resources consumed. One of a set of blocks to be connected to the bus is selected as a primary block, the ports of which are to be positioned so that no two ports of the primary block reside within the same routing track running parallel to a primary bus route. All other blocks, known as secondary blocks, have ports positioned so that no two ports of each separate block reside within the same routing track running perpendicular to the primary bus route. A primary connection for each signal of the bus is then aligned over each primary block port, extending essentially along the length of the primary bus route. Each secondary block port then has a secondary connection associated with it that connects that port to the primary connection associated with that port in a perpendicular manner.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
A simplified embodiment of the invention is shown in
The ports of the primary block are then positioned so that no two of those ports reside in the same routing track running parallel to a primary bus route (step 120 of
In alternate embodiments, the ports of the primary block will not strictly form a straight line; each port of the primary block need only reside within a separate routing track parallel to the primary bus route. However, in the case of
Ports for each of the secondary blocks are then positioned so that no two ports within a single secondary block reside in a single routing track perpendicular to the primary bus route (step 130 of
Once the ports are positioned, a primary connection is placed over each port of the primary block substantially along the length of and parallel to the primary bus route (step 140 of
Also, a secondary connection is placed to connect each port of each secondary block with the appropriate primary connection in a perpendicular manner (step 150 of
Generally speaking, horizontal routing tracks reside on a separate IC layer from vertical routing tracks in order to efficiently utilize all IC resources dedicated to is routing of signals. As a result, the connections between horizontal and vertical routing tracks, as well as between routing tracks and the ports of the circuit blocks, are implemented by interlayer connections. A positive consequence of such an arrangement is that horizontal tracks cross over or under vertical tracks without unintended connection between the two. For example, referring to
As a result of embodiments of this invention, the physical ordering of ports P of each primary and secondary block are not required to coincide. This phenomenon can be seen in
Another advantage of embodiments of the invention is that substantially fewer routing resources are consumed when compared to the prior art, such as the signal bus routing shown in
The configuration and orientation of the primary bus route may vary greatly from case to case. As shown in the example of
Additionally, unlike the embodiments of
Embodiments of the invention may also be described in terms of the IC signal bus structure resulting from the implementation of the above-described methods. In general, such signal bus structures include a set of primary connections, with each primary connection being connected to a separate port of a primary circuit block. Each primary connection lies essentially parallel to each other. Although the primary connections may all run in a single direction such as the vertical primary connections of
From the foregoing, the invention provides integrated circuit bus structures, and improved methods for routing such structures, which allow relatively simple bus routing and efficient usage of limited IC routing resources without the need for strictly enforced port placement. Embodiments of the invention other than those shown above are also possible. As a result, the invention is not to be limited to the specific forms so described and illustrated; the invention is limited only by the claims.
Claims
1. A method for routing an integrated circuit signal bus, comprising:
- selecting a primary block from a plurality of blocks, each of the blocks having a plurality of ports to be connected to the signal bus, the remainder of the plurality of blocks being secondary blocks;
- positioning the plurality of ports of the primary block so that no two ports of the primary block reside with a single routing track running parallel to the portion of a primary bus route residing closest to the primary block;
- positioning the plurality of ports of each secondary block so that no two ports within each secondary block reside within a single routing track running perpendicular to the portion of the primary bus route residing closest to that secondary block;
- for each port of the primary block, placing a primary connection over that port parallel to the primary bus route, each primary connection running substantially the length of the primary bus route; and
- for each port of each secondary block, placing a secondary connection extending orthogonally from one of the primary connections to that port.
2. The method of claim 1, wherein the primary bus route essentially describes a straight line.
3. The method of claim 1, wherein the primary bus route contains at least one change of direction.
4. A computer system for routing an integrated circuit signal bus, comprising:
- means for selecting a primary block from a plurality of blocks, each of the blocks having a plurality of ports to be connected to the signal bus, the remainder of the plurality of blocks being secondary blocks;
- means for positioning the plurality of ports of the primary block so that no two ports of the primary block reside with a single routing track running parallel to the portion of a primary bus route residing closest to the primary block;
- means for positioning the plurality of ports of each secondary block so that no two ports within each secondary block reside within a single routing track running perpendicular to the portion of the primary bus route residing closest to that secondary block;
- for each port of the primary block, means for placing a primary connection over that port parallel to the primary bus route, each primary connection running substantially the length of the primary bus route; and
- for each port of each secondary block, means for placing a secondary connection extending orthogonally from one of the primary connections to that port.
5. The computer system of claim 4, wherein the primary bus route essentially describes a straight line.
6. The computer system of claim 4, wherein the primary bus route contains at least one change of direction.
7. A program storage medium readable by a computer system, embodying a program executable by the computer system to perform method steps for routing an integrated circuit signal bus, the method steps comprising:
- selecting a primary block from a plurality of blocks, each of the blocks having a plurality of ports to be connected to the signal bus, the remainder of the plurality of blocks being secondary blocks;
- positioning the plurality of ports of the primary block so that no two ports of the primary block reside with a single routing track running parallel to the portion of a primary bus route residing closest to the primary block;
- positioning the plurality of ports of each secondary block so that no two ports within each secondary block reside within a single routing track running perpendicular to the portion of the primary bus route residing closest to that secondary block;
- for each port of the primary block, placing a primary connection over that port parallel to the primary bus route, each primary connection running substantially the length of the primary bus route; and
- for each port of each secondary block, placing a secondary connection extending orthogonally from one of the primary connections to that port.
8. The program storage medium of claim 7, wherein the primary bus route essentially describes a straight line.
9. The program storage medium of claim 7, wherein the primary bus route contains at least one change of direction.
10. An integrated circuit signal bus structure, comprising:
- a plurality of primary connections, each primary connection being connected to a separate port of a primary block, the plurality of primary connections lying essentially parallel to each other; and
- a plurality of secondary connections, each secondary connection coupling a port of a secondary block with one of the plurality of primary connections, the connection between each secondary connection and its associated primary connection being perpendicular, the secondary connections of any single secondary block being parallel to each other.
11. The integrated circuit signal bus structure of claim 10, wherein the plurality of primary connections essentially describes a straight line.
12. The integrated circuit signal bus structure of claim 10, wherein the plurality of primary connections contains at least one change of direction.
13. An integrated circuit containing the integrated circuit bus structure of claim 10.
Type: Application
Filed: Jul 25, 2005
Publication Date: Nov 24, 2005
Inventors: Gerald Esch (Ft. Collins, CO), Richard Rodgers (Fort Collins, CO)
Application Number: 11/188,925