METHOD AND APPARATUS FOR STACKING ELECTRICAL COMPONENTS USING OUTER LEAD PORTIONS AND EXPOSED INNER LEAD PORTIONS TO PROVIDE INTERCONNECTION
A stacking structure is described that permits stacking of electrical components with no requirement for an ancillary stacking framework. Electrical components are fabricated with inner and outer lead portions that provide connection to a substrate and to other electrical components in a stack.
1. Field of the Invention
The present invention relates generally to electrical component fabrication methods and, more particularly, to fabrication of thin packages containing a multiplicity of electrical components.
2. Description of Related Art
Personal devices that require a large number of electronic components to be provided in a small volume are rapidly proliferating. A pocket-sized personal music player that includes a hard disk is only one example of such a device. Today's personal electronic devices require that more and more functionality must be provided in a relatively small space. Traditionally, multi-chip electronic devices were fabricated by placing chips on a two-dimensional substrate such as a printed circuit board (PCB). As circuit density increased, methods were devised for stacking multiple chips, thereby trading a scarce resource of substrate area for space in a third dimension. Several prior-art structures for stacking multiple chips have been devised, but none has proven to be wholly satisfactory. The need to stack components typically requires fabricating a superstructure that supports the stacked components. This superstructure adds to the volume and weight, and therefore to the cost, of the component stack, thereby offsetting an advantage that may be gained by stacking. Some stacking structures make efficient use of space, but tend to be complicated and expensive to fabricate. Less complicated and expensive stacking structures may either fail to make efficient use of space and/or present problems in disposing of the heat generated by chips in a stack
A need thus exists in the prior art for a stacking structure that is efficient in its use of space while being easy to fabricate. A further need exists for a structure that is capable of efficiently dissipating heat generated by stacked electronic components.
SUMMARY OF THE INVENTIONThe present invention addresses these needs by providing a scalable structure for stacking electrical components using substantially identical parts. The stacking structure is fabricated into the parts, themselves, and no special stacking superstructure is needed. The invention described herein discloses a stacking structure for at least a first and a second electrical component wherein the first and second electrical components each include inner and outer leads. The second electrical component is capable of being stacked on the first electrical component. According to a representative embodiment, a connection between the first electrical component and the second electrical component is provided by contact between the inner leads of the first electrical component and the inner leads of the second electrical component. Moreover, the connection between the first electrical component and the second electrical component can be provided by contact between the outer leads of the first electrical component and the outer leads of the second electrical component.
A method of stacking at least a first electrical component and a second electrical component also is disclosed. According to one implementation of the method, first and second electrical components are fabricated, each electrical component having inner and outer leads. The second electrical component is stacked on the first electrical component by placing the inner leads of the first electrical component in contact with the inner leads of the second electrical component. According to another implementation of the method, the second electrical component is stacked on the first electrical component by placing the outer leads of the first electrical component in contact with the outer leads of the second electrical component.
While the apparatus and method has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless expressly formulated under 35 U.S.C. 112, are not to be construed as necessarily limited in any way by the construction of “means” or “steps” limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents, and in the case where the claims are expressly formulated under 35 U.S.C. 112 are to be accorded full statutory equivalents under 35 U.S.C. 112.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one skilled in the art. For purposes of summarizing the present invention, certain aspects, advantages and novel features of the present invention are described herein. Of course, it is to be understood that not necessarily all such aspects, advantages or features will be embodied in any particular embodiment of the present invention. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims that follow.
BRIEF DESCRIPTION OF THE FIGURES
Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the drawings are in simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as, top, bottom, left, right, up, down, over, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms should not be construed to limit the scope of the invention in any manner.
Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. The intent of the following detailed description, although discussing exemplary embodiments, is to be construed to cover all modifications, alternatives, and equivalents of the embodiments as may fall within the spirit and scope of the invention as defined by the appended claims. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of stacking structures. The present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are conventionally used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention.
Referring more particularly to the drawings,
The active surface 116a comprises a central area and a peripheral area having a plurality of bonding pads 120a (
Molding resin 160a encapsulates the active surface 116a of the chip 115a, the bonding pads, the adhering surface 111a of the chip paddle 110a, the wire-connecting surfaces 145a of the inner portions 130a of leads 125a, and the wires 150a in the illustrated embodiment. The encapsulation leaves the non-active surface 117a of the chip 115a, the non-adhering surface 112a of the chip paddle 110a, and the mounting surfaces 140a of the inner lead portions 130a exposed. Exposing these elements of first electrical component 100a may enhance the dispersion of thermal energy produced in chip 115a. The outer lead portions 135a provide mechanical and electrical contact between first electrical component 100a and the substrate 105a in a typical embodiment.
A plan view from below an embodiment of a stacking structure of the type illustrated in
Parts of the leadframe, including the adhering surface 211a of the chip paddle 210a, the bonding pads, the wire-connecting surfaces 245a of leads 225a, and the active surface 216a of the chip 215a are encapsulated in molding resin 260a. The encapsulation leaves the non-active surface 217a of the chip 215a, the outer lead portions 235a, and the mounting surfaces 240a of the inner lead portions 230a exposed. Again, the illustrated embodiment differs from the embodiment illustrated in
Second chip 320a has a second active surface 321a that may comprise a second plurality of bonding pads (not shown) and an opposing second non-active surface 322a. The second non-active surface 322a is secured to the second adhering surface of the chip paddle 310a. The electrical component 300a further comprises leads 325a that may be formed as part of a leadframe that also comprises the chip paddle 310a. The leads 325a in the illustrated embodiment comprise inner lead portions 330a and outer lead portions 335a. The inner lead portions 330a have wire-connecting surfaces 345a and mounting surfaces 340a. The electrical component 300a also comprises first and second pluralities of wires 350a and 355a. The first plurality of wires 350a connects the first plurality of bonding pads to certain ones of wire-connecting surfaces 345a. Likewise, the second plurality of wires 355a connects the second plurality of bonding pads to other ones of wire-connecting surfaces 345a.
The active surface 316a of first chip 315a, the second chip 320a, the chip paddle 310a, and first and second pluralities of wires 350a and 355a may be encapsulated in molding resin 360a, with the non-active surface 317a of the first chip 315a exposed. The outer lead portions 335a and the mounting surfaces 340a of the inner lead portions 330a also may be exposed, not being encapsulated in molding resin 360a. Exposing these elements of electrical component 300a may provide additional thermal dispersion when compared to the prior art. The electrical component 300a is mounted on a substrate 305a with electrical contact provided between the substrate 305a and the electrical component 300a by the outer lead portions 335a.
The flow diagram of
The stacking structures described in the foregoing can reduce stacking thickness thereby permitting a relatively larger number of electrical components to be stacked in a limited space. Stacking more electrical components can provide more electronic functionality in a given volume than previously was possible. For example, memory density can be significantly improved by employing the present invention in memory designs. The stacking methods disclosed herein are compatible with commonly-used industry assembly processes and with surface mount technology (SMT) processes. These methods further enhance the efficiency of thermal dispersion in integrated circuit packages as described herein.
According to prior art methods, chips intended for use in a multi-chip stack would typically undergo full functional testing at the wafer level before assembly, in order to prevent a single failing chip from causing failure of the whole assembly. In contrast, components assembled according to the present invention may be tested after each subassembly (see for example
In view of the foregoing, it will be understood by those skilled in the art that the methods of the present invention can facilitate formation of stacked electrical components. The above-described embodiments have been provided by way of example, and the present invention is not limited to these examples. Multiple variations and modification to the disclosed embodiments will occur, to the extent not mutually exclusive, to those skilled in the art upon consideration of the foregoing description. Additionally, other combinations, omissions, substitutions and modifications will be apparent to the skilled artisan in view of the disclosure herein. Accordingly, the present invention is not intended to be limited by the disclosed embodiments, but is to be defined by reference to the appended claims.
Claims
1. (canceled)
2. A stacking structure for electrical components, comprising:
- a first electrical component that includes first leads having first inner lead portions and first outer lead portions; and
- a second electrical component that includes second leads having second inner lead portions and second outer lead portions, the second electrical component being capable of being stacked on the first electrical component by placing the second inner lead portions in contact with the first inner lead portions, and also being capable of being stacked on the first electrical component by solacing the second outer lead portions in contact with the first outer lead portions;
- wherein the first electrical component further comprises: a chip having an active surface and an opposing non-active surface, wherein the active surface comprises a central area and a peripheral area having a plurality of bonding pads; a lead frame comprising the first leads, a plurality of tie bars, and a chip paddle having an adhering surface and a opposing non-adhering surface, the adhering surface being connected with the central area, the tie bars being connected to the chip paddle and attached to the active surface of the chip in such a way as to avoid contact with the bonding pads, each of the first leads comprising a wire-connecting surface and a wire non-connecting surface; a plurality of wires electrically connecting bonding pads and wire-connecting surfaces of the first leads; and an encapsulation covering the active surface of the chip, the bonding pads, the adhering surface of the chip paddle, and the wire-connecting surfaces of the first leads and the wires, such that the opposing non-active surface of the chip, the opposing non-adhering surface of the chip paddle and the wire non-connecting surfaces of the first leads are exposed.
3. The stacking structure as set forth in claim 2, wherein the chip paddle is attached to the active surface by one of a solid and a liquid non-conductive adhesive.
4. A stacking structure for electrical components, comprising:
- a first electrical component that includes first leads having first inner lead portions and first outer lead portions; and
- a second electrical component that includes second leads having second inner lead portions and second outer lead portions, the second electrical component being capable of being stacked on the first electrical component by placing the second inner lead portions in contact with the first inner lead portions, and also being capable of being stacked on the first electrical component by placing the second outer lead portions in contact with the first outer lead portions;
- wherein the first electrical component comprises (i) a first chip having an active surface and an opposing non-active surface, wherein the active surface comprises a central area and a peripheral area having a plurality of first bonding pads, and (ii) a lead frame comprising the first leads and a chip paddle having a first adhering surface and a second adhering surface, the first adhering surface being adhered to the active surface of the first chip in such a way as to avoid contact with the first bonding pads, and each of the first leads comprising a wire connecting surface and a wire non-connecting surface;
- wherein the second electrical component comprises a second chip having an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, wherein the active surface of the second chip comprises a central area and a peripheral area having a plurality of second bonding pads;
- wherein the stacking structure further comprises a plurality of wires, parts of which electrically connect first bonding pads with first leads, and parts of which electrically connect second bonding pad with first leads; and
- wherein an encapsulation covers the chip paddle, the second chip, the wire connecting surfaces of the first leads, the active surface of the first chip and the wires, with the non-active surface of the first chip and the wire non-connecting surfaces of the fist leads exposed beyond the encapsulation.
5. The stacking structure as set forth in claim 4, wherein the first adhering surface of chip paddle is attached to the first active surface by one of a solid and a liquid non-conductive adhesive.
6. The stacking structure as set forth in claim 4, wherein the second adhering surface of the chip paddle is attached to the second non-active surface by one of a solid and a liquid adhesive.
7. The stacking structure as set forth in claim 2, wherein the second inner lead portions contact the first inner lead portions and the stacking structure further comprises a third electrical component including third leads laving third inner lead portions and third outer lead portions, the third outer lead portions contacting the second outer lead portions.
8. The stacking structure as set forth in claim 7, further comprising a fourth electrical component including fourth leads having fourth inner lead portions and fourth outer lead portions, the fourth inner lead portions contacting the third inner lead portions.
9. The stacking structure as set forth in claim 2, wherein the second outer lead portions contact the first outer lead portions and the stacking structure further comprises a third electrical component including third leads having third inner lead portions and third outer lead portions, the third inner lead portions contacting the second inner lead portions.
10. The stacking structure as set forth in claim 9, further comprising a fourth electrical component including fourth leads having fourth inner lead portions and fourth outer lead portions, the fourth outer lead portions contacting the third outer lead portions.
11. (canceled)
12. The method as set forth in claim 16, wherein the stacking comprises placing the second inner lead portions in contact with the first inner lead portions and the method further comprises:
- providing a third electrical component including third leads having third inner lead portions and third outer lead portions; and
- stacking the third electrical component on the second electrical component by placing the third outer lead portions in contact with the second outer lead portions.
13. The method as set forth in claim 12, the method further comprising: p1 providing a fourth electrical component including fourth leads having fourth inner lead portions and fourth outer lead portions; and
- stacking the fourth electrical component on the third electrical component by placing the fourth inner lead portions in contact with the third inner lead portions.
14. The method as set forth in claim 16, wherein the stacking comprises placing the second outer lead portions in contact with the first outer lead portions and the method further comprises:
- providing a third electrical component including third leads having third inner lead portions and third outer lead portions; and
- stacking the third electrical component on the second electrical component by placing the third inner lead portions in contact with the second inner lead portions.
15. The method as set forth in claim 14, the method further comprising:
- providing a fourth electrical component including fourth leads having fourth inner lead portions and fourth outer lead portions; and
- stacking the fourth electrical component on the third electrical component by placing the fourth outer lead portions in contact with the third outer lead portions.
16. A method of stacking at least a first electrical component and a second electrical component, comprising:
- providing a first electrical component including first leads having first inner lead portions and first outer lead portions;
- providing second electrical component including second leads having second inner lead portions and second outer lead portions;
- stacking the second electrical component on the first electrical component by one of placing the second inner lead portions in contact with the first inner lead portions and placing the second outer lead portions in contact with the first outer lead portions;
- wherein the providing of the first electrical component comprises: providing a chip having an active surface and an opposing non-active surface, the active surface having a central area and a peripheral area, the peripheral area having a plurality of bonding pads; fabricating a leadframe comprising a chip paddle having an adhering surface, a non-adhering surface, and at least one tie bar, the leadframe having the first leads disposed at a periphery thereof; securing the adhering surface of the chip paddle to the active surface such that the chip paddle does not interfere with the plurality of bonding pads.
17. The method as set forth in claim 16, wherein the securing of the adhering surface of the chip paddle comprises securing the chip paddle with a nonconducting adhesive.
18. The method as set forth in claim 16, wherein:
- the providing of a first electrical component comprises forming wire-connecting surfaces and mounting surfaces on the first inner lead portions; and
- the method further comprises providing a plurality of wires, and disposing the plurality of wires to connect pads of the plurality of bonding pads to wire-connecting surfaces of the first inner lead portions.
19. The method as set forth in claim 18, further comprising encapsulating the active surface of the chip, the plurality of wires, the bonding pads, the adhering surface of the chip paddle, and the wire-connecting surfaces of the first inner lead portions in molding resin such that the non-active surface of the chip, the non-adhering surface of the chip paddle, and the mounting surfaces of the first leads are exposed.
20. A method of stacking at least a first electrical component and a second electrical component, comprising:
- providing a first electrical component including first leads having first inner lead portions and first outer lead portions;
- providing a second electrical component including second leads having second inner lead portions and second outer lead portions;
- stacking the second electrical component on the first electrical component by one of placing the second inner lead portions in contact with the first inner lead portions and placing the second outer lead portions in contact with the first outer lead portions
- wherein the providing of a first electrical component comprises: providing a first chip having a first active surface and an opposing first non-active surface, the first active surface comprising a central area and a peripheral area having a first plurality of bonding pads; forming a leadframe having the first leads disposed at a periphery thereof, the leadframe including a chip paddle having a first adhering surface and a second adhering surface; providing a second chip having a second active surface and an opposing second non-active surface, the second active surface having a second plurality of bonding pads; attaching the first adhering surface of the chip paddle to the first active surface such that the chip paddle does not interfere with the first plurality of bonding pads; and attaching the second adhering surface of the chip paddle to the second non-active surface.
21. The method as set forth in claim 20, wherein:
- the attaching of the first adhering surface of the chip paddle to the first active surface comprises attaching the first adhering surface of the chip paddle using a nonconductive adhesive; and
- the attaching of the second adhering surface of the chip paddle to the second non-active surface comprises attaching the second adhering surface of the chip paddle using a non-conductive adhesive.
22. The method as set forth in claim 21, wherein:
- the providing of a first electrical component comprises forming wire-connecting surfaces and mounting surfaces on the first inner lead portions; and the attaching of the first adhering surface is followed by electrically connecting a first plurality of wires to the first plurality of bonding pads and the wire-connecting surfaces of certain ones of the first inner lead portions; and the attaching of the second adhering surface is followed by electrically connecting a second plurality of wires to the second plurality of bonding pads and the wire-connecting surfaces of other ones of the first inner lead portions.
23. The method as set forth in claim 22, further comprising encapsulating the chip paddle, the second chip, the first active surface of the first chip, the first and second pluralities of wires, and the wire-connecting surfaces of the first inner lead portions such that the non wire connecting surfaces of the first inner lead portions and the first non-active surface of the first chip are exposed.
Type: Application
Filed: May 28, 2004
Publication Date: Dec 1, 2005
Inventors: Chen-Jung Tsai (Hsinchu), Chih-Wen Lin (Hsinchu)
Application Number: 10/856,452