Raised-lines overlay semiconductor targets and method of making the same
The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.
This application is a divisional of application Ser. No. 10/992,549, filed Nov. 18, 2004, pending, which is a continuation of application Ser. No. 09/651,790, filed Aug. 30, 2000, now U.S. Pat. No. 6,914,017, issued Jul. 5, 2005.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to the field of semiconductor device fabrication. Specifically, the present invention provides a residue-free overlay target which enables precise alignment of lithographic masks or reticles while substantially preventing residue build-up at the surface of the semiconductor substrate and eliminating process steps associated with known overlay targets.
2. State of the Art
As is well known, state of the art semiconductor memory and processing devices include multiple layers of electronic features which must be fabricated using multiple process steps. Individual features of state of the art semiconductor devices are generally defined by photolithographic processes wherein a resist is applied over the surface of a semiconductor substrate, or a material layer overlying a semiconductor substrate, and individual device features are patterned into the resist using a mask or reticle. After patterning the resist, the device features are permanently defined in the material layer being processed or the underlying semiconductor substrate by wet or dry etch steps. Advanced processes used to fabricate state of the art semiconductor devices may require as many as fifteen or more separate patterning and etching steps at varying layers during the fabrication process. However, in order to consistently fabricate functional and reliable semiconductor devices, it is necessary that each pattern be accurately aligned over the semiconductor substrate or material layer being processed and the feature dimensions must be precisely defined at each patterning and etch step. This is particularly true for state of the art semiconductor devices which require tolerances in the tens of nanometers range.
To help ensure that the device patterns are accurately positioned, a mask or reticle may be aligned using overlay targets located outside the chip pattern defined on the wafer being processed. Overlay targets are generally etched into the semiconductor substrate or into an overlying material layer and, therefore, become a permanent part of the wafer being processed. As new layers are deposited, patterned, and etched, the new masks or reticles used to process the new layers are often aligned by referencing back to the permanent overlay targets previously defined in an underlying material layer.
Manual or automated registration tools may be used for pattern alignment which is generally accomplished by aligning overlay targets with marks included on the mask or reticle used. In state of the art fabrication facilities, however, automated registration tools are preferred because of their accuracy and high throughput capabilities. To accomplish their task, such automated registration tools must be able to readily detect the edges of the pattern formed by the overlay targets. Yet, as will be described hereinafter, known overlay targets enable intermittent accumulation of process residue which obscures the edges of the overlay target patterns, thereby substantially interfering with the proper function of registration tools.
Known overlay targets generally include a pattern formed by one or more etched trenches or pad areas. Illustrated in drawing
Depicted in drawing
Though the build-up of process residue over an overlay target may occur only intermittently across the surface of a wafer, even one obscured overlay target may render mask or reticle alignment impossible or, at best, imprecise. For this reason, the surface of an incomplete wafer must be periodically cleaned, such as by patterning and etching steps, in order to ensure each of the overlay targets formed in the wafer are clean and easily registered by a registration tool. As is easily appreciated, such cleaning steps add time and cost to the fabrication process. Therefore, an overlay target which does not lead to the collection of obscuring process residue would be an improvement in the art, obviating the cost and delay associated with the cleaning steps currently undertaken to ensure the proper registration of overlay targets.
BRIEF SUMMARY OF THE INVENTIONThe present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target, which answer the foregoing needs. The trenches or pads forming the residue-free overlay target of the present invention are broken down into a series of smaller raised lines which substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers. The residue-free overlay target of the present invention, therefore, prevents the formation of surface features which could serve as collection points for obscuring process residue, thereby eliminating the need to perform the intermediate cleaning steps otherwise necessary to ensure registration of overlay targets.
The method of forming a residue-free overlay target of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art. The method of the present invention includes providing a semiconductor substrate having top and bottom surfaces, depositing a resist layer, exposing the resist layer using a mask or reticle creating a resist pattern corresponding to at least one overlay target according to the present invention developing the resist pattern, and executing a wet or dry etch to create at least one overlay target including a trench or pad area including a series of raised lines. As will be understood by those of skill in the art, the method of the present invention may be used to create overlay targets having a variety of patterns suitable for different semiconductor device fabrication processes, as well as different manual or automated registration tools. Moreover, the method of the present invention is easily modified for the fabrication of overlay targets in a variety of substrates.
Other features and advantages of the present invention will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGSThe figures presented in conjunction with this description are not actual views of any particular portion of an actual semiconductor device or component, but are merely representations employed to more clearly and fully depict the present invention.
The present invention includes a residue-free overlay target useful in the fabrication of state of the art semiconductor devices. The overlay target of the present invention includes one or more trenches or pad areas including a series of raised lines which substantially prevent subsequently deposited material layers from conforming to the topography of the overlay target. Because the subsequently deposited material layers do not conform to the overlay target topography, the overlay target of the present invention prevents formation of surface topography which could serve to collect obscuring process residue. Thus, the overlay target of the present invention simplifies current fabrication methods by eliminating the cleaning steps otherwise necessary to remove accumulated process residue and ensure registration of overlay targets after deposition and processing of subsequently applied material layers.
In a first embodiment, illustrated in drawing
In another embodiment illustrated in drawing
A third embodiment of the overlay target 30 of the present invention is illustrated in drawing
It is significant to note that even though the three preceding embodiments of the overlay target of the present invention include either one or more continuous trenches, a plurality of discontinuous trenches, or a pad area, the overlay target of the present invention is not so limited. The overlay target of the present invention may include more than one pad area, one or more continuous trenches in combination with one or more discontinuous trenches, one or more pad areas in combination with one or more continuous trenches and one or more discontinuous trenches, or one or more pad areas in combination with one or more continuous trenches or one or more discontinuous trenches. As will be understood by one of skill in the art, any combination of continuous trenches, discontinuous trenches, or pad areas may be used, provided that each trench or pad area includes a series of spaced, raised lines and each overlay target forms a pattern that can be evaluated by a registration tool.
The spaced raised lines included in each of the trenches or pad areas of an overlay target of the present invention substantially prevent overlying material layers from conforming to the topography of the overlay target. Illustrated in drawing
Additionally, the spaces defining the raised lines included in each of the trenches or pad areas of an overlay target of the present invention may be of various widths. For example, the widths of the spaces defining the raised lines may be increased where a less conforming material is deposited over the overlay target, or the widths of the spaces defining the raised lines may be decreased where a highly conforming material is deposited over the overlay target. Moreover, the widths of the spaces defining the raised lines included in the overlay target of the present invention may be varied depending on the capabilities of the registration tool used.
Although drawings
A useful comparison is illustrated in drawings
To ensure that the overlay target shown in drawing
Provided in drawing
The present invention also includes a method for forming an overlay target, which will be described in relation to drawings
Though this first embodiment of the method of the present invention has been illustrated using a first material layer as the layer in which the overlay target is fabricated, the first embodiment of the method of the present invention is not so limited. The material layer used for creation of the overlay target need not be the first material layer deposited over the semiconductor substrate. The method according to the first embodiment may also be used to produce overlay targets in any material layer overlying the semiconductor substrate.
In a second embodiment of the method of the present invention the overlay target is etched directly into the semiconductor substrate 60. Thus, as is shown in drawing
It will be easily understood by one of ordinary skill in the art that the method of the present invention is extremely flexible. The method of the present invention is easily adapted to create overlay targets in a variety of substrates using known patterning and etching processes. Moreover, the method of fabricating an overlay target of the present invention may be used to fabricate overlay targets comprising virtually any suitable target pattern.
Though the overlay targets and method of the present invention have been described herein with reference to specific examples, such examples are for illustrative purposes only. The scope of the present invention is defined by the appended claims and is, therefore, not limited by the preceding description and drawings.
Claims
1. An overlay target on a wafer comprising:
- a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the plurality of raised lines of the overlay target.
2. The overlay target of claim 1, further comprising:
- at least one trench comprising a continuous trench defining a geometric shape.
3. The overlay target of claim 1, further comprising:
- at least one trench comprising a plurality of trenches defining said overlay target, each of said plurality of trenches includes a series of raised lines.
4. The overlay target of claim 3, wherein said plurality of trenches includes at least one continuous trench defining a geometric shape.
5. The overlay target of claim 1, wherein said plurality of raised lines comprises raised lines etched into said wafer.
6. The overlay target of claim 5, wherein said plurality of raised lines comprise raised lines etched into a material layer overlying said wafer.
7. The overlay target of claim 5, wherein said plurality of raised lines comprise raised lines disposed in at least one trench.
8. The overlay target claim 5, wherein a plurality of trenches and a corresponding plurality of series of raised lines define said overlay target, each of said plurality of trenches including at lest one of said plurality of series of raised lines.
9. The overlay target of claim 5, wherein said plurality of raised lines comprises raised lines disposed in at least one pad area.
10. The overlay target of claim 9, wherein a plurality of pad areas and a corresponding plurality of series of raised lines define said overlay target, each of said plurality of pad areas including at least one of said plurality of series of raised lines.
11. The overlay target of claim 5, wherein said plurality of raised lines comprises a first series of raised lines disposed in a pad area and a second series of raised lines disposed in a trench.
12. An overlay target on a wafer for use in a semiconductor manufacturing process comprising:
- a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the plurality of raised lines of the overlay target.
13. The overlay target of claim 12, further comprising:
- at least one trench comprising a continuous trench defining a geometric shape.
14. The overlay target of claim 12, further comprising:
- at least one trench comprising a plurality of trenches defining said overlay target, each of said plurality of trenches includes a series of raised lines.
15. The overlay target of claim 14, wherein said plurality of trenches includes at least one continuous trench defining a geometric shape.
16. An overlay target formed on a wafer in a manufacturing process comprising:
- a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the plurality of raised lines of the overlay target.
17. The overlay target of claim 16, further comprising:
- at least one trench comprising a continuous trench defining a geometric shape.
18. The overlay target of claim 16, further comprising:
- at least one trench comprising a plurality of trenches defining said overlay target, each of said plurality of trenches includes a series of raised lines.
19. The overlay target of claim 18, wherein said plurality of trenches includes at least one continuous trench defining a geometric shape.
Type: Application
Filed: Sep 1, 2005
Publication Date: Jan 26, 2006
Inventors: Pary Baluswamy (Boise, ID), Scott DeBoer (Boise, ID), Ceredig Roberts (Boise, ID), Tim Bossart (Boise, ID)
Application Number: 11/217,998
International Classification: H01L 27/148 (20060101);