METHOD AND APPARATUS FOR IMPLEMENTING A CO-AXIAL WIRE IN A SEMICONDUCTOR CHIP
A coaxial shield for a semiconductor chip includes: a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield; a first side shield wire formed in an intermediate metal layer of the semiconductor chip; a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length; a second side shield wire formed in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.
1. Field of the Invention
The present invention is directed to the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to shielding conductors in semiconductor chips.
2. Description of Related Art
Crosstalk noise is generally capacitively and inductively coupled between traces in an integrated circuit and is most significant when the sources of the crosstalk, commonly referred to as aggressor nets or aggressors, have a fast switching waveform. The switching waveforms of one or more aggressor nets are coupled by parasitic capacitance and inductance to a “victim” net. The crosstalk noise may cause false switching in the victim net (noise violation) or alter the net delay, resulting in failure of the integrated circuit design to meet timing specifications.
SUMMARY OF THE INVENTIONIn one aspect of the present invention, a coaxial shield for a semiconductor chip includes:
a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield;
a first side shield wire formed in an intermediate metal layer of the semiconductor chip;
a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to connect the first side shield wire to the top shield wire along the selected length;
a second side shield wire formed opposite the first side shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and
a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top shield wire along the length corresponding to the selected length.
In another aspect of the present invention, A method of shielding a volume in a semiconductor chip includes steps of:
forming a top shield wire in a top metal layer of a semiconductor chip wherein the top shield wire has a selected length for providing a coaxial shield;
forming a first side shield wire in an intermediate metal layer of the semiconductor chip;
forming a first upper via in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top shield wire along the selected length;
forming a second side shield wire opposite the first side shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and
forming a second upper via in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top shield wire along the length corresponding to the selected length.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements throughout the several views of the drawings, and in which:
Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to point out distinctive features in the illustrated embodiments of the present invention.
DESCRIPTION OF THE ILLUSTRATED EMBODIMENTSOne of the most significant factors that may affect propagation delay in a net of an integrated circuit design is the crosstalk noise generated from signals carried in wires adjacent to the net. The crosstalk noise may inject an incremental crosstalk delay (positive or negative) in a net. Crosstalk noise is generally coupled by parasitic capacitance and inductance between traces or wires in an integrated circuit die and is most significant when the sources of the crosstalk, commonly referred to as aggressor nets, or “aggressors”, have a fast switching waveform. The switching waveforms of one or more aggressor nets are coupled by parasitic coupling capacitance and inductance to a net commonly referred to as a victim net or “victim”. Crosstalk noise may cause false switching in the victim net or alter the value of net delay, resulting in consequent failure of the integrated circuit design to meet setup time, hold time, or other timing specifications.
Examples of previous methods for avoiding crosstalk in integrated circuit designs are described, for example, on U.S. Pat. No. 5,109,168 issued on Apr. 28, 1992 to Rusu (Rusu), U.S. Pat. No. 4,514,749 issued on Apr. 30, 1985 to Shoji (Shoji), and U.S. Pat. No. 6,456,117 issued on Sep. 24, 2002 to Tanaka (Tanaka), all of which are incorporated herein by reference. Rusu, Shoji, and Tanaka disclose increasing the wire spacing around critical nets and routing shield wires adjacent to wires in the same metal layer of a critical net, also referred to as coplanar routing. Disadvantageously, neither of these methods provide full protection from crosstalk noise. Increasing the spacing around critical nets may result in a larger die area, which increases manufacturing costs and may also impact other design criteria.
An integrated circuit design is typically implemented by a semiconductor die, or chip, that includes a number of parallel, electrically conductive metal layers in which the wires that connect the nets are formed. The metal layers are generally electrically insulated from one another by insulating layers of dielectric material. Electrical connections from one metal layer to another are made by electrically conductive vias formed in the insulating layers of dielectric material.
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In circuits made from separate components, that is, not sharing the same substrate and package, critical signal wires are typically protected by a coaxial cable as shown in
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In one aspect of the present invention, a coaxial shield for a semiconductor chip includes:
a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield;
a first side shield wire formed in an intermediate metal layer of the semiconductor chip;
a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length;
a second side shield wire formed opposite the first shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and
a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.
The vertical shield wires 1118 and 1120 are formed as wide traces according to well known techniques. The vertical shield wires 1118 and 1120 have a selected length for providing a coaxial shield, in this example, to the signal wire 1112.
The side shield wires 1114 and 1116 may be formed, for example, on opposite sides of the signal wire 1112 in the same manner as in
The vias 1122, 1124, 1126 and 1128 may be formed in the dielectric layers 1108 and 1110, for example, in the same manner used for making vias in a typical semiconductor die. Vias are usually formed as small rectangular holes in a dielectric layer that are filled with an electrically conductive metal, for example, the same material used in the metal layers. The vias electrically connect the two metal layers that are adjacent to the dielectric layer. In various embodiments of the present invention, the small rectangular via shape of the prior art is extended in length and width to form a continuous electrical connection between the metal layers adjacent to the dielectric layer in which the via is formed. The vias 1122 and 1124 formed in the dielectric layer 1108 connect opposite sides of the vertical shield wire 1118 formed in the metal layer 1102 of the semiconductor die to the side shield wires 1114 and 1116 respectively. The vias 1126 and 1128 formed in the dielectric layer 1110 connect opposite sides of the vertical shield wire 1120 formed in the metal layer 1106 of the semiconductor die to the side shield wires 1114 and 1116 respectively.
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In another embodiment of the present invention, the coaxial crosstalk protection scheme of
In another embodiment of the present invention, the coaxial crosstalk protection scheme of
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In another embodiment of the present invention, combined coplanar and vertical shielding may be used to encapsulate a module, for example, a hardmacro or a core, from the rest of the semiconductor chip.
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The side shield rings 2616 and 2618 are formed as closed rings around the module in the intermediate metal layers, in this example, the two metal layers 2604 and 2606. Other numbers of metal layers and dielectric layers may also be used to practice various embodiments of the present invention within the scope of the appended claims.
The via rings 2624, 2626 and 2628 are formed in the dielectric layers 2610, 2612 and 2614 respectively to electrically connect the side shield rings 2616 and 2618 to the vertical shield plates 2620 and 2622.
In another embodiment of the present invention, the coaxial shield of
The side shield rings 2616 and 2618 are formed in the same manner as the side shield wires described above, the vertical shield plates 2620 and 2622 may be formed in the same manner as the vertical shield wires described above, and the via rings 2624, 2626 and 2628 may be formed in the same manner as the vias described above with reference to the coaxial shield of
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In another aspect of the present invention, A method of shielding a volume in a semiconductor chip includes steps of:
forming a top vertical shield wire in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield;
forming a first side shield wire in an intermediate metal layer of the semiconductor chip;
forming a first upper via in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to connect the first side shield wire to the top vertical shield wire along the selected length;
forming a second side shield wire opposite the first shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and
forming a second upper via in the first dielectric layer that extends lengthwise parallel to the second side shield wire to connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.
Step 2802 is the entry point of the flow chart 100.
In step 2804, a top vertical shield wire is formed in a top metal layer of a semiconductor chip.
In step 2806, a first side shield wire is formed in an intermediate metal layer of the semiconductor chip. The first side shield wire has a selected length, for example, the length of the signal wire to be shielded or the length of the volume of the semiconductor chip to be encapsulated.
In step 2808, a first upper via is formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire. The first upper via electrically connects the first side shield wire to the top vertical shield wire along the selected length.
In step 2810, a second side shield wire is formed opposite the first side shield wire in the intermediate metal layer of the semiconductor chip. The second side shield wire has a length corresponding to the selected length so that the second side shield wire extends lengthwise parallel to the first side shield wire.
In step 2812, a second upper via is formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire. The second upper via electrically connects the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.
Step 2814 is the exit point of the flow chart 100.
In other embodiments of the present invention, additional steps include forming a bottom vertical shield wire formed in a bottom metal layer of the semiconductor chip, forming a first lower via formed in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the bottom vertical shield wire along the selected length, and forming a second lower via in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.
Although the method of the present invention illustrated by the flowchart description above is described and shown with reference to specific steps performed in a specific order, these steps may be combined, sub-divided, or reordered without departing from the scope of the claims. Unless specifically indicated herein, the order and grouping of steps is not a limitation of the present invention.
While the invention herein disclosed has been described by means of specific embodiments and applications thereof, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope of the invention set forth in the following claims.
Claims
1. A coaxial shield for a semiconductor chip comprising:
- a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield;
- a first side shield wire formed in an intermediate metal layer of the semiconductor chip;
- a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length;
- a second side shield wire formed opposite the first side shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and
- a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.
2. The coaxial shield of claim 1 further comprising:
- a bottom vertical shield wire formed in a bottom metal layer of the semiconductor chip;
- a first lower via formed in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the bottom vertical shield wire along the selected length; and
- a second lower via formed in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.
3. The coaxial shield of claim 1 further comprising a signal wire formed in the intermediate metal layer between the first shield wire and the second shield wire.
4. The coaxial shield of claim 3 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.
5. The coaxial shield of claim 1 further comprising:
- a third side shield wire formed in an additional intermediate metal layer of the semiconductor chip wherein the third side shield wire extends lengthwise parallel to the first side shield wire along the selected length;
- a first lower via formed in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the first side shield wire along the selected length;
- a fourth side shield wire formed in the additional intermediate metal layer of the semiconductor chip wherein the fourth side shield wire extends lengthwise parallel to the second side shield wire along the length corresponding to the selected length; and
- a second lower via formed in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the fourth side shield wire to the second side shield wire along the length corresponding to the selected length.
6. The coaxial shield of claim 5 further comprising:
- a bottom vertical shield wire formed in a bottom metal layer of the semiconductor chip;
- a third lower via formed in a third dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the bottom vertical shield wire along the selected length; and
- a fourth lower via formed in the third dielectric layer that extends lengthwise parallel to the fourth side shield wire to electrically connect the fourth side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.
7. The coaxial shield of claim 5 further comprising a signal wire formed in the intermediate metal layer between the first shield wire and the second shield wire.
8. The coaxial shield of claim 7 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.
9. A method of shielding a volume in a semiconductor chip comprising steps of:
- forming a top vertical shield wire in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield;
- forming a first side shield wire in an intermediate metal layer of the semiconductor chip;
- forming a first upper via in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length;
- forming a second side shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and
- forming a second upper via in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.
10. The method of claim 9 further comprising steps of:
- forming a bottom vertical shield wire in a bottom metal layer of the semiconductor chip;
- forming a first lower via in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the bottom vertical shield wire along the selected length; and
- forming a second lower via in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.
11. The method of claim 9 further comprising a step of forming a signal wire in the intermediate metal layer between the first shield wire and the second shield wire.
12. The method of claim 11 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.
13. The method of claim 9 further comprising a steps of:
- forming a third side shield wire in an additional intermediate metal layer of the semiconductor chip wherein the third side shield wire extends lengthwise parallel to the first side shield wire along the selected length;
- forming a first lower via in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the first side shield wire along the selected length;
- forming a fourth side shield wire in the additional intermediate metal layer of the semiconductor chip wherein the fourth side shield wire extends lengthwise parallel to the second side shield wire along the length corresponding to the selected length; and
- forming a second lower via in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the fourth side shield wire to the second side shield wire along the length corresponding to the selected length.
14. The method of claim 13 further comprising steps of:
- forming a bottom vertical shield wire in a bottom metal layer of the semiconductor chip;
- forming a third lower via in a third dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the bottom vertical shield wire along the selected length; and
- forming a fourth lower via in the third dielectric layer that extends lengthwise parallel to the fourth side shield wire to electrically connect the fourth side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.
15. The method of claim 13 further comprising forming a signal wire in the intermediate metal layer between the first shield wire and the second shield wire.
16. The method of claim 15 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.
Type: Application
Filed: Aug 26, 2004
Publication Date: Mar 2, 2006
Inventor: Alexander Tetelbaum (Hayward, CA)
Application Number: 10/927,985
International Classification: H01L 29/40 (20060101);