Semiconductor test device with heating circuit
A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.
The invention is generally related to the field of semiconductor devices and, more particularly, to a semiconductor wafer having an integrally formed heating element.
BACKGROUND OF THE INVENTIONA well-known problem area affecting semiconductor reliability is thermal reliability. Consequently, thermal analysis is an important part of testing semiconductor devices. In particular, measurements of cyclic thermal loading on interconnect behavior, such as thermal fatigue and Joule heating that affect the known phenomena of electro-migration and stress migration of interconnects, are necessary to assess reliability of a semiconductor circuit. Conventional techniques for assessing the reliability of a semiconductor circuit include assembling the circuit in a ceramic or similar package, heating the package using external heating sources such as by placing the package in a temperature controlled chamber, applying heat to the package, while applying a direct current (DC) signal to the circuit and monitoring changes in the signal as the circuit is heated. For example, heat induced stress migration effects on a circuit may be studied by exposing the circuit to isothermal heating conditions and measuring the resistance change of the circuit. However, conventional thermal fatigue testing of a semiconductor circuit may become excessively time consuming due to the amount of time required to heat the circuit using external sources. For example, it may be difficult to ramp temperatures up and down as quickly as would be commonly experienced by a semiconductor device being used in the field.
BRIEF DESCRIPTION OF THE DRAWINGS
It is to be understood that the following detailed description is exemplary and explanatory only and is not to be viewed as being restrictive of the present, as claimed. These and other aspects, features and advantages of the present invention will become apparent after a review of the following description of the preferred embodiments and the appended claims.
DESCRIPTION OF PREFERRED EMBODIMENTS
The heating circuit 14 may be integrally formed with the wafer, such as by using known semiconductor manufacturing processes, and includes a plurality of circuit meanders 22 positioned adjacent the conductor trace 16. For example, the meanders 22 may be oriented parallel with a plane of the reliability test circuit 12, such as coplanar with the circuit 12, and may surround a periphery 38 of the circuit 12. The heating circuit 14 may be powered by an alternating current (AC) source 24 connected via contacts 26 for inducing heating in the heating circuit as a result of known I2R heating effects, where “I” is an amperage of the AC current provided to the heating circuit 14, and “R” is the resistance of the heating circuit 14. The heat generated by the heating circuit 14 is conducted through the surrounding insulating or dielectric material 13 of the wafer 10 to impart heating to the conductor trace 16 of the test circuit 12 positioned adjacent to the heating circuit 14. The meanders 22 of the heating circuit 14 may be configured to provide a desired level of heating to the conductor trace 16 based on parameters such as a meander length 30, a meander width 32, a spacing 36 between meanders, and a spacing 34 between the meander 22 and the conductor trace 16. In an aspect of the invention depicted in
To provide additional control over heating the reliability test circuit 12, the AC source 24 may be controlled by controller 28 to provide a desired level of heating based on parameters such as amperage (measured, for example, as a root mean square of the amplitude of an AC signal) a frequency, and/or a duty cycle of the AC current. For example, the controller 28 may control the AC source 24 to produce an AC current having an amperage and frequency sufficiently close to an amperage and frequency of an AC signal that a conductor trace may be subjected to when used in a semiconductor device. In another aspect of the invention, the AC source 24 may be cycled on and off in a desired duty cycle to expose the conductor trace 16 to cyclic thermal cycling, for example to simulate a cyclic thermal cycle that a conductor trace may be subjected to when used in a semiconductor device. The heating circuit 14 is able to provide sufficient heat to the circuit trace 16 of the test circuit 12 by conducting an AC current having a higher amperage than a current used in typical semiconductor devices without the heating circuit being subject to electro-migration. Because the heating circuit 14 conducting such an AC current may not be affected by electro-migration, the heating circuit 14 may be allowed to operate at a temperature exceeding a standard operating temperature of the semiconductor device to study effects of heating. For example, for circuits having interconnects formed of aluminum alloys, the temperatures may be raised to as high as 450° Centigrade (C), and for copper interconnects, the temperatures may be raised to as high as 500° (C), taking into account the limitations of barriers and thermal properties of the materials used for the fabrication of the semiconductor wafer.
Although several embodiments of the present invention and its advantages have been described in detail, it should be understood that mutations, changes, substitutions, transformations, modifications, variations, and alterations can be made therein without departing from the teachings of the present invention, the spirit and scope of the invention being set forth by the appended claims. For example, a skilled artisan may develop different configurations of meanders, vias, and positions of meanders and vias in different layers of a semiconductor wafer, such as to form a fence or cage configuration, to produce a desired heating of one or more reliability test circuits. In addition, different portions of the heating circuit may be separately powered to achieve a desired heating effect.
Claims
1. A semiconductor test device comprising:
- a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit; and
- a heating circuit, integrally formed with the semiconductor test device, comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.
2. The semiconductor test device of claim 1, wherein the meander of the heating circuit is oriented parallel with a plane of the test circuit.
3. The semiconductor test device of claim 2, wherein the heating circuit is positioned to be coplanar with the test circuit.
4. The semiconductor test device of claim 2, wherein the heating circuit surrounds a periphery of the test circuit.
5. The semiconductor test device of claim 2, wherein the wafer comprises at least two layers, the heating circuit being positioned in a first layer and the test circuit being positioned in a second layer.
6. The semiconductor test device of claim 5, wherein the heating circuit surrounds a periphery of the test circuit projected onto the first layer.
7. The semiconductor test device of claim 6, wherein the heating circuit overlaps a periphery of the test circuit projected onto the first layer.
8. The semiconductor test device of claim 2, wherein the wafer comprises at least three layers, a first portion of the heating circuit being positioned in a first layer, the test circuit being positioned in a second layer below the first layer, and a second portion of the heating circuit being positioned in a third layer below the second layer.
9. The semiconductor test device of claim 8, wherein the heating circuit surrounds a periphery of the test circuit projected into the first layer.
10. The semiconductor test device of claim 9, wherein the heating circuit overlaps a periphery of the test circuit projected into the first layer.
11. The semiconductor test device of claim 8, wherein the second heating circuit surrounds a periphery of the test circuit projected into the third layer.
12. The semiconductor test device of claim 11, wherein the second heating circuit overlaps a periphery of the test circuit projected into the third layer.
13. The semiconductor test device of claim 1, the heating circuit comprising a plurality of meanders, wherein at least a first portion of the meanders of the heating circuit are oriented vertically with respect to a horizontal plane of the test circuit.
14. The semiconductor test device of claim 13, wherein the at least some of the first portion of the meanders surrounds a periphery of the test circuit.
15. The semiconductor test device of claim 13, wherein the semiconductor test device comprises at least three layers, the test circuit being positioned in a second layer between a first layer and third layer, the at least some of the first portion of the meanders being positioned in the three layers so that the at least some of the first portion of meanders extend into the first, second, and third layers.
16. The semiconductor test device of claim 15, wherein the heating circuit surrounds the periphery of the test circuit.
17. The semiconductor test device of claim 15, wherein the heating circuit further comprises a second plurality of meanders positioned in the first layer and oriented parallel with the plane of the test circuit.
18. The semiconductor test device of claim 15, wherein the second plurality of meanders covers a periphery of the test circuit projected onto the first layer.
19. The semiconductor test device of claim 15, wherein the heating circuit further comprises a third plurality of meanders positioned in the third layer and oriented parallel with the plane of the test circuit.
20. The semiconductor test device of claim 15, wherein the third plurality of meanders covers a periphery of the test circuit projected onto the third layer.
21. The semiconductor test device of claim 1, wherein the heating circuit receives an alternating current heating signal from a heating circuit controller.
22. The semiconductor test device of claim 21, wherein the alternating current is turned on and off to expose the test circuit to temperature cycling at a rate corresponding to the rate at which the alternating current is turned on and off.
23. The semiconductor test device of claim 1, wherein the heating circuit comprises a heating conductor trace having a trace width and trace height approximately the same as a trace width and trace height of a conductor trace in the test circuit.
24. The semiconductor test device of claim 1 further comprising a plurality of circuit meanders positioned around the test circuit to enclose the test circuit within a space defined by the plurality of circuit meanders.
25. A semiconductor test device comprising:
- a plurality of test die having contacts for applying an electrical signal and measuring electrical parameters of the test die; and
- a plurality of heating circuits, each heating circuit associated with a respective test die, each heating circuit integrally formed within the semiconductor test device and comprising at least one circuit meander positioned adjacent the respective test die for raising a temperature of the respective test die.
26. A method for evaluating reliability in a test circuit of a semiconductor device comprising:
- integrally forming a heating circuit comprising a circuit meander positioned adjacent a test circuit in the semiconductor device;
- applying an alternating current to the heating circuit to induce heating of the heating circuit; and
- measuring an electrical parameter of the test circuit responsive to the heating of the heating circuit.
27. The method of claim 26, further comprising turning the alternating current on and off to expose the test circuit to temperature cycling at a rate corresponding to the rate at which the alternating current is turned on and off.
Type: Application
Filed: Sep 28, 2004
Publication Date: Mar 30, 2006
Inventors: Seung Kang (Sinking Spring, PA), Subramanian Karthikeyan (Schnecksville, PA), Sailesh Merchant (Macungie, PA), Lisa Mullin (Pottsville, PA)
Application Number: 10/952,453
International Classification: G01R 31/02 (20060101);