Semiconductor device having trench gate structure and manufacturing method thereof
A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.
This application is a divisional of U.S. patent application Ser. No. 10/682,111, filed Oct. 10, 2003, and is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-205983, filed Aug. 5, 2003. The entire contents of these applications are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof and is applied, for example, to a vertical MOSFET or the like having a trench gate structure.
2. Description of the Related Art
A trench gate structure configured by forming trenches (grooves) in the main surface of a semiconductor substrate and forming gate electrodes by the use of the trenches is applied to a semiconductor device such as an insulated gate bipolar transistor (IGBT) or vertical metal oxide semiconductor field effect transistor (vertical MOSFET), for example. It is mainly used for a power supply (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2000-164869) or the like.
The above vertical MOSFET having a trench gate structure has a grater current capacity and lower ON resistance in comparison with the conventional double metal oxide semiconductor (DMOS) transistor and the cost thereof can be expected to be lowered due to chip shrink. Further, since a withstand voltage of approximately several tens of volts to several hundreds of volts can be attained, it can be widely used for a switching power supply of a mobile terminal, personal computer or the like.
However, for example, a power supply system which supplies electric power is desired to perform high-speed and highly efficient operation with an increase in the operation speed of a central processing unit (CPU) of the personal computer or the like. Therefore, in the vertical MOSFET used in the output stage of a DC/DC converter power supply circuit, it becomes particularly important to enhance the switching characteristic thereof with an increase in the operation speed.
In order to enhance the switching characteristic, particularly, it is necessary to reduce the ON resistance and the feedback capacitance between the gate and drain. For example, in an element having a low withstand voltage of 100 V or less, since the proportion of the channel resistance to the ON resistance of the element becomes higher, the ON-resistance tends to become more important.
Next, a conventional semiconductor device is explained by taking the vertical MOSFET as an example.
A semiconductor device according to one aspect of the invention comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, a third semiconductor layer of the first conductivity type formed in the second semiconductor layer and electrically isolated from the first semiconductor layer, a trench formed to extend from the surface of the third semiconductor layer and penetrate the third semiconductor layer and having depth to reach at least a portion lying near the first semiconductor layer, a first insulating film formed on side walls and a bottom portion of the trench, a first electrode formed at least partly on the first insulating film in the trench and electrically isolated from the first to third semiconductor layers, and a fourth semiconductor layer of the first conductivity type formed near the trench on an interface between the first and second semiconductor layers and having an impurity concentration higher than that of the first semiconductor layer, wherein a profile of the impurity concentration of the second semiconductor layer has a first peak in a portion near an interface between the third and second semiconductor layers and a second peak which is lower than the first peak and lying in a portion near an interface between the second and fourth semiconductor layers, threshold voltage is determined based on the first peak and a dose amount of the second semiconductor region is determined based on the second peak.
A method of manufacturing a semiconductor device according to still another aspect of the invention comprises forming a second semiconductor layer of a second conductivity type on a first semiconductor layer of a first conductivity type, forming a third semiconductor layer of the first conductivity type which is electrically isolated from the first semiconductor layer on a surface region of the second semiconductor layer, forming a trench which extends from the surface of the third semiconductor layer, penetrates the third semiconductor layer and has depth to reach at least a portion lying near the first semiconductor layer, forming a first insulating film on side walls and a bottom portion of the trench, forming a fourth semiconductor layer of the first conductivity type near the trench on an interface between the first and second semiconductor layers, the fourth semiconductor layer having an impurity concentration higher than that of the first semiconductor layer, and forming a first electrode at least partly on the first insulating film in the trench, the first electrode being electrically isolated from the first to third semiconductor layers, wherein the forming the second semiconductor layer includes forming a first peak in a portion near an interface between the third and second semiconductor layers to determine threshold voltage, and forming a second peak which is lower than the first peak in a portion near an interface between the second and fourth semiconductor layers to determine a dose amount of the second semiconductor layer.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
FIGS. 7 to 19 are cross-sectional views showing manufacturing steps for forming the semiconductor device according to the first embodiment of this invention;
There will now be described embodiments of this invention with reference to the accompanying drawings. In the following explanation, common reference symbols are attached to like portions throughout the drawings.
First Embodiment First, a semiconductor device according to a first embodiment of this invention is explained with reference to FIGS. 1 to 6.
As shown in
A trench 24 is formed to extend from the surface of the source region 23 and penetrate the base region 22 and has depth to reach the epitaxial layer (drain region) 21. A gate insulating film 25 is formed on the side walls and bottom portion of the trench 24 and a gate electrode 26 is formed or filled in the trench 24 while it is electrically isolated from the respective semiconductor layers (n−-type drain region 21, p-type base region 22, n-type source regions 23) by the gate insulating film 25. Further, an n-type semiconductor layer 27 having an impurity concentration higher than that of the n−-type drain region 21 is formed on boundary portions between the gate insulating film 25, p-type base region 22 and n−-type drain region 21.
At least part of the insulating film 25 which is formed in contact with the n-type semiconductor layer 27 is formed thicker than the other portion. Further, p+-type semiconductor layers 30 are formed in contact with the n+-type source regions 23 on the p-type base region 22. A drain electrode 28 is formed on the surface (rear surface) of the n+-type semiconductor substrate 20 which is opposite to the main surface thereof. Further, a source electrode 29 is formed on the insulating film 25, n+-type source regions 23 and p+-type semiconductor layers 30. The p+-type semiconductor layer 30 and n+-type source region 23 are formed in ohmic-contact with the source electrode 29.
The impurity concentration profile of part of the p-type base region 22 which faces the gate electrode 26 with the gate insulating film 25 disposed therebetween has a first peak in a portion near the interface between the n+-type source region 23 and the p-type base region 22 and a second peak having the impurity concentration lower than that of the first peak and lying in a portion near the interface between the p-type base region 22 and the n−-type drain region 21. The threshold voltage of the MOSFET is determined based on the first peak and the dose amount of the p-type base region 22 is determined based on the second peak. The impurity concentration profile of the p-type base region 22 is explained in more detail with reference to FIGS. 2 to 4.
As shown by the solid line 31 in
Further, since the n-type semiconductor layer 27 is formed between the p-type base region 22 and the n−-type drain region 21, a steeper pn junction portion is formed between the p-type base region 22 and the n-type semiconductor layer 27. Therefore, a shape similar to a so-called BOX shape in which the impurity concentration profile of the p-type base region 22 is flat in a portion near the maximum value and the pn junction portions of the p-type base region 22 with the n+-type source region 23 and the n-type semiconductor layer 27 are steep can be attained.
In
Further, the first peak which determines the threshold voltage of the MOSFET can be positioned near an interface between the n+-type source region 23 and the p-type base region 22 or an interface between the n-type semiconductor layer 27 and the p-type base region 22.
Thus, a shape similar to the BOX shape can be attained by forming the peak of the impurity concentration of the p-type base region 22 in a portion near the n-type semiconductor layer 27. Further, by forming the above profile of the impurity concentration of the p-type base region 22, the channel length (the distance between the n+-type source region 23 and the n-type semiconductor layer 27) can be shortened while the integral value of an amount of the p-type impurity doped into the p-type base region 22 is maintained. Therefore, the ON resistance can be reduced and the switching characteristic can be enhanced.
As described above, since the integral value of an amount of the p-type impurity doped into the p-type base region 22 is maintained, an impurity dose amount which prevents a leakage current from flowing even when reverse bias voltage is applied between the n+-type source region 23 and the n−-type drain region 21 can be acquired. Therefore, high withstand voltage can be attained. Further, since the channel length can be reduced, the ON resistance can be lowered while the high withstand voltage is maintained. As a result, a vertical MOSFET having a high withstand voltage of approximately 300 V, for example, can be provided.
Further, since the impurity concentration profile is approximately set to a BOX shape as shown in
Further, the n-type semiconductor layer 27 having the impurity concentration higher than that of the n−-type drain region 21 is formed on the boundary portions between the gate insulating film 25, p-type base region 22 and n−-type drain region 21. Therefore, the ON resistance can be reduced and a current path for a current to pass through the channel can be acquired.
Further, the film thickness of a portion of the insulating film 25 which is formed in contact with the n-type semiconductor layer 27 is made larger than the film thickness of the other portion. Therefore, it can be prevented that the feedback capacitance between the gate electrode 26 and the n−-type drain region 21 becomes large to elongate the switching time. That is, an increase in the feedback capacitance can be suppressed and the switching time can be reduced. The film thickness of the other portion is made smaller than the film thickness of the portion of the insulating film 25 which is formed in contact with the n-type semiconductor layer 27. Therefore, even when gate voltage is applied to the gate electrode 26, there occurs no possibility that the tendency of the channel to be inverted will become weak and the ON resistance will become higher. Thus, the ON resistance and the feedback capacitance between the gate electrode 26 and the n−-type drain region 21 can be reduced and the switching time can be further shortened.
Another example of the impurity concentration along the A-A′ line in
By providing the profile as shown in
In
Next, it is assumed that the width of a portion of the n−-type drain region 21 which is formed in contact with the bottom portion of the trench 24 is set at X1 [μm] and the minimum width (cell pitch width) of an repetition interval of the gate electrodes 26 in the gate width direction is set at X2 [μm]. It is desirable to set X1 and X2 so as to satisfy the relation of 0.05<X1/X2<0.25. This is explained in more detail with reference to
Further, it is assumed that the depth from the surface of the n+-type source region 23 to the deepest bottom portion of the p-type base region 22 is set at Y2 [μm] and the depth from the deepest bottom portion of the trench 24 to the deepest bottom portion of the p-type base region 22 is set at Y1 [μm]. It is desirable to set Y1 and Y2 so as to satisfy the relations of 0<Y1<1.2 [μm] and Y2<3 [μm]. The depth Y1 is explained in more detail with reference to
Since the channel length increases when Y2 increases, the ON resistance increases. Therefore, it is desirable to set Y2 so as to satisfy the relation of Y2<3 [μm].
As described above, by setting the depths Y1, Y2 to satisfy the relations of 0<Y1<1.2 [μm] and Y2<3 [μm], the ON resistance can be further reduced.
Next, a manufacturing method of the semiconductor device according to the first embodiment is explained with reference to FIGS. 7 to 14 by using the vertical MOSFET shown in
First, as shown in
Then, photoresist is coated on the oxide film 42 and the thus formed photoresist film is exposed and developed to form a pattern (not shown) which is used to form a trench on the oxide film 42. After this the photoresist film is removed.
Next, as shown in
As the step of forming the trench 24, it is possible to use a LOCOS (Local Oxidation of Silicon) method, for example. The trench 24 can be formed shallow by using the above method.
Next, as shown in
After this, as shown in
The film thickness of the oxide film 25 formed on the side surface of the trench 24 is approximately 400 angstrom or less and the film thickness of the insulating film 25 formed on the bottom portion of the trench 24 is approximately 500 to 1000 angstrom, for example. Further, the oxide film 25 on the bottom portion of the trench 24 can be formed by separating the insulating film from the side surface of the trench 24 after the n-type semiconductor layer 27 is formed and forming a thick oxide film by use of the thermal oxidation method, for example.
Next, as shown in
After this, a p-type impurity such as boron (B) or the like is doped into the n−-type drain region 21 by use of the ion-implantation method, for example. In this case, the acceleration voltage is set at an adequately selected level and ion-implantation is performed to form a peak of the impurity concentration in a deep position. Then, by performing the heat treatment at high temperatures (for example, 1000° C. or more) to activate implanted ions, a p-type base region 22 whose impurity concentration profile is made similar to the BOX shape is formed.
As the method for forming the p-type base region 22 and n-type semiconductor layer 27, a selective epitaxial growth method or the like can be used.
Next, as shown in
After this, as shown in
By the above steps, the vertical MOSFET shown in
In the above manufacturing steps, after the n-type semiconductor layer 27 is formed in a portion in contact with the bottom portion of the trench 25, impurity is ion-implanted to form an impurity concentration peak in a deeper portion and is thermally diffused to form the p-type base region 22. By the above steps, the n-type semiconductor layer 27 functions as a stopper for the p-type impurity to determine the lower limit of the impurity concentration of the p-type base region 22 in the step of ion-implanting the p-type impurity into the deep portion and in the thermal diffusion step performed after the ion-implanting step. Therefore, the pn junction between the n+-type source region 23 and the n-type semiconductor layer 27 can be made steep. Thus, the impurity concentration profile of the p-type base region 22 can be made closer to the BOX shape. Since the trench 24 can be formed shallower in order to further make the impurity concentration profile closer to the BOX shape, it becomes easier to set Y1 so as to satisfy the relation of 0<Y1<1.2 [μm].
The p-type base region 22 is formed by performing the step of ion-implanting p-type impurity ions only once. Therefore, the number of manufacturing steps can be reduced and the manufacturing cost can be lowered.
Further, the n-type semiconductor layer 27 can be formed by use of a selective epitaxial growth method. Also, it is desirable to use arsenic (As) as ions to be implanted to form the n-type semiconductor layer 27. By using arsenic, diffusion in the width direction of the trench 24 can be attained without fail.
Next, a manufacturing method of the semiconductor device having the impurity concentration profile of the p-type base region 22 as shown in
First, as shown in
Then, as shown in
After this, photoresist is coated on the oxide film 49 and the thus formed photoresist film is exposed and developed to form a pattern (not shown) which is used to form a trench on the oxide film 49. Next, as shown in
Next, as shown in
Then, as shown in
After this, the oxide film 49 is removed. Then, as shown in
After this, the vertical MOSFET shown in
In the above manufacturing steps, the impurity concentration profile of the p-type semiconductor layer can be made similar to the BOX shape by the two ion-implantation steps. Therefore, ion-implantation is performed to mainly set the threshold voltage (Vth) to a preset value in a shallow layer in the first ion-implantation step. Then, in the second ion-implantation step, ion-implantation is performed to mainly set the integral value of the impurity concentration to a preset value in a deep layer. As described above, the impurity concentration profile can be set closer to the BOX shape by separately performing the ion-implantation steps. The number of ion-implantation steps is not limited to two and it is of course possible to form the p-type base region 22 by performing three or more ion-implantation steps.
Further, an n-type semiconductor layer 27 is formed on the bottom portion of the trench 24 before the second ion-implantation step. Therefore, the n-type semiconductor layer 27 can be used as a stopper in the second ion-implantation step and the later heat treatment process. Further, the lower limit of the impurity concentration of the p-type base region 22 can be determined and the pn junction between the n+-type source region 23 and the n−-type drain region 21 can be made steep. Therefore, the impurity concentration profile of the p-type base region 22 can be set closer to the BOX shape. The other effect which is the same as that shown in FIGS. 7 to 14 can be attained.
Second Embodiment A semiconductor device according to a second embodiment of this invention is explained with reference to
The current passage acquiring layer 51 is used to acquire a passage of a current flowing between an n+-type source region 23 and the n−-type drain region 21 in the p-type base region 22 and reduce the feedback capacitance between the gate and drain. As the current passage acquiring layer 51, for example, a layer containing carbon or an n-type layer whose impurity concentration is higher than that of the n−-type drain region 21 can be used.
Further, like the first embodiment, it is desirable to set X1, X2 and Y1 so as to satisfy the relation of 0.05<X1/X2<0.25 and Y2<3 [μm].
The passage of a current flowing between the n+-type source region 23 and the n−-type drain region 21 in the p-type base region 22 can be acquired and the feedback capacitance between the gate and drain can be reduced by use of the current passage acquiring layer 51.
When the current passage acquiring layer 51 is formed of an n-type high-impurity concentration layer, the p-type base region 22 in the second embodiment has an impurity concentration profile as shown in
Further, if the trench 24 is formed to penetrate the current passage acquiring layer 51 and extend into the n−-type drain region 21, the same effect as described above can be attained.
Next, a manufacturing method of the semiconductor device according to the second embodiment is explained with reference to
As shown in
Then, photoresist is coated on the oxide film 42 and the thus formed photoresist film is exposed and developed to form a pattern (not shown) which is used to form a trench on the oxide film 42. Next, the photoresist film is removed. Further, as shown in
After this, the semiconductor device shown in
In the above manufacturing steps, the current passage acquiring layer 51 is formed on the n−-type drain region 21 before the p-type base region 22 is formed. Therefore, impurities in the p-type base region 22 and current passage acquiring layer 51 can be prevented from being diffused into each other. Thus, the pn junction between the p-type base region 22 and the current passage acquiring layer 51 can be made steep. As a result, the impurity concentration profile of the p-type base region 22 can be set closer to the BOX shape.
Third Embodiment A semiconductor device according to a third embodiment of this invention is explained with reference to
With the above structure, the facing area between a gate electrode 26 and the n−-type drain region 21 used as a drain can be reduced. Therefore, the feedback capacitance between the gate and drain can be reduced.
Next, a manufacturing method of the semiconductor device shown in
Next, a thick insulating film 42 (mask member) used to form a trench is formed on the oxide film 41 by the thermal oxidation method, for example. Then, photoresist is coated on the oxide film 42 and the thus formed photoresist film is exposed and developed to form a pattern (not shown) which is used to form a trench on the oxide film 42. Next, the photoresist film is removed. Further, as shown in
Then, an insulating film 25 is formed in the internal portion of the trench 24 by the thermal oxidation method. Further, an n-type impurity such as phosphorus (P) or arsenic (As) is doped into a portion of the n−-type drain region 21 which is formed in contact with the bottom portion of the trench 24 by the ion-implantation method, for example, so as to form an n-type semiconductor layer 27. In the above step, at least the width of the trench 24 is made larger than X1. It is desirable to use phosphorus (P) as the n-type impurity used in the step of forming the n-type semiconductor layer 27.
After this, the semiconductor device shown in
It is desirable to use phosphorus (P) in the step of forming the n-type semiconductor layer 27. Since phosphorus (P) can be diffused to a large extent in the depth direction of the trench in the thermal oxidation step and is diffused into the insulating film 25, a region sandwiched between portions of the p-type base region 22 can be freely adjusted by the time and temperature of the thermal diffusion process. Therefore, the n-type semiconductor layer 27 can be easily formed so as to set at least the width of the trench 24 larger than X1.
Fourth Embodiment Next, a semiconductor device according to a fourth embodiment of this invention is explained with reference to
As described above, since the surface of the gate electrode 26 is set higher than the surface of the trench 24, the volume of the gate electrode 26 increases. Therefore, the gate resistance of the gate electrode 26 can be lowered. Further, since a desired interval can be attained between the low-resistance layer 55 and the n+-type source region 23 and p+-type semiconductor layer 30 on the semiconductor surface, sufficient insulation therebetween can be attained.
On the other hand, Y2 is maintained, that is, the channel length is kept unchanged. As a result, the gate resistance can be reduced while the ON resistance is maintained. Further, since the surface of the gate electrode 26 is set higher than the surface of the trench 24, the chip size in the X2 direction, that is, in the gate width direction of the gate electrode 26 can be reduced.
In addition, the switching characteristic can be enhanced by lowering the gate resistance. Therefore, when the semiconductor device shown in
Since the low-resistance layer 55 is formed on part of the side surface and the upper surface of the gate electrode 26, the gate resistance can be further reduced. Even when the low-resistance layer 55 is formed on the surface of the n+-type source region 23 or p+-type semiconductor layer 30, the same effect can be attained.
It is of course possible to combine the structure of the gate electrode 26 or low-resistance layer 55 shown in
Next, a manufacturing method of the semiconductor device shown in
First, an n−-type drain region 21, trench 24, insulating films 25, 41 and n-type semiconductor layer 27 are formed on the main surface of an n+-type semiconductor substrate by the same steps as the steps shown in FIGS. 7 to 9.
Next, as shown in
Then, as shown in
Next, for example, an oxide film is formed on the entire surface and a side wall is formed on the side surface of polysilicon which projects from the silicon surface by subjecting the oxide film to the anisotropic etching process by the RIE method. After this, for example, a Ti film (not shown) is formed on the entire surface. Further, the Ti film is subjected to the high-temperature process of temperatures higher than 850° C. to form a low-resistance layer 55 such as a TiSi2 film by the wet process. It is known that the TiSi2 film is aggregated to raise the resistivity thereof if the high-temperature process of temperatures higher than 850° C. is performed in the above step after the low-resistance layer 55 is formed. Therefore, the step of lowering the resistance of the gate electrode material 26 is performed after the n+-type source region 23 and p-type semiconductor layer 30 are formed. That is, the heating process is performed after a metal film (Ti film) is deposited on the gate electrode 26 by a salicide step, for example. Thus, the low-resistance layer 55 is formed by the above step.
After this, an insulating film 24 which provides insulation between the gate electrode material 26 and low-resistance layer 55 and the n+-type source region 23 and p-type semiconductor layer 30 is formed. Then, the semiconductor device shown in
It is also possible to remove the insulating film 25 on the surface of the p-type base region 22 after the step of forming the gate electrode 26, form the n+-type source region 23 and p-type semiconductor layer 30 and perform the salicide step. By the above step, a silicide layer can be simultaneously formed on the surfaces of the p-type semiconductor layer 30 and at least part of the n+-type source region 23. Therefore, the manufacturing cost can be lowered.
Further, a polysilicon layer can be formed at substantially the same height as a mask material directly on the trench by performing an etching process after the polysilicon layer is deposited with the insulating film 41 or 42 shown in FIGS. 7 to 9 left behind to attain the semiconductor device shown in
A semiconductor device according to a fifth embodiment of this invention is explained with reference to
Further, the two portions of the n-type semiconductor layer 27 are formed in contact with the p-type base region 22 to sandwich the trench 24. The n-type semiconductor layer 27 is formed with the impurity concentration higher than that of the n−-type drain region 21.
By forming the trench with the above structure, the ON resistance can be further reduced. Further, by using the n-type semiconductor layer 27 with the above structure, the channel length can be made smaller. As a result, the switching characteristic can be enhanced.
The film thickness of an insulating film formed at least on the bottom portion of the trench 24 can be made larger than that of an insulating film 25 formed on the side wall of the trench 24. Therefore, the high withstand voltage can be maintained even if the trench 24 is formed deep.
Next, a manufacturing method of the semiconductor device shown in
First, an n−-type drain region 21, trench 24, insulating film 25 and n-type semiconductor layer 27 are formed on the main surface of an n+-type semiconductor substrate 20 by the same steps as those shown in FIGS. 7 to 9. In this case, it is desirable to use an SiN film or the like deposited and formed by the CVD method, for example, as the insulating film 25.
Next, for example, the etching process is performed by the RIE method so as to elongate the trench 24 so that the trench 24 can penetrate the n-type semiconductor layer 27 and reach the deep portion of the n−-type drain region 21. Further, the film thickness of the insulating film on the side wall of the elongated trench 24 and the film thickness of the insulating film 25 on the bottom portion thereof are made larger by use of the thermal oxidation method, for example.
After this, the semiconductor device shown in
As described above, the insulating film 25 such as an SiN film is used to form the trench 24 before it is elongated, then the trench is formed deeper with the insulating film 25 left behind only on the side wall thereof and, after this, an insulating film with larger film thickness is formed on the bottom portion of the trench 24 which has been elongated. Thus, it becomes possible to form a thin insulating film on the side wall of the trench 24 used as a channel portion and a thick insulating film on the bottom portion of the elongated trench 24. Therefore, the dielectric breakdown strength can be enhanced and the high withstand voltage can be maintained even if the trench is formed deep.
The p-type base region 22 is formed after the n-type semiconductor layer 27 is formed. Therefore, the two portions of the n-type semiconductor layer 27 which are formed to sandwich the trench 24 can be prevented from being diffused into the n−-type drain region 21 in the step of forming the p-type base region 22.
In the explanation of the above embodiments, the first conductivity type is set to n and the second conductivity type is set to p. However, the same effect as that of the embodiments of this invention can be attained even if the first conductivity type is set to p and the second conductivity type is set to n.
Only the schematic cross sections of the semiconductor devices explained in the first to fifth embodiments are shown and an example in which the n+-type source region 23 is formed to always lie adjacent to the trench 24 with the insulating film 25 disposed therebetween is shown. However, in a semiconductor device having the same cross section, for example, the n+-type source region 23 and p+-type layer 30 can be arranged to cross a direction in which the trench 24 extends at right angles and the n+-type source regions 23 and p+-type layers 30 can be alternately arranged in the plane layout structure.
In explaining this invention, the vertical MOSFET is used as one example. However, this invention can easily be applied to another semiconductor device such as an IGBT.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
1. A method of manufacturing a semiconductor device comprising:
- forming a second semiconductor layer of a second conductivity type on a first semiconductor layer of a first conductivity type;
- forming a trench which extends from the surface of the second semiconductor layer, penetrates the second semiconductor layer and has depth to reach at least a portion lying near the first semiconductor layer;
- forming an insulating film on side walls and a bottom portion of the trench;
- forming a third semiconductor layer of the first conductivity type in the first semiconductor layer near the bottom of the trench, the third semiconductor layer having an impurity concentration higher than that of the first semiconductor layer;
- forming a fourth semiconductor layer of the second conductivity type by ion-implantating using the third semiconductor layer as a stopper in a region deeper than the second semiconductor layer; and
- forming a gate electrode at least partly on the insulating film in the trench.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the forming the second semiconductor layer includes forming a first peak by performing a first ion-implantation process, and the forming the fourth semiconductor layer includes forming a second peak by selecting acceleration voltage higher than that used in the first ion-implantation process and performing a second ion-implantation process.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the second and the fourth semiconductor layers are formed as a base layer.
4. The method of manufacturing a semiconductor device according to claim 2, wherein the first peak and the second peak are formed along and directly face a side surface of the trench.
5. The method of manufacturing a semiconductor device according to claim 2, further comprising forming a source region in the second semiconductor layer, and the first peak is formed in a portion near an interface between the source region and second semiconductor layer, and the second peak is formed in a portion near an interface between the third and the fourth semiconductor layers.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the first peak determines a threshold voltage, and the second peak determines a dose amount of the impurities.
7. The method of manufacturing a semiconductor device according to claim 2, wherein the second peak is lower than the first peak.
8. The method of manufacturing a semiconductor device according to claim 1, further comprising increasing a film thickness of the insulating film on the bottom portion of the trench, after forming the fourth semiconductor layer.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a source region is performed before forming the trench.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a source region is performed after forming the trench.
11. The method of manufacturing a semiconductor device according to claim 9, further comprising forming a fifth semiconductor layer of the second conductivity type in the second semiconductor layer which is adjacent to the source region, after forming the source region.
12. The method of manufacturing a semiconductor device according to claim 10, further comprising forming a fifth semiconductor layer of the second conductivity type in the second semiconductor layer which is adjacent to the source region, after forming the source region.
13. The method of manufacturing a semiconductor device according to claim 1, wherein forming the fourth semiconductor layer includes a thermal diffusion after the ion-implanting.
14. A method of manufacturing a semiconductor device comprising: forming a first semiconductor layer of a first conductivity type;
- forming a first part of a base layer of a second conductivity type in the first semiconductor layer;
- forming a trench in the first and the second semiconductor layers;
- forming an insulating film on side walls and a bottom portion of the trench;
- forming a second semiconductor layer of the first conductivity type in the first semiconductor layer near the bottom of the trench, the second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer;
- forming a second part of the base layer of the second conductivity type in the first semiconductor layer using the second semiconductor layer as a stopper in a region deeper than the first part of the base layer; and
- forming a gate electrode at least partly on the insulating film in the trench,
- wherein the base layer is formed by performing ion-implantation a plurality of times before and after forming the second semiconductor layer.
15. The method of manufacturing a semiconductor device according to claim 14, further comprising forming a third semiconductor layer of the first conductivity type in the first part of the base layer, before forming the trench.
16. The method of manufacturing a semiconductor device according to claim 14, further comprising forming a source region in the first part of the base layer, after forming the second part of the base layer.
17. The method of manufacturing a semiconductor device according to claim 15, further comprising forming a fourth semiconductor layer of the second conductivity type in the first part of the base layer which is adjacent to the source region, after forming the source region.
18. The method of manufacturing a semiconductor device according to claim 16, further comprising forming a fourth semiconductor layer of the second conductivity type in the first part of the base layer which is adjacent to the source region, after forming the source region.
19. The method of manufacturing a semiconductor device according to claim 14, wherein the forming the first and the second parts of the base layer includes a thermal diffusion.
Type: Application
Filed: Feb 27, 2006
Publication Date: Jun 29, 2006
Inventors: Syotaro Ono (Yokohama-shi), Yusuke Kawaguchi (Miura-gun), Akio Nakagawa (Fujisawa-shi)
Application Number: 11/362,150
International Classification: H01L 29/94 (20060101);