THREE-DIMENSIONAL MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.
This application is a continuation of a prior application Ser. No. 10/906,779, filed Mar. 7, 2005, which now is allowed. The prior application Ser. No. 10/906,779 is a continuation application of a prior application Ser. No. 10/604,042, filed Jun. 24, 2003, which now is abandoned. All disclosures are incorporated herewith by reference.
BACKGROUND OF THE INVENTION1. Field of Invention
The present invention relates to a three-dimensional memory structure and manufacturing method thereof. More particularly, the present invention relates to a vertically stacked three-dimensional memory array and manufacturing method thereof.
2. Description of Related Art
Due to the rapid development of integrated circuit technologies, each integrated circuit contains an increasing number of electronic devices. Memory is a common semiconductor device most often used inside a personal computer and some electronic equipment. Earlier, each memory includes an array of memory cells on a single layer over a semiconductor substrate. The cross over area between each column and row constitutes a specified memory cell address. In general, memory cells within the same column or the same row have a common conductive wire connection. With this design, the only way to increase the level of integration is to reduce the size of each memory cell. A vertical stacked non-volatile memory structure is disclosed in U.S. Pat. No. 6,351,406. The method includes forming a three-dimensional multi-layered array memory structure over a substrate with each array layer having a plurality of memory cells such that the memory cells in the same column or row are connected to a common conductive wire.
Although U.S. Pat. No. 6,351,406 has proposed a method of manufacturing a vertical stacked non-volatile memory for increasing overall level of device integration, the method requires N+1 photolithographic processes to form the N memory cell array layers over a substrate. Along with the photolithographic steps needed to producing interconnecting vias, the total number of processing steps is exceptionally high. In other words, the stacked three-dimensional memory is rather difficult and costly to manufacture.
SUMMARY OF THE INVENTIONAccordingly, one object of the present invention is to provide a three-dimensional memory structure and manufacturing method thereof that only involves simple processing steps.
A second object of this invention is to provide a three-dimensional memory structure and manufacturing method thereof capable of increasing overall level of integration of the memory devices.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a three-dimensional memory structure. The memory structure comprises a multiple of stacked circuits. The first stacked circuit includes two conductive layers, an n-type polysilicon layer, a p-type polysilicon layer and an anti-fuse. The n-type polysilicon layer in the first stacked circuit is located between the two conductive layers and the p-type polysilicon layer is located between the n-type polysilicon layer and one of the two conductive layers. The anti-fuse is located between the n-type polysilicon layer and the other one of the two conductive layers. Hence, the first stacked circuit includes a conductive layer/p-type polysilicon layer/n-type polysilicon layer/anti-fuse/conductive layer (C/P/N/A/C) setup and a conductive layer/anti-fuse/n-type polysilicon layer/p-type polysilicon layer/conductive layer (C/A/N/P/C) setup.
The second stacked circuit of the three-dimensional memory structure includes two conductive layers, an n-type polysilicon layer, a p-type polysilicon layer and an anti-fuse. The p-type polysilicon layer of the second stacked circuit is located between the two conductive layers and the n-type polysilicon layer is located between the p-type polysilicon layer and one of the conductive layers. The anti-fuse is located between the p-type polysilicon and the other one of the two conductive layers. Hence, the second stacked circuit includes a conductive layer/anti-fuse/p-type polysilicon layer/n-type polysilicon layer/conductive layer (C/A/P/N/C) setup and a conductive layer/n-type polysilicon layer/p-type polysilicon layer/anti-fuse/conductive layer (C/N/P/A/C) setup. The second stacked circuit and the first stacked circuit cross over each other in the vertical dimension. Therefore, a total of four different methods of combining the first stacked circuit and the second stacked circuit are possible. In addition, according to the memory capacity, one of the four aforementioned configurations can be used to form more stacked circuits over the substrate.
This invention also provides a method of fabricating a three-dimensional memory structure. First, an n-type polysilicon layer/conductive layer/anti-fuse/n-type polysilicon layer (N/C/A/N) stack structure is formed over a substrate. The N/C/A/N stack structure is patterned to form an array of linear first stacked lines. Thereafter, a dielectric layer is formed in the space between the first stacked lines above the substrate. The dielectric layer is planarized to expose the topmost n-type polysilicon layer of the first stacked lines. A p-type polysilicon/conductive layer/anti-fuse/p-type polysilicon layer (P/C/A/P) stacked structure is formed over the topmost n-type polysilicon layer of the first stacked line. Next, the P/C/A/P stacked structure and the topmost n-type polysilicon layer of the first stacked line is patterned to form an array of linear second stacked lines that crosses over the first stacked lines vertically. Another dielectric layer is formed in the space between the second stacked lines above the anti-fuse of the first stacked lines. The dielectric layer is again planarized to expose the topmost p-type polysilicon layer of the second stacked lines. The overlapping areas between the first stacked lines and the second stacked lines forms an array of cylindrical memory cells. The aforementioned processing steps are repeated to form more stacked lines and hence build up a three-dimensional memory structure.
A three-dimensional multi-layered memory array structure is used in this invention. The odd-numbered memory cell array and the even-numbered memory cell array of the three-dimensional structure are alternately stacked over each other and oriented in a direction perpendicular to each other above the substrate. Hence, substrate area required to accommodate the memory device is reduced and overall level of integration of the memory chip is increased. Moreover, in the fabrication process, the anti-fuse is used as an etching stop layer. Since the anti-fuse is fabricated from silicon oxide, the anti-fuse has a relatively high etching selectivity ratio relative to the polysilicon and the conductive layer. Therefore, the processing window is increased and the steps for fabricating the three-dimensional memory are simplified. Furthermore, the steps of forming via is to break through the anti-fuse after etching stop on the anti-fuse, so it can effectively etch stop on the conductive layer. Therefore, it can prevent via from forming p-n or n-p rectification junction due to the conductive layer being perforated, resulting in non-conducting.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
In general, there are other types of setups for the various layers inside the aforementioned stack circuit. For example, the first stack circuit 21 can have an n-type polysilicon/anti-fuse/conductive layer/n-type polysilicon (N/A/C/N) setup and the second stack circuit 31 can have a p-type polysilicon/anti-fuse/conductive layer/p-type polysilicon setup. In fact, there are four different setups for combining the first stack circuit 21 and the second stack circuit 31 together.
The n-type polysilicon layer 202, the conductive layer 204, the anti-fuse 206 and the n-type polysilicon layer 208 are patterned to form an array of linear first stack circuits 210 each having an n-type polysilicon/conductive layer/anti-fuse/n-type polysilicon (N/C/A/N) composite layer setup. Thereafter, a dielectric layer 10 is formed in the space between the first stack circuits 210. The dielectric layer 10 is, for example, a silicon oxide layer, a silicon nitride layer or a spin-coated glass layer. The dielectric layer 10 is formed, for example, by performing a high-density plasma chemical vapor deposition or a spin-coating process.
A portion of the dielectric layer 10 is removed to expose the topmost n-type polysilicon layer 208. The dielectric layer 10 above the n-type polysilicon layer 208 is removed, for example, by chemical-mechanical polishing or conducting an etching back process.
As shown in
The p-type polysilicon layer 212, the conductive layer 214, the anti-fuse 216 and the p-type polysilicon layer 218 are patterned to form an array of linear second stack circuits 210 each having an n-type polysilicon/p-type polysilicon/conductive layer/anti-fuse/p-type polysilicon (N/P/C/A/P) composite layer setup. The second stack circuits 220 are oriented in a direction perpendicular to and vertically above the first stack circuits 210. In patterning the second stack circuits 220, the anti-fuse serves as an etching stop layer. Thereafter, a dielectric layer 12 is formed in the space between the second stack circuits 220. The dielectric layer 12 is, for example, a silicon oxide layer, a silicon nitride layer or a spin-coated glass layer. The dielectric layer 12 is formed, for example, by performing a high-density plasma chemical vapor deposition or a spin-coating process.
A portion of the dielectric layer 12 is removed to expose the topmost p-type polysilicon layer 218. The dielectric layer 12 above the p-type polysilicon layer 218 is removed, for example, by chemical-mechanical polishing or conducting an etching back process.
As shown in
As shown in
The n-type polysilicon layer 222, the conductive layer 224, the anti-fuse 226, the n-type polysilicon layer 228 and the p-type polysilicon layer 218 are patterned to form an array of linear third stack circuits 230 each having a p-type polysilicon/n-type polysilicon/conductive layer/anti-fuse/n-type polysilicon (P/N/C/A/N) composite layer setup. The third stack circuits 230 are oriented in the same direction as the first stack circuits 210. Thereafter, a dielectric layer 18 is formed in the space between the first stack circuits 210, for example, by performing a high-density plasma chemical vapor deposition or a spin-coating process. The dielectric layer 18 is, for example, a silicon oxide layer, a silicon nitride layer or a spin-coated glass layer.
A portion of the dielectric layer 18 is removed to expose the topmost n-type polysilicon layer 228. The dielectric layer 18 above the n-type polysilicon layer 228 is removed, for example, by chemical-mechanical polishing or conducting an etching back process.
As shown in
The p-type polysilicon layer 232, the conductive layer 234, the anti-fuse 236, the p-type polysilicon layer 238 and the n-type polysilicon layer 228 are patterned to form an array of linear fourth stack circuits 240 each having a n-type polysilicon/p-type polysilicon/conductive layer/anti-fuse/p-type polysilicon (N/P/C/A/P) composite layer setup. The fourth stack circuits 240 are oriented in a direction identical to the second stack circuits 220. Thereafter, a dielectric layer 20 is formed in the space between the fourth stack circuits 240 above the anti-fuse 226. The dielectric layer 20 is, for example, a silicon oxide layer, a silicon nitride layer or a spin-coated glass layer. The dielectric layer 20 is formed, for example, by performing a high-density plasma chemical vapor deposition or a spin-coating process.
A portion of the dielectric layer 20 is removed to expose the topmost p-type polysilicon layer 238. The dielectric layer 20 above the p-type polysilicon layer 238 is removed, for example, by chemical-mechanical polishing or conducting an etching back process.
As shown in
As shown in
The aforementioned steps may be repeated to stack alternately crossed circuits above the substrate so that a truly three-dimensional memory structure is formed.
In this invention, a three-dimensional multi-layered memory array structure is produced. The odd-numbered memory cell array and the even-numbered memory cell array of the three-dimensional structure are alternately stacked over each other and oriented in a direction perpendicular to each other above the substrate. Hence, substrate area required to accommodate the memory device is reduced and overall level of integration of the memory chip is increased. Moreover, in the fabrication process, the anti-fuse is used as an etching stop layer. Since the anti-fuse is fabricated from silicon oxide, the anti-fuse has a relatively high etching selectivity ratio relative to the polysilicon and the conductive layer. Therefore, the processing window is increased and the steps for fabricating the three-dimensional memory are simplified. Furthermore, the steps of forming via is to break through the anti-fuse after etching stop on the anti-fuse, so it can effectively etch stop on the conductive layer Therefore, it can prevent via from forming p-n or n-p rectification junction due to the conductive layer being perforated, resulting in non-conducting.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims
1. A memory structure, comprising:
- a first conductor;
- a second conductor cross over the first conductor;
- a third conductor cross over the second conductor;
- a first diode between the first conductor and the second conductor;
- a second diode between the second conductor and the third conductor, wherein the directions of currents flowing through the first diode and second diode are opposite;
- a first anti-fuse between the first conductor and the second conductor; and
- a second anti-fuse between the second conductor and the third conductor.
2. The memory structure of claim 1, wherein the first anti-fuse is between the first conductor and the first diode.
3. The memory structure of claim 1, wherein the first anti-fuse is between the first diode and second conductor.
4. The memory structure of claim 1, wherein the first anti-fuse is within the first diode.
5. The memory structure of claim 1, wherein the first anti-fuse and the second anti-fuse comprise oxide.
6. A memory structure, comprising:
- a first conductor;
- a second conductor cross over the first conductor;
- a third conductor cross over the second conductor;
- a first layer of a first conductivity between the first conductor and the second conductor, a second layer of the first conductivity between the second conductor and the third conductor;
- a third layer of a second conductivity between the first layer and the second conductor;
- a fourth layer of the second conductivity between the second conductor and the second layer;
- a first anti-fuse between the first conductor and the second conductor; and
- a second anti-fuse between the second conductor and the third conductor.
7. The memory structure of claim 6, wherein the first anti-fuse is between the first conductor and the first layer.
8. The memory structure of claim 6, wherein the first anti-fuse is between the first layer and the second conductor.
9. The memory structure of claim 6, wherein the first anti-fuse is between the first layer and the first layer of the second conductivity.
10. The memory structure of claim 9, wherein the first conductivity comprises n type.
11. The memory structure of claim 9, wherein the second conductivity comprises p type.
12. The memory structure of claim 9, wherein the first conductivity comprises p type.
13. The memory structure of claim 9, wherein the second conductivity comprises n type.
14. The memory structure of claim 9, wherein the first anti-fuse and the second anti-fuse comprise oxide.
Type: Application
Filed: Jan 27, 2006
Publication Date: Sep 7, 2006
Inventors: Erh-Kun Lai (Taichung), Ming-Chung Liang (Hsinchu)
Application Number: 11/307,221
International Classification: H01L 29/00 (20060101);