Leaded Package Integrated Circuit Stacking
There is provided a stacked IC module including first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages, and a flexible circuit disposed in part between the first and second leaded packages, wherein the flexible is folded back on itself to create an arcuate connective field that is compressed to have conformity with the plural leads of the first and second leaded packages.
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This application is a continuation of U.S. patent application Ser. No. 11/248,662 filed Oct. 11, 2005, which is incorporated by reference.
TECHNICAL FIELDThis invention relates to stacking leaded integrated circuit devices. More particularly, this invention relates to stacks of leaded integrated circuits and associated flex circuitry.
BACKGROUNDA variety of systems and techniques are known for stacking packaged integrated circuits. Some techniques are devised for stacking chip-scale packaged devices (CSPs) while other systems and methods are better directed to leaded packages which exhibit a set of leads extending from at least one lateral side of a typically rectangular package.
Memory devices are packaged in both chip-scale (CSP) and leaded packages. However, techniques for stacking CSP devices are typically not optimum for stacking leaded devices. Although CSP devices are gaining market share, in many areas integrated circuits continue to be packaged in high volumes in leaded packages. For example, the well-known flash memory integrated circuit is typically packaged in leaded packages with fine-pitched leads emergent from one or both sides of a package. A common package for flash memory is a fine pitch thin small outline package commonly known as the TSOP. Flash circuitry in TSOP packaging typically differs from common TSOP-packaged DSRAMs in that flash TSOPs typically exhibit fine pitch leads emergent from the shorter pair of the lateral sides of the package while DRAM TSOPs typically exhibit leads emergent from the longer pair of sides of the package.
The assignees of the present invention, Staktek Group L.P., has developed a wide variety of techniques, systems and designs for stacks and stacking with both leaded and CSP devices. In leaded package stacking, Staktek Group L.P. has developed rail bus systems that interconnect the leads of stacked leaded IC devices by use of rails. The present assignee also owns, for example, U.S. Pat. No. 6,572,387 issued Jun. 3, 2003 and U.S. patent application Ser. No. 10/449,242 published as Pub. No. 2003/0203663 A1 which disclose and claim various techniques and apparatus related to stacking leaded packages.
Many other techniques have been developed that use various means for interconnecting the leads of the stacked devices. For example, U.S. Pat. No. 4,696,525 to Coller et al. teaches a socket connector for coupling adjacent devices in a stacked configuration to one another. The socket has external conductors that interconnect leads from like, adjacent devices to one another. Sockets, however, are limited in several respects. They are not versatile in their ability to implement complex interconnections. In addition, such sockets, which have relatively thick, plastic bodies, act as heat insulators between adjoining upper and lower (major) package surfaces, which can inhibit the module's overall ability to dissipate heat.
Although the art has many techniques for stacking leaded devices, a new system and method for stacking leaded package devices is a welcome development. Accordingly, the present application discloses improved systems and methods for electrically and thermally coupling adjacent integrated circuit devices in stacked modules.
SUMMARY OF THE INVENTIONThe present invention provides a system and method for electrically and thermally coupling adjacent IC packages to one another in a stacked configuration. A flex circuit having an interconnective pattern is inserted between ICs to be stacked. A part of the flex circuit emerges from between the ICs and provides a connective field that provides plural contact areas that connect to respective leads of the ICs. Thus, the flex does not require discrete leads which must be individually aligned with the individual leads of the constituent ICs employed in the stack. The principle may be employed to aggregate two or more contact areas for respective connection to leads of constituent ICs but is most profitably employed with a continuous connective field that provides contact areas for many leads of the ICs.
BRIEF DESCRIPTION OF THE DRAWINGS
Flex circuit 12 may have more than two layers but is shown with layers 14L and 16 as an efficient and simple construction that may be employed in devising modules in accordance with preferred embodiments of the present invention. As those of skill will appreciate, flex circuitry with more than two layers may readily be employed particularly where especially complex electrical connections are required. Adhesive 18 is shown on flex circuit 12 and an optional form 17 is shown within connective field 19. Adhesive 18 may also be disposed on ICs 20 and/or 22 in addition to or instead of on flex circuit 12 when constructing a module in accordance with some embodiments of the present invention. Optional form 17 is preferably an elastomer to provide a ready preformed shape for configuration of a connective field 19 and encourage compressive forces to enhance contact between contact areas 14 and leads of ICs 20 and 22.
Flex circuit 12 is shown with substantially planar portion 12A that resides between ICs in a stacked module devised in accordance with some embodiments of the present invention. An optional portion 12B of flex circuit 12 is also resident between ICs in a stacked module and typically resides beneath a part of portion 12A.
Conductive layer 14L and connect areas 14 are preferably comprised of copper although any conductive material may be employed for such purposes. A more preferred copper layer would be thin and ductile copper deposited upon substrate layer 16 that is preferably a polyimide. An etched copper or other conductive material may also be used as a conductive layer 14L but a conductive layer 14L deposited on a substrate would be preferred.
Flex circuit 12 is disposed between ICs 20 and 22 and force (represented by Fo+ and/or Fo in the Fig.) with or without heat is applied to bring together the components flex circuit 12 and ICs 20 and 22. As a result, connective field 19 is preferably compressed to have conformity with the configurations of the leads of the constituent ICs thus improving contact between contact areas 14 and respective leads. Those of skill will recognize that flex circuit 12 may be constructed in two pieces with one piece for each of connective fields 19 and such a construction, although less than preferred, should be understood to be within the scope of the present invention. Further, identified adhesive 18 may be applied to the ICs 20 and/or 22 in addition to or in place of its disposition on flex circuit 12 but that use of a thin file adhesive on flex circuit 12 is preferred for efficient construction.
When ICs 20 and 22 are brought together with flex circuit 12 between, portions of contact areas 14 exposed around parts of connective fields 19 are preferably disposed in contact with leads 24 of ICs 20 and 22 and, in preferred embodiments, contact between leads 24 and appropriate contact areas 14 is preferably realized while connective field 19 deforms in compliance with the configurations of the constituent IC leads. Solder as shown in later Figs. is then preferably employed between leads and contact areas 14. A module could be built in accordance with an embodiment in which no solder was employed and compression between leads 24 and flex circuit 12 was the sole realization of the contact between contact areas 14 and respective leads 24 but as those of skill will recognize, such a construction would not be preferred. Further, a module in accordance with an alternative embodiment could be devised in which the contact areas 14 do not touch the respective leads but await realization of electrical contact with solder or other conductive attachment. Other forms of bonding other than solder between contact areas 14 and leads 24 may also be employed (such as brazing or welding for example) but soldering techniques are well understood and adapted for use in large scale manufacturing.
Although the present invention has been described in detail, it will be apparent to those skilled in the art that many embodiments taking a variety of specific forms and reflecting changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. Therefore, the described embodiments illustrate but do not restrict the scope of the claims.
Claims
1. A stacked IC module comprising:
- first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages; and
- a flexible circuit disposed in part between the first and second leaded packages, wherein the flexible is folded back on itself to create an arcuate connective field that is compressed to have conformity with the plural leads of the first and second leaded packages.
2. The stacked IC module of claim 1, wherein the arcuate connective field is compressed to form a planar contact with the plural leads of both the first and second leaded packages.
3. The stacked IC module of claim 1, wherein the flexible circuit is bonded to itself in the portion of the flexible circuit that is folded back.
4. The attached IC module of claim 3, wherein the flexible circuit is bonded to itself with a non-conductive adhesive.
5. The stacked IC module of claim 1, in which the first and second leaded packages include flash memory circuitry.
6. The stacked IC module of claim 1, in which the connective field is disposed about a form.
7. The stacked IC module of claim 6, in which the form is comprised of elastomer.
8. A leaded package interconnection system comprising:
- a flexible circuit folded back upon itself to form an arcuate connection field, wherein the arcuate connective field, wherein the arcuate connection field is configured to deform in shape when the flexible circuit is disposed between two leaded packages.
9. The leaded package interconnection system of claim 8, wherein the flexible circuit is bonded to itself to form the arcuate connection field.
10. The leaded package interconnection system of claim 8, comprising an elastomer form disposed within the arcuate connection field.
11. The leaded package interconnection system of claim 8, wherein the arcuate connection field is configured to form a planar connection with leads emergent from the two leaded packages.
12. The leaded package interconnection system of claim 8, comprising the two leaded packages.
13. The leaded package interconnection system of claim 8, wherein the flexible circuit is folded back on itself on both ends of the flexible circuit.
14. A stacked IC module construction method comprising:
- providing a flex circuit that exhibits at least one connective field configured in an arcuate shape;
- providing first and second leaded ICs, the first and second leaded ICs each having leads emergent from at least one side; and
- disposing together, the first and second ICs with the flex circuit between to deform the connective field to be conformal with the leads of the first and second leaded ICs to realize contact between selected contact areas of the at least one connective field and selected ones of the leads of the first and second ICs.
15. The method of claim 14, comprising disposing an adhesive between at least one of the first and second ICs and the flex circuit.
16. The method of claim 14, in which the first and second ICs are each memory circuits in leaded packages.
17. The method of claim 14, in which the flex circuit exhibits two connective fields each of which includes plural contact areas and the flex circuit is comprised of at least two layers with a first of the two layers being comprised of copper and the second of the two layers being comprised of a dielectric.
18. The method of claim 17, in which the layer comprised of copper is deposited on the layer comprised of the dielectric.
Type: Application
Filed: Jul 9, 2007
Publication Date: Nov 8, 2007
Applicant: Staktek Group L.P. (Austin, TX)
Inventors: James Wehrly (Austin, TX), David Roper (Austin, TX)
Application Number: 11/774,846
International Classification: H01L 23/02 (20060101); H01L 23/52 (20060101);