THIN TRANSITION LAYER BETWEEN A GROUP III-V SUBSTRATE AND A HIGH-K GATE DIELECTRIC LAYER
Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.
In many complementary metal oxide semiconductor (CMOS) logic operations it is desirable to have high mobility material for both NMOS and PMOS transistors. With silicon (Si) substrates, low electron or hole mobility values limit speed and increase power consumption. High electron and hole mobility substrate materials, such as indium antimonide (InSb) may greatly improve logic performance.
Forming the gate dielectric of CMOS devices from certain high-k dielectric materials can reduce gate leakage. When conventional processes are used to form such transistors, a layer of an oxide of the substrate may form between the high-k dielectric and the substrate. The presence of that oxide layer may unfavorably contribute to the overall electrical thickness of the gate dielectric stack.
BRIEF DESCRIPTION OF THE DRAWINGS
In various embodiments, an apparatus and method relating to the formation of a high-k dielectric layer on a group III-V substrate with little to no oxide of the substrate between the substrate and dielectric layer are described. In the following description, various embodiments will be described. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
The group III-V substrate 102 may comprise a group III-V material. A group III-V material includes at least one element from group III of the periodic table and an element from group V. Examples of such group III-V materials include gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), aluminium antimonide (AlSb), indium antimonide (InSb), InAlSb, and InGaAs. Other III-V materials not listed may also be used. The substrate 102 may include a layer of a group III-V material and may also include additional layers or materials. For example, the substrate 102 may include an upper layer of a group III-V material, and a lower layer (not shown) of silicon, germanium, gallium arsenide, or another material. The upper layer of group III-V material may, for example, be about 120 angstroms thick, although it may have other thicknesses in alternative embodiments. Additional layers, such as a buffer layer between a group III-V material layer and a lower layer, or materials may also be included as part of the substrate 102.
The high-k dielectric layer 106 may comprise a material with a dielectric constant value greater than 10. In another embodiment, the high-k dielectric layer 106 may comprise a material with a dielectric constant value greater than that of silicon dioxide. The high-k dielectric layer 106 may include a metal cation as part of the high-k material. For example, the high-k dielectric layer 106 may comprise Al2O3, where the Al is the metal cation, and the layer 106 has a k-value of about 12. In other embodiments, the high-k gate dielectric layer 106 may have a k-value between about 15 and about 25, e.g. HfO2. In yet other embodiments, the high-k gate dielectric layer 106 may have a k-value even higher, such as 35, 80 or even higher. In various embodiments, the high-k dielectric layer 106 may comprise another material, such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, lead scandium tantalum oxide, lead zinc niobate, or another high-k dielectric material.
In some embodiments, the high-k gate dielectric layer 106 may be less than about 40 angstroms thick. In other embodiments, the high-k gate dielectric layer 106 may be between about 5 angstroms and about 20 angstroms thick.
There may be a thin transition layer 104 between the substrate 102 and high-k dielectric layer 106. There may be substantially no oxide of the substrate 102 material between the substrate 102 and high-k dielectric layer 106. In an embodiment, the thin transition layer 104 may consist essentially of a monolayer of oxygen. In an embodiment, the thin transition layer 104 may be about 5 angstroms thick or less.
In some embodiments, reoxidation of the substrate 102 surface between removal of the oxide layer 202 and formation of the capping layer 402 is prevented. This may be done by exposing the substrate 102 surface to the organometallic material while the substrate 102 surface is still covered by liquid (e.g., deionized water) from the oxide layer 202 removal process. In anther embodiment, the ambient environment around the substrate 102 is kept free of oxygen between the time the oxide layer 202 is removed and the formation of the capping layer 402.
In an embodiment, the high-k dielectric layer 106 is formed by atomic layer deposition (ALD). In another embodiment, the high-k dielectric layer 106 is formed by a physical vapor deposition, or sputtering, process in a reducing environment. In other embodiments, the high-k dielectric layer 106 is formed by other processes.
Depending on the applications, system 900 may include other components, including but are not limited to volatile and non-volatile memory 912, a graphics processor (integrated with the motherboard 904 or connected to the motherboard as a separate removable component such as an AGP or PCI-E graphics processor), a digital signal processor, a crypto processor, mass storage 914 (such as hard disk, compact disk (CD), digital versatile disk (DVD) and so forth), input and/or output devices 916, and so forth.
In various embodiments, system 900 may be a personal digital assistant (PDA), a mobile phone, a tablet computing device, a laptop computing device, a desktop computing device, a set-top box, an entertainment control unit, a digital camera, a digital video recorder, a CD player, a DVD player, or other digital device of the like.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims
1. A method for forming a semiconductor device, comprising:
- removing a surface oxide from a top surface of a substrate comprising a group III-V material;
- forming, after removing the surface oxide, a capping layer comprising an metal cation on the top surface of the substrate from which the surface oxide was removed, wherein substantially no additional oxide formed on the top surface of the substrate after the surface oxide was removed and before forming the capping layer; and
- forming, after forming the capping layer, a high-k gate dielectric layer comprising the same metal cation as the capping layer.
2. The method of claim 1, wherein forming the capping layer comprises exposing the top surface to an organometallic compound that includes the metal cation, wherein the oranometallic compound is adsorbed by the top surface to form the capping layer.
3. The method of claim 2, wherein the organometallic compound comprises the metal cation, a ligand, and a bulky leaving group.
4. The method of claim 3, wherein the high-k dielectric layer consists essentially of Al2O3, the metal cation is Al, the ligand comprises CH3, and the bulky leaving group comprises amidinate.
5. The method of claim 3, wherein forming the high-k dielectric layer comprises forming the high-k dielectric layer by atomic layer deposition, during which the bulky leaving group is displaced, leaving a thin transition layer between the high-k dielectric layer and the substrate.
6. The method of claim 5, wherein the thin transition layer consists essentially of a monolayer of oxygen.
7. The method of claim 1, further comprising:
- forming an electrode layer on the high-k dielectric layer;
- patterning the high-k dielectric and electrode layers; and
- forming spacers adjacent the patterned high-k dielectric and electrode layers.
8. A method for forming a high-k dielectric layer on a group Ill-V substrate with an abrupt transition between the high-k dielectric layer and substrate, comprising:
- removing a surface oxide from a top surface of a substrate comprising a group III-V material;
- exposing, after removing the surface oxide, the top surface of the substrate to an organometallic compound; and
- forming, after exposing the top surface to the organometallic compound, a high-k dielectric layer on the substrate with a thin transition layer and substantially no oxide of the group Ill-V material between the substrate and the high-k dielectric layer.
9. The method of claim 8, wherein the organometallic compound comprises a metal cation, a ligand, and a bulky leaving group and the high-k dielectric layer comprises the same metal cation as the organometallic compound.
10. The method of claim 9, wherein exposing the top surface of the substrate to the organometallic compound results in a capping layer including the metal cation and the bulky leaving group on the substrate, the capping layer capable of preventing oxidation of the group III-V material.
11. The method of claim 10, wherein forming the high-k dielectric layer comprises displacing the bulky leaving group.
12. The method of claim 10, wherein the top surface of the substrate is terminated by OH groups after the surface oxide is removed, and the organometallic compound reacts with the OH groups to release the H and form a bond between the metal cation of the organometallic compound and the oxygen of the OH group.
13. The method of claim 12, wherein the metal cation of the organometallic compound becomes part of the high-k dielectric layer, and the oxygen between the high-k dielectric layer and the substrate acts as the transition layer between the substrate and high-k dielectric layer.
14. The method of claim 8, wherein the high-k dielectric layer has a dielectric constant greater than 10.
15. The method of claim 8, further comprising patterning the high-k dielectric layer for use as a gate dielectric layer in a transistor.
16. A semiconductor device, comprising:
- a substrate comprising a group III-V material;
- a high-k gate dielectric layer on the substrate;
- a thin transition layer between the high-k dielectric layer and the substrate; and
- wherein there is substantially no oxide of the group III-V material in a region between the substrate and the high-k dielectric layer.
17. The device of claim 16, wherein the thin transition layer consists substantially of a monolayer of oxygen, and there is substantially no other layer between the substrate and the high-k dielectric layer.
18. The device of claim 17, further comprising:
- a gate electrode layer on the high-k gate dielectric layer;
- spacers adjacent side walls of the high-k gate dielectric layer and gate electrode layer; and
- source and drain regions adjacent the spacers.
Type: Application
Filed: May 9, 2006
Publication Date: Nov 15, 2007
Patent Grant number: 7879739
Inventors: Willy Rachmady (Beaverton, OR), James Blackwell (Portland, OR), Suman Datta (Beaverton, OR), Jack Kavalieros (Portland, OR), Mantu Hudait (Portland, OR)
Application Number: 11/382,428
International Classification: H01L 21/31 (20060101); H01L 21/469 (20060101);