Nonvolatile semiconductor memory device and manufacturing method thereof
A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.
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This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-183658, filed Jul. 3, 2006, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a NOR-type nonvolatile semiconductor memory device and a manufacturing method thereof capable of decreasing a power supply voltage without causing write characteristics to deteriorate.
2. Description of the Related Art
Recently, demands for NOR-type flash memories have been rapidly increasing along with a rapid growth in markets of memory media including digital cameras and portable audio equipment including mobile telephones. At present, in order to achieve smaller sizes, lighter weights and enhanced functions of these devices, there are increasing requests for miniaturization, higher integration, lower power supply voltages and enhanced reliability in the NOR-type flash memories.
The NOR-type flash memory has a plurality of MOS type nonvolatile semiconductor memory elements which are NOR-connected. As is well known, one element comprises a source diffusion layer and a drain diffusion layer oppositely formed on the surface of a semiconductor substrate, and a gate insulating film, a floating gate, an intergate insulating film and a control gate which are stacked on the semiconductor substrate between the source diffusion layer and the drain diffusion layer.
In contrast to a NAND-type flash memory which achieves writing by FN tunneling, the NOR-type flash memory implants hot electrons (HE) generated by use of electric field concentration at a drain edge into the floating gate to write information. At this point, because a voltage is applied to a drain electrode, there is caused a problem of deterioration of the gate insulating film located in the vicinity of the drain electrode. Thus, simple miniaturization of a gate length causes the deterioration of write characteristics.
While many reports have been made regarding problems and improvements in the size reduction of the NOR-type flash memory, a study has been conducted on the characteristics of writing achieved by secondary electrons induced in a channel, for example, in IEEE trans. Electron Devices, Vol. 50, No. 10, October 2003, pp. 2104-2111, wherein there are reported deterioration due to scaling (size reduction), the optimization of device parameters, trade-off for problems at the drain edge, etc.
However, it is known that write efficiency deteriorates as the gate length decreases, and simple miniaturization in conventional structures has already reached the limits. It has therefore been desired to achieve a NOR-type nonvolatile semiconductor memory device and a manufacturing method thereof capable of improving the write efficiency of the micro NOR-type flash memory.
BRIEF SUMMARY OF THE INVENTIONAccording to one aspect of the invention, there is provided a nonvolatile semiconductor memory device, which includes:
a semiconductor substrate of a first conductivity type;
a pair of a source diffusion region and a drain diffusion region of a second conductivity type oppositely formed on a surface of the semiconductor substrate; and
a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source diffusion region and the drain diffusion region, an edge of the stacked structure in the vicinity of the source region being formed away from a junction position between the source diffusion region and the channel region.
Before describing embodiments of the present invention, problems of a hot electron implantation NOR-type flash memory will be described.
Thus, further miniaturization causes the write characteristics to deteriorate because an electron velocity at a drain edge significantly increases.
In the present invention, the peak position of electric field concentration is displaced to a source side due to the presence of a high-resistance offset region formed by controlling an impurity distribution at a source edge, so that the implantation of the hot electrons into a drain diffusion region is suppressed, and the velocity overshoot at the edge of the drain diffusion region is also suppressed, thereby making it possible to provide a NOR-type nonvolatile semiconductor memory device with significantly improved write characteristics.
The embodiments of the present invention will hereinafter be described with reference to the drawings.
First EmbodimentAs shown in
It should be noted that in the NOR-type flash memory in general, the conductivity type of the semiconductor substrate 1 is p type, the source diffusion region 2 and the drain diffusion region 3 are n type, and carriers are electrons, but the conductivity types can be reversed and the carriers can be holes. In the following description, the carriers are electrons.
Here, the overlapping position relation among the source diffusion region 2, the drain diffusion region 3 and the floating gate 5 is defined. As schematically shown in
First, a simulation will be described which has been carried out to explain that the structure in
In the source offset structure shown in
As understood from
On the other hand, in the drain edge offset structure, the drain diffusion layer 3 is farther away from the gate edge, so that a peak of electric field concentration not only emerges at the gate edge on the drain side but also emerges at a drain electrode edge. This enlarges the electric field concentrated region where the electrons are accelerated, and therefore, the electron energy further increases. As a result, the velocity overshoot becomes more obvious. Therefore, as shown in
Furthermore,
Thus, the write characteristics can be improved by the source edge offset structure shown in
However, when a high-resistance offset region is formed at the source edge as in
Thus, in the first embodiment of the present invention, the high-resistance offset region is provided at the source edge, and the drain diffusion region profile is optimized, thereby making it possible to improve the write characteristics of the NOR-type flash memory without causing the current drive force to deteriorate.
Furthermore, as shown in
Moreover,
The manufacturing method is as follows. First, layers to be the gate (tunnel) insulating film 4, the floating gate 5, the intergate (interlayer) insulating film 6 and the control gate 7 are stacked on the substrate 1 in order (
Next, as shown in
As described above, according to the first embodiment, the provision of the high-resistance offset region at the source edge can improve the write characteristics.
Second EmbodimentIn a NOR-type nonvolatile semiconductor memory device according to a second embodiment of the present invention, a diffusion depth Ds of a source diffusion region 2 is formed to be less (shallower) than a diffusion depth Dd of a drain diffusion region 3, as shown in
Next, as shown in
Next, as shown in
As described above, the depth of the source diffusion region 2 is shallower than the depth of the drain diffusion region 3, such that the high-resistance offset region can be provided at the source edge, and write characteristics can be improved, as in the first embodiment.
Third EmbodimentA mask is added to form a desired device structure in the manufacturing method of the second embodiment. However, it is desirable to prevent the addition of the mask as much as possible from the viewpoint of a manufacturing cost reduction. In a device structure of a NOR-type nonvolatile semiconductor memory device according to a third embodiment shown in
Next, as shown in
Next, as shown in
As described above, according to the third embodiment, the depth of the source diffusion region 2 is made shallower than the depth of the drain diffusion region 3 without using the mask, and the high-resistance offset region can be provided at the source edge, so that write characteristics can be improved, as in the first embodiment.
Fourth EmbodimentIn an element structure in a fourth embodiment, a heavily-doped impurity region 8 (source halo region) of the same conductivity type as substrate impurities is provided at an edge (source edge) in the vicinity of a floating gate of a source diffusion region 2, as shown in
Next, as shown in
As described above, according to the fourth embodiment, the heavily-doped impurity region of the same conductivity type as the substrate is provided at the source edge to provide the high-resistance region at the source edge, so that write characteristics can be improved, as in the first embodiment.
Fifth EmbodimentIn an element structure of a NOR-type nonvolatile semiconductor memory device according to a fifth embodiment, a heavily-doped impurity region 8 (source halo region) of the same conductivity type as substrate impurities is also provided at an edge (source edge) in the vicinity of a floating gate of a source diffusion region 2, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
As described above, according to the fifth embodiment, since the distance between the cell transistors on the drain side is formed to be less than the distance between the cell transistors on the source side, the heavily-doped impurity region of the same conductivity type as the substrate is provided at the source edge without adding the mask, such that a high-resistance region can be provided only at the source edge. Thus, a write characteristic improving effect similar to that in the fourth embodiment can be obtained without increasing manufacturing costs.
Sixth EmbodimentIn a sixth embodiment, a lightly-doped second drain region (LDD structure) with a low impurity concentration is provided at an inner edge of a drain region 3, as shown in
Next, as shown in
As described above, according to the sixth embodiment, the LDD region is provided at the drain edge to provide the high-resistance region at the source edge, so that write characteristics can be improved, as in the first embodiment.
Seventh EmbodimentA NOR-type nonvolatile semiconductor memory device according to a seventh embodiment is characterized in that the distance between cell transistors on the side of a source 2 is formed to be less than the distance between cell transistors on the side of a drain 3, as shown in
First, layers to be a tunnel insulating film 4, a floating gate 5, an intergate insulating film 6 and a control gate 7 are stacked on a substrate 1 in order, and lithography is used to carry out stacked gate patterning, and then a sidewall insulating film 15 is formed by an oxidation process to form a structure shown in
Next, as shown in
Next, as shown in
As described above, according to the seventh embodiment, since the distance between the cell transistors on the source side is formed to be less than the distance between the cell transistors on the drain side, the LDD region can be provided only at the drain edge without adding a mask, and a high-resistance region can be provided only at the source edge. Thus, a write characteristic improving effect similar to that in the fourth embodiment can be obtained without increasing manufacturing costs.
Eighth EmbodimentThe first to seventh embodiments assume, as a conventional structure, a structure having a control gate, an intergate insulating film, a floating gate, a tunnel insulating film and a substrate. However, the first to seventh embodiments are also effective in a metal-oxide-nitride-oxide semiconductor (MONOS) structure. A nonvolatile semiconductor memory device using the MONOS structure is called an NROM.
As shown in
In the MONOS structure, electrons are captured by a trap site present in the silicon nitride film 12 to write information. In the first to seventh embodiments, effects similar to those in the first to seventh embodiments can also be obtained for the NROM in which an upper structure of the substrate has the MONOS structure.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
1. A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate of a first conductivity type;
- a pair of a source diffusion region and a drain diffusion region of a second conductivity type oppositely formed on a surface of the semiconductor substrate; and
- a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source diffusion region and the drain diffusion region, an edge of the stacked structure in the vicinity of the source region being formed away from a junction position between the source diffusion region and the channel region.
2. The device according to claim 1, wherein a diffusion depth of the source diffusion region is shallower than that of the drain region.
3. The device according to claim 1, wherein a width of the source diffusion region is formed to be less than a width of the drain diffusion region in a gate length direction of the control gate.
4. The device according to claim 3, wherein a lightly-doped impurity region of the second conductivity type, whose impurity concentration is lower than those of the source diffusion region and the drain diffusion region, is formed between the drain diffusion region and the channel region.
5. The device according to claim 1, wherein a highly-doped impurity region of the first conductivity type, whose impurity concentration is higher than that of the substrate, is formed in the channel region adjacent to the source region around an edge of the stacked structure.
6. The device according to claim 5, wherein a width of the source diffusion region is formed to be less than a width of the drain diffusion region in a gate length direction of the control gate.
7. The device according to claim 1, wherein a lightly-doped impurity region of the second conductivity type, whose impurity concentration is lower than those of the source diffusion region and the drain diffusion region, is formed between the drain diffusion region and the channel region.
8. The device according to claim 1, wherein the charge accumulation film includes polysilicon.
9. The device according to claim 1, wherein the charge accumulation film includes silicon nitride.
10. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
- forming a stacked film by stacking in order a gate insulating layer, a charge accumulation layer, a first interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;
- by selectively etching the stacked film, forming, at regular intervals in one predetermined direction, a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate;
- forming a second interlayer insulating film to cover the plurality of stacked structures;
- narrowing an exposed surface of the source planned region by processing the second interlayer insulating film such that sidewall insulating films are formed only on side surfaces of the stacked structures along the source planned region; and
- forming a source diffusion region in the source planned region and a drain diffusion region in the drain planned region, by ion-implanting impurities of a second conductivity type perpendicularly to an upper surface of the semiconductor substrate with the stacked structures and the sidewall insulating films used as masks.
11. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
- forming a stacked layer by stacking in order a gate insulating layer, a charge accumulation layer, a first interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;
- by selectively etching the stacked layer, arranging in a predetermined direction a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate; and
- forming a source diffusion region and a drain diffusion region, which are of a second conductivity type, along the predetermined direction on the surface of the semiconductor substrate by ion implantation of impurities of the second conductivity type using the stacked structures as masks, such that a depth of the source diffusion region is shallower than that of the drain diffusion region.
12. The method according to claim 11, wherein
- said forming a source diffusion region and a drain diffusion region includes:
- forming a second interlayer insulating film to bury the plurality of stacked structures;
- removing the second interlayer insulating film on the drain planned region;
- leaving the second insulating film on the source planned region at a desired height; and
- forming the depth of the source diffusion region shallower than that of the drain diffusion region, by ion-implanting impurities of the second conductivity type perpendicularly to an upper surface of the semiconductor substrate, while interposing the second interlayer insulating film left only on the source planned region.
13. The method according to claim 11, wherein
- said arranging a plurality of stacked structures in a predetermined direction includes:
- arranging the stacked structures such that the source planned region having a small space and the drain planned region having a large space are alternately arranged in the predetermined direction, and
- said forming the source diffusion region and the drain diffusion region includes:
- forming the second interlayer insulating film so as to cover the plurality of stacked structures, to bury the source planned region and to line the drain planned region and inner surfaces of the stacked structures adjacent thereto;
- providing an opening in the second interlayer insulating film on the drain planned region; and
- forming the depth of the source diffusion region shallower than that of the drain diffusion region, by ion-implanting impurities of the second conductivity type perpendicularly to an upper surface of the semiconductor substrate, while interposing the second interlayer insulating film deposited on the source planned region.
14. The method according to claim 11, wherein
- said arranging a plurality of stacked structures in a predetermined direction includes:
- arranging the stacked structures such that the source planned region having a small space and the drain planned region having a large space are alternately arranged in the predetermined direction, and
- said forming the source diffusion region and the drain diffusion region includes:
- forming the second interlayer insulating film so as to cover the plurality of stacked structures, to bury the source planned region and to line the drain planned region and inner surfaces of the stacked structures adjacent thereto;
- providing an opening in the second interlayer insulating film in the drain planned region;
- ion-implanting impurities of the second conductivity type in a low concentration and obliquely with respect to an upper surface of the semiconductor substrate from two directions including a direction running from the drain planned region to the source planned region and a direction opposite thereto, such that a lightly-doped impurity region is formed only in the vicinity of the boundary between the stacked structures and the drain planned region; and
- forming the source diffusion region in the source planned region, while forming the drain diffusion region in the drain planned region so as to adjoin the lightly-doped impurity region, by ion-implanting the impurities of the second conductivity type perpendicularly to the upper surface of the semiconductor substrate.
15. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
- forming a stacked layer by stacking in order a gate insulating layer, a charge accumulation layer, a first interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;
- by selectively etching the stacked layer, arranging in one predetermined direction a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate;
- forming a highly-doped impurity region of the first conductivity type having a concentration higher than that of the semiconductor substrate only in the vicinity of a boundary between the stacked structures and the source planned region, by implanting impurity ions of the first conductivity type in a high concentration and obliquely with respect to an upper surface of the semiconductor substrate in a direction running from the source planned region to the drain planned region; and
- forming the source diffusion region in the source planned region so as to adjoin the highly-doped impurity region, while forming the drain diffusion region in the drain planned region, by ion-implanting impurities of the second conductivity type perpendicularly to the upper surface of the semiconductor substrate.
16. The method according to claim 15, wherein
- said forming highly-doped impurity region of the first conductivity type includes:
- forming an ion implantation blocking mask on the drain planned region; and
- implanting impurity ions of the second conductivity type obliquely with respect to the upper surface of the semiconductor substrate from two directions including a direction running from the source planned region to the drain planned region and a direction opposite thereto.
17. The method according to claim 15, wherein
- said forming the highly-doped impurity region of the first conductivity type includes:
- forming a second interlayer insulating film to cover the plurality of stacked structures, so as to bury the drain planned region having a small space and to line the source planned region having a large space and sidewalls of the stacked structures adjacent thereto;
- providing an opening in the second interlayer insulating film on the source planned region; and
- implanting impurity ions of the second conductivity type obliquely with respect to an upper surface of the semiconductor substrate from two directions including a direction running from the source planned region to the drain planned region and a direction opposite thereto.
18. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
- forming a stacked layer by stacking in order a gate insulating layer, a charge accumulation layer, an interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;
- by selectively etching the stacked layer, arranging in one predetermined direction a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate;
- forming a lightly-doped impurity region of a second conductivity type only in the vicinity of a boundary between the stacked structures and the drain planned region, by implanting impurity ions of the second conductivity type obliquely with respect to an upper surface of the semiconductor substrate; and
- forming the source diffusion region in the source planned region and the drain diffusion region in the drain planned region so as to adjoin the lightly-doped impurity region, by ion-implanting impurities of the second conductivity type perpendicularly to the upper surface of the semiconductor substrate.
19. The method according to claim 18, wherein
- said forming the lightly-doped impurity region includes:
- forming an ion implantation blocking mask only on the source planned region;
- forming the lightly-doped impurity region by ion-implanting impurities of the second conductivity type in a low concentration obliquely with respect to the upper surface of the semiconductor substrate from two directions including a direction running from the source planned region to the drain planned region and a direction opposite thereto after said forming an ion implantation blocking mask; and
- forming the source diffusion region and the drain diffusion region such that the drain diffusion region adjoins the lightly-doped impurity region, by ion-implanting impurities of the second conductivity type having a concentration higher than the low concentration perpendicularly to the upper surface of the semiconductor substrate after removal of the ion implantation blocking mask.
20. The method according to claim 18, wherein
- said forming a lightly-doped impurity region includes:
- forming the second interlayer insulating film so as to cover the plurality of stacked structures, bury the source planned region having a small space, and line the drain planned region having a large space and inner surfaces of the stacked structures adjacent thereto;
- forming a lightly-doped impurity region only in the vicinity of the boundary between the drain planned region and the stacked structures, by ion-implanting impurities of the second conductivity type in a low concentration obliquely with respect to the upper surface of the semiconductor substrate from two directions including a direction running from the drain planned region to the source planned region and a direction opposite thereto; and
- forming the source diffusion region and the drain diffusion region such that the drain region adjoins the lightly-doped impurity region, by ion-implanting impurities of the second conductivity type having a concentration higher than the low concentration perpendicularly to the upper surface of the semiconductor substrate.
Type: Application
Filed: Dec 22, 2006
Publication Date: Jan 3, 2008
Applicant:
Inventor: Takamitsu Ishihara (Yokohama-shi)
Application Number: 11/643,904
International Classification: H01L 29/76 (20060101);