Semiconductor device and method of manufacturing the same
A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-171593 filed on Jun. 21, 2006 in Japan, the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTIONThe present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a MIS field effect transistor the source and drain portions of which are improved and a method of manufacturing the same.
BACKGROUND OF THE INVENTIONTo advance the performance of a semiconductor integrated circuit, the performance of a field effect transistor serving as a constituent device must be advanced. For advancing the device performance, scaling down of the device is effective. For this reason, device performance has been improved by scaling down the device by micro patterning. However, as micro patterning advanced, a technical barrier to be solved becomes high at the same time. According to the international semiconductor roadmap, especially in relation to a technique for forming source and drain portions, a solution for realizing a junction having a depth of 10 to 20 nm in a drain-extension portion in the 65-nm generation or later cannot be found in the existing circumstances.
In this background, in order to improve both suppression of short channel effect and reduction of junction leakage, a device using Schottky source and drain to which an impurity segregation technique is applied is proposed (JP-A 2005-101588 (KOKAI)). In particular, in the 45-nm generation or later, a channel resistance caused by scattering of carriers is not a prevailing factor that degrades a drain current because of a small gate length. For this reason, improvement of device performance relying only to micro patterning is very difficult. Therefore, in order to realize further improvement of performance, a device using a Schottky source-drain maximally utilizing the characteristic feature of a Schottky junction which can inject high-speed carriers into a channel is desired (K. Ucida et al., Appl. Phys. Lett., 76, 3992 (2000)). However, a device structure using a conventional Schottky source-drain has the following problem. That is, the merit of the Schottky source-drain which can inject high-speed carriers into a channel is not always maximally utilized.
Thus, the device using a conventional Schottky source-drain has a merit for short channel effect and suppression of junction leakage. However, the merit of the Schottky source-drain which can inject high-speed carriers into a channel is not always maximally utilized. More specifically, in order to improve the device performance by using an increase in rate of injection by the Schottky source-drain, a device structure must be optimized. However, up to now, it cannot be said that the device structure is optimized.
SUMMARY OF THE INVENTIONThe present invention has been made in consideration of the above circumstances. It is an object of the present invention to provide a semiconductor device having a field effect transistor with a device structure which can achieve improvement of performance by increasing an injection rate of carriers while effectively suppressing a short channel effect and junction leakage, and a method of manufacturing the semiconductor device.
A semiconductor device according to an embodiment of the present invention comprises a field effect transistor including: a first semiconductor region of a first conductivity type having a surface portion on which a channel region is formed; a gate electrode formed on the channel region, a gate insulating film in between the gate electrode and the channel region; a source electrode and a drain electrode formed on both the sides of the channel region; second semiconductor regions of a second conductivity type formed between the source electrode and the channel region and between the drain electrode and the channel region to serve as extension regions of a source and a drain; third semiconductor regions of the second conductivity type formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions and having an impurity concentration higher than that of the second semiconductor region; and side wall insulating films formed on both the side surfaces of the gate electrode, the side wall insulating films being separated from the source electrode and the drain electrode.
A method for producing the field effect transistor according to another embodiment of the present invention comprises: forming a gate electrode on a first semiconductor region of a first conductivity type, a gate insulating film in between, and side wall insulating films on both side surfaces of the gate electrode; ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain; forming second side wall insulating films on both side surfaces of the side wall insulating film; and siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
A method for producing the field effect transistor according to still another embodiment of the present invention comprises: forming a gate electrode on a first semiconductor region of a first conductivity type, a gate insulating film in between; forming side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode; ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain; and siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
A method for producing the field effect transistor according to still another embodiment of the present invention comprises: forming a gate electrode on a part of a first semiconductor region of a first conductivity type, a gate insulating film in between; depositing an insulating film serving as a side wall insulating film of the gate electrode; maximally etching the insulating film serving as the side wall insulating film by anisotropic etching not to expose an underlying layer; ion-implanting an impurity in the first semiconductor region from above the insulating film serving as the side wall insulating film to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain; etching the insulating film serving as the side wall insulating film which is maximally etched not to expose the underlying layer to form side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode, siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode; and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
According to the present invention, there can be provided a semiconductor device having a field effect transistor with a device structure which can achieve improvement of performance by increasing an injection rate of carriers while effectively suppressing a short channel effect and junction leakage, and a method of manufacturing the semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 7 to 13 are cross-sectional views showing a first manufacturing step for the MIS field effect transistor according to the first embodiment;
FIGS. 15 to 20 are cross-sectional views showing the second manufacturing step for the MIS field effect transistor according to the first embodiment;
FIGS. 21 to 23 are cross-sectional views showing a third manufacturing step for the MIS field effect transistor according to the first embodiment;
FIGS. 26 to 34 are cross-sectional views showing an device structure of a MIS field effect transistor according to a fourth embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTSEmbodiments of the present invention will be described below with reference to the drawings.
First Embodiment
A polysilicon gate electrode 102 is formed on a p-type silicon substrate (first semiconductor region) 100 a gate insulating film 101 in between. A gate silicide 103 is formed on the polysilicon gate electrode 102. In this case, the gate electrode 102 is made of polysilicon. However, a metal gate structure in which the polysilicon gate electrode 102 and the gate silicide 103 are replaced by a single metal layer may be employed.
On both the side surfaces of the gate electrodes 102 and 103, a gate side wall insulating film 104 constituted by a silicon nitride film is formed. Source and drain regions are formed in the silicon substrate 100 to interpose a channel region under the polysilicon gate electrode 102. The source and drain regions are constituted by, an n-type extension diffusion layer (second semiconductor region) 105 using, for example, As as an impurity, source and drain suicides (source electrode and drain electrode) 107 made of, for example, nickel silicide (NiSi), and an n+-type high-concentration impurity layer (third semiconductor region) 106 using, for example, As as an impurity. The n+-type high-concentration impurity layer 106 is formed between the source and drain electrodes 107 and the silicon substrate 100 and the n-type extension diffusion layer 105. The n+-type high-concentration impurity layer 106 has an impurity concentration higher than that of the n-type extension diffusion layer 105. The impurity of the n+-type high-concentration impurity layer 106 is formed by segregating the impurity of the n-type extension diffusion layer 105 in manufacturing of the source and drain electrodes 107.
A characteristic feature of the embodiment is to have a structure in which, as shown in
As described above, when the structure in which the interface of the source and drain suicides 107 is separated from the gate side wall insulating film 104 is employed, a conspicuous operation and effect that suppress a decrease in injection rate of carriers from the source are obtained.
The operation and effect of the embodiment will be described below with reference to the band diagram in
In the embodiment, as shown in
The operation and effect of the embodiment are especially effective when the material constituting the gate side wall insulating film has a dielectric constant higher than that of the upper layer film of the gate side wall insulating film, for example, when the gate side wall insulating film and the upper layer film are a silicon nitride film and a silicon oxide film, respectively. This is because convergence of an electric line of force on the interface of the gate electric field which goes around the gate electrode from the gate electrode side surface becomes conspicuous. However, when the dielectric constants are equal to each other, for example, even though both the gate side wall insulating film and the upper layer film are silicon nitride films, the electric line of force of the gate electric field is terminated due to the influence of an interface level existing on the interface. For this reason, the operation and effect as those described above are obtained as well.
A simulation result of characteristics of the field effect transistor according to the embodiment will be described below with reference to the drawings. In the simulation, as reference values of respective parameters, a gate length (L)=30 nm, an equivalent oxide thickness (EOT) of a gate insulating film=1.2 nm, a side wall thickness of the gate side wall insulating film=8 nm, and a separation distance (L1) between the gate side wall insulating film and the source-drain silicide interface=10 nm are set. Parameters to which conditions are not assigned are calculated to be fixed to the reference values. The side wall thickness and the separation distance (L1) are calculated such that the side wall thickness and the separation distance are symmetrically changed with respect to a gate in both the side directions. With respect to an increasing rata of a drain current, a field effect transistor using a diffusion layer as a source-drain having an equivalent standby current characteristic is used as an object to be compared.
According to the above result, the separation distance L1 is desirably larger than 0 and 30 nm or less. This is because in the region a drain current becomes larger than that of a conventional field effect transistor in which a source-drain silicide interface and a side wall insulating film overlap. Furthermore, the separation distance L1 is desirably 4 nm or more and 20 nm or less. This is because a drain current has a maximal value in this region.
According to the above result, the gate length (L) is desirably 80 nm or less which is equal to or more than that of a conventional field effect transistor. Furthermore, the gate length (L) is desirably less than 30 nm where an increasing rate of the drain current is 10% or more (1.1 times the drain current).
According to the above result, the gate insulating film EOT is desirably set at 4 nm or more which is equal to or larger than the characteristic of the conventional field effect transistor such that an increasing rate of the drain current is 0% or more. Furthermore, the gate insulating EOT is desirably 1.3 nm or less at which the drain current further increases.
According to the above result, the side wall thickness is desirably 10 nm or less at which deterioration of a drain current characteristic is not conspicuous, and is more desirably 8 nm or less at which the deterioration of the drain current characteristic is not observed.
In the field effect transistor according to the embodiment, an impurity concentration of the n+-type high-concentration impurity layer 106 in interfaces between the impurity layer and the source and the drain electrode is desirably 8×1019 to 5×1020 atoms/cm3, and an impurity concentration at a depth of 20 nm from the interfaces between the impurity layer and the source and drain electrode is desirably 1/10 or less the impurity concentration in the interfaces between the impurity layer and the source and drain electrode. More specifically, a depth of a point at which an impurity concentration decreases to 1/10 from the interface is desirably 20 nm or less. This is because, when the concentration in the interface is equal to or less than the above value, the current decreases due to an insufficient decrease of a Schottky barrier. When the depth of the point at which the impurity concentration decreases to 1/10 from the interface is the above depth or more, an injection rate is decreased by the resistance of an impurity layer in traveling of carriers from the source to the drain.
The n-type extension diffusion layer 105 desirably has a maximum impurity concentration in a gate insulating film interface, the maximum impurity concentration is desirably ½ or less the impurity concentration of the n+-type high-concentration impurity layer 106 in the interfaces between the impurity layer 106 and the source and the drain electrode, and an impurity concentration at a depth of 30 nm from the gate insulating film interface is desirably 1/10 or less the concentration in the gate insulating film interface. More specifically, the depth of the point at which the impurity concentration decreases to 1/10 from the interface is desirably 30 nm or less. This is because, when the concentration and the depth are equal to or larger than the given concentration and the given depth, respectively, an off current increases due to the influence of a short channel effect.
A first manufacturing method for the field effect transistor according to the embodiment will be described below with reference to FIGS. 7 to 12.
As shown in
As shown in
As shown in
As shown in
After the surface of the silicon substrate 100 is cleaned with a diluted hydrofluoric acid or the like, Ni is sputtered in a thickness of 7 to 11 nm (more desirably, 9 nm or less) and heat-treated at 350° C. for 30 seconds, as shown in
At the same time, an As impurity in the n-type extension layer 105 is segregated by siliciding. The n+-type high-concentration impurity layer 106 having a concentration higher than that of the n-type extension layer 105 is formed in the interface between the source-drain silicide 107 and the n-type extension layer 105.
Thereafter, as shown in
According to the first manufacturing method described above, the deposited film thickness of the TEOS oxide film forming the second side wall insulating film 112 is changed, so that the separation distance (L1) of the interface between the gate side wall insulating film 104 and the source-drain silicide 107 can be set to a desired value.
In the first manufacturing method, control of an amount of substrate etching is important when the TEOS oxide film is etched back by the RIE method to form the second side wall insulating film 112. As shown in
According to the above result, etching conditions and etching time are desirably controlled such that the amount of substrate etching is set to 8 nm or less which obtain a drain current having an increasing rate of 0% or more, i.e., equal to or larger than that of conventional field effect transistor characteristics, more preferably, 6 nm or less at which the drain current further increases.
As shown in
A second manufacturing method for the field effect transistor according to the embodiment will be described below with reference to FIGS. 15 to 20.
As shown in
As shown in
As shown in
As shown in
Thereafter, as shown in
According to the second manufacturing method described above, the step of forming a second sidewall insulating film is unnecessary. For this reason, the manufacturing steps of the second manufacturing method can be simplified in comparison with the first manufacturing method.
As shown in
Therefore, as in the first manufacturing method, etching conditions and etching time are desirably controlled such that the amount of substrate etching is set to 8 nm or less at which a drain current has an increasing rate of 0% or more, and more preferably, 6 nm or less at which the drain current further increases. However, unlike in the first manufacturing method, the n-type extension layer 105 is formed after the etch-back process in the RIE in the second manufacturing method. For this reason, a problem of removal of the n-type extension layer 105 is not occurred.
In this case, in order to avoid the silicon substrate 100 from being etched, the following third manufacturing method can also be used. More specifically, as in the first and second manufacturing methods, the gate insulating film 101 and the gate electrode 102 are formed by patterning. Thereafter, as shown in
As shown in
As shown in
The subsequent steps are the same as those in the second manufacturing method. As described above, in removal of the silicon nitride film, the amount of etching of the substrate 100 can be minimized by using wet etching which can have selectivity to the silicon substrate 100 higher than that in the RIE method.
The field effect transistor according to the embodiment described above has a self-aligned silicide structure. An interface between the silicide of the source-drain portion and the silicon substrate is separated from the gate side wall insulating film. The interface is covered with an impurity layer having a steep impurity concentration profile at a desired concentration or more. Therefore, improvement of performance by increasing an injection rate of carriers and improvement of element reliability can be achieved while suppressing punch through and leakage current.
Second Embodiment
The HALO diffusion layer 201 is a p-type region the impurity type of which is the same as that of a silicon substrate 100, and has an impurity concentration higher than that of the silicon substrate 100 as a characteristic feature. The field effect transistor according to the embodiment includes the HALO diffusion layer 201 to obtain the operation and effect of the first embodiment and to achieve improvement of a roll-off characteristic.
Third Embodiment
The n+-type deep diffusion layer 301 is formed between an n+-type high-concentration impurity layer 106 and the silicon substrate 100, and has a thickness of, for example, about 50 nm.
The field effect transistor according to the embodiment includes the n+-type deep diffusion layer 301 to obtain the operation and effect of the first embodiment and to achieve a considerable reduction in junction leakage from the source-drain bottom portion.
Due to the presence of the n+-type high-concentration impurity layer 106, the n+-type deep diffusion layer 301 can be made shallower or can have a concentration lower than a deep diffusion layer applied to a MOSFET using a normal diffusion layer as a source-drain region. Therefore, it is also a characteristic feature of the embodiment that a punch through current can be suppressed.
Fourth Embodiment
In this manner, both the HALO diffusion layer 201 and the n+-type deep diffusion layer 301 are formed to make it possible to simultaneously realize improvement of the roll-off characteristic and a considerable reduction in junction leakage as described above.
A method of manufacturing a field effect transistor according to the embodiment will be described below with reference to FIGS. 27 to 34.
As shown in
As shown in
As shown in
The dummy gate side wall insulating films 121 are removed by wet etching or the like. Subsequently, as shown in
As shown in
As shown in
After the substrate surface is cleaned with a diluted hydrofluoric acid or the like, Ni is sputtered in a thickness of 7 to 11 nm (more desirably, 9 nm or less), as shown in
Thereafter, as shown in
The present invention is not limited to the above embodiments. In the embodiments, an n-channel MIS field effect transistor is described. However, the present invention can be also applied to a p-channel MIS field effect transistor. In the embodiments, the description is made by using As as impurities in the second and third semiconductor regions, but the impurity is not limited to As. When an n-type semiconductor region is formed, an impurity can also be selected from elements such as P serving as a donor. When a p-type semiconductor region is formed, the impurity can be selected from elements such as B serving as an acceptor. Although silicon is used as a semiconductor substrate material, the semiconductor substrate material is not limited to silicon. Silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), aluminum nitride (AlN), or the like can be used.
The orientation of the substrate material is not limited to a (100) orientation plane. A (110) orientation plane, a (111) orientation plane or the like can be properly selected. The present invention can also be applied to any MIS field effect transistor, including a three-dimensional structure such as an Fin structure or a double-gate structure. Furthermore, various modifications of the present invention can be effected without departing from the spirit and scope of the invention.
Claims
1. A semiconductor device comprising a field effect transistor including:
- a first semiconductor region of a first conductivity type having a surface portion on which a channel region is formed;
- a gate electrode formed on the channel region;
- a gate insulating film in between the gate electrode and the channel region;
- a source electrode and a drain electrode formed on both the sides of the channel region;
- second semiconductor regions of a second conductivity type formed between the source electrode and the channel region and between the drain electrode and the channel region;
- third semiconductor regions of the second conductivity type formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions and having an impurity concentration higher than that of the second semiconductor region; and
- sidewall insulating films formed on both the side surfaces of the gate electrode,
- the side wall insulating films being separated from the source electrode and the drain electrode.
2. The semiconductor device according to claim 1, wherein a distance of separation between the side wall insulating film and the source electrode and between the side wall insulating film and the drain electrode is longer than 0 and not more than 30 nm.
3. The semiconductor device according to claim 1, wherein an impurity concentration in interfaces between the third semiconductor region and the source and drain electrode is not less than 8×1019 and not more than 5×1020 atoms/cm3,
- an impurity concentration in the third semiconductor region at a depth of 20 nm from the interfaces between the third semiconductor region and the source and drain electrode is not more than 1/10 an impurity concentration in the interfaces between the third semiconductor region and the source and drain electrode,
- the second semiconductor region has a maximum impurity concentration in a gate insulating film interface, and the maximum impurity concentration is not more than ½ the impurity concentration in the interfaces between the third semiconductor region and the source and drain electrode, and
- an impurity concentration of the second semiconductor region at a depth of 30 nm from the gate insulating film interface is not more than 1/10 the impurity concentration in the gate insulating film interface in the second semiconductor region.
4. The semiconductor device according to claim 1, wherein a gate length of the gate electrode is not more than 80 nm,
- an equivalent physical oxide thickness (EOT) of the gate insulating film is not more than 4 nm, and
- a film thickness of the side wall insulating film is not more than 10 nm.
5. The semiconductor device according to claim 1, wherein a fourth semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region is formed between the second semiconductor region and the first semiconductor region.
6. The semiconductor device according to claim 1, wherein a fifth semiconductor region of the second conductivity type is formed between a bottom of the third semiconductor region and the first semiconductor region.
7. The semiconductor device according to claim 1, wherein the side wall insulating film is a silicon nitride film, and an upper-layer film of the side wall insulating film is a silicon oxide film.
8. The semiconductor device according to claim 1, wherein the first to third semiconductor regions are made of silicon.
9. The semiconductor device according to claim 1, wherein the field effect transistor is an n-channel MIS field effect transistor, and impurities in the second and third semiconductor regions are As.
10. The semiconductor device according to claim 1, wherein the source electrode and the drain electrode are made of nickel silicide (NiSi).
11. A method of manufacturing a semiconductor device, comprising:
- forming a gate insulating film on a first semiconductor region of a first conductivity type;
- forming a gate electrode on the gate insulating film;
- forming side wall insulating films on both side surfaces of the gate electrode;
- ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type;
- forming second side wall insulating films on both side surfaces of the side wall insulating film; and
- siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
12. The method according to claim 11, wherein in forming the side wall insulating film, an amount of substrate etching is not more than 8 nm.
13. The method according to claim 11, wherein the first to third semiconductor regions are made of silicon.
14. The method according to claim 11, wherein the impurity is As, and the silicide is nickel silicide (NiSi).
15. A method of manufacturing a semiconductor device, comprising:
- forming a gate insulating film on a first semiconductor region of a first conductivity type;
- forming a gate electrode on the gate insulating film;
- forming side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode;
- ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type; and
- siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
16. The method according to claim 15, wherein in forming the side wall insulating film, an amount of substrate etching is not more than 8 nm.
17. The method according to claim 15, wherein the first to third semiconductor regions are made of silicon.
18. The method according to claim 15, wherein the impurity is As, and the silicide is nickel silicide (NiSi).
19. A method of manufacturing a semiconductor device, comprising:
- forming a gate electrode on a part of a first semiconductor region of a first conductivity type, a gate insulating film in between the gate electrode and the first semiconductor region;
- depositing an insulating film serving as a side wall insulating film of the gate electrode;
- etching the insulating film serving as the side wall insulating film by anisotropic etching not to expose an underlying layer;
- ion-implanting an impurity in the first semiconductor region from above the insulating film serving as the side wall insulating film to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain;
- etching the insulating film serving as the side wall insulating film which is etched not to expose the underlying layer to form side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode; and
- siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
20. The method according to claim 19, wherein the first to third semiconductor regions are made of silicon, the impurity is As, and the silicide is nickel silicide (NiSi).
Type: Application
Filed: Jun 20, 2007
Publication Date: Jan 3, 2008
Inventors: Atsuhiro Kinoshita (Kanagawa), Junji Koga (Kanagawa)
Application Number: 11/812,609
International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101);