Method of manufacturing semiconductor device
Provided are a semiconductor device capable of mounting a plurality of semiconductor chips in compact on a leadframe and reducing manufacturing costs, and a method of manufacturing the same. The semiconductor device includes: a semiconductor chip (20) having a top surface (20a) provided with a plurality of electrode pads (22) on a periphery thereof, and an under surface (20b) which is opposite to the top surface, the semiconductor chip (20) being mounted with a side of the top surface (20a) being opposed to an under surface (3b) of the island portion (3); a semiconductor chip (10) having a top surface (10a) provided with a plurality of electrode pads (12) on a periphery thereof, and an under surface (10b) which is opposite side to the top surface, the semiconductor chip (10) being mounted with a side of the under surface (10b) being opposed to a top surface (3a) of the island portion (3); a plurality of wires (30) each connecting an associated one of leads (5) and an associated one of electrode pads (12, 22) by reverse bonding, with a point on each lead (5) being a starting point, and with each electrode pad (12, 22) of one of the corresponding semiconductor chips (10, 20) being an ending point; and an encapsulation resin (40), in which the wires (30) are connected such that each side surface of the wires (30) contacts each electrode pad substantially in parallel with each top surface (10a, 20a) of the semiconductor chips (10, 20).
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1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a plurality of semiconductor chips laminated on a leadframe, and a method of manufacturing the same.
2. Description of the Related Art
As an example of a conventional semiconductor device, there is a semiconductor device as disclosed in JP 05-152503 A.
As a conventional semiconductor device having a plurality of semiconductor chips mounted thereon, there is a semiconductor device as shown in
Further, a semiconductor device disclosed in JP 11-097476 A (JP 2954109 B) is filed by the applicant of this application. According to the semiconductor device, in a ball-grid-array (BGA) type chip size package (CSP) semiconductor device having a chip-on-lead (COL) structure, leads and pads are connected to each other through wires by reverse bonding, with a point on each lead in the vicinity of the chip being a starting point and with each electrode pad on the chip being an ending point. As a result, it is possible to reduce a lead length and a package size.
However, the prior arts disclosed in the above-mentioned cited references have a room for improvement in the following points.
First, when each electrode of the chips is normally bonded to the leads, the wires extending from the electrodes of the semiconductor chips each rise substantially vertically with respect to each surface of the chips, and each form a loop shape. As a result, in any case of
Second, in a case where a plurality of chips are laminated, as shown in
Third, in a case of
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device capable of mounting a plurality of semiconductor chips in compact on a leadframe and reducing manufacturing costs, and a method of manufacturing the same.
According to the present invention, there is provided a semiconductor device including: a leadframe including an island portion and a plurality of leads; a first semiconductor chip having a top surface provided with a plurality of electrode pads on a periphery thereof, and an under surface opposite to the top surface, the first semiconductor chip being mounted onto the under surface of the island portion of the leadframe so that the top surface of the first semiconductor chip opposes the under surface of the island portion of the leadframe; a second semiconductor chip having a top surface provided with a plurality of electrode pads on a periphery thereof, and an under surface opposite to the top surface, the second semiconductor chip being mounted onto the top surface of the island portion of the leadframe so that the under surface of the second semiconductor chip opposes the top surface of the island portion of the leadframe; a plurality of wires each connecting an associated one of the leads and an associated one of the electrode pads by reverse bonding, with a point on each lead of the plurality of leads of the leadframe being a starting point, and with each electrode pad of one of the corresponding first semiconductor chip and second semiconductor chip being an ending point; and an encapsulation resin for encapsulating the first semiconductor chip and the second semiconductor chip, in which the plurality of wires are connected so that each side surface of the plurality of wires contacts one of the electrode pads substantially in parallel with the each top surface of the first semiconductor chip and the second semiconductor chip.
According to the present invention, it is possible to mount a plurality of semiconductor chips in compact on a leadframe and reduce manufacturing costs.
According to the present invention, there is provided a method of manufacturing a semiconductor device, including the steps of: preparing a leadframe including an island portion and a plurality of leads; mounting a first semiconductor chip having a top surface provided with a plurality of electrode pads on a periphery thereof, and an under surface provided on an opposite side of the top surface, with a side of the top surface being opposed to an under surface of the island portion of the leadframe; mounting a second semiconductor chip having a top surface provided with a plurality of electrode pads on a periphery thereof, and an under surface provided on an opposite side of the top surface, with a side of the under surface being opposed to a top surface of the island portion of the leadframe; connecting wires to each an associated one of the leads and an associated one of the electrode pads by reverse bonding, with a point on each lead of the plurality of leads of the leadframe being a starting point, and with each electrode pad of one of the corresponding first semiconductor chip and second semiconductor chip being an ending point; and encapsulating the first semiconductor chip and the second semiconductor chip with an encapsulation resin, in which the wires are connected such that each side surface of the wires contacts one of the electrode pads substantially in parallel with each top surface of the first semiconductor chip and the second semiconductor chip.
According to the present invention, it is possible to mount a plurality of semiconductor chips in compact on a leadframe, and reduce manufacturing costs.
According to the present invention, it is possible to provide a semiconductor device capable of mounting a plurality of semiconductor chips in compact on a leadframe and reducing manufacturing costs, and a method of manufacturing the same.
In the accompanying drawings:
Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that in each figure, the same components are denoted by the same reference numerals and appropriate explanations thereof will be omitted. In addition, in each figure described below, structures of portions that are not related to essential parts of the present invention are omitted.
The under surface 3b of the island portion 3 has a size smaller than the dimension of the first semiconductor chip 20 excluding the electrode pads 22 thereof, the first semiconductor chip 20 being mounted under the island portion 3. The island portion 3 of the leadframe 1 may have a thickness of about less than 80 μm to 25 μm. In this embodiment, the thickness of the island portion 3 is set to 75 μm. In addition, in this embodiment, the first semiconductor chip 20 and the second semiconductor chip 10 have the same shape.
Next, a method of manufacturing the semiconductor device 100 according to this embodiment will be described with reference to
The method of manufacturing the semiconductor device 100 according to this embodiment includes the steps of: preparing the leadframe 1 having the island portion 3 and the plurality of leads 5 (
Specifically, as shown in
Next, as shown in
Next, as shown in
The wires 30 thus formed through reverse bonding are connected such that each side surface of the wires 30 contacts each electrode pad substantially in parallel with the top surface 20a of the first semiconductor chip 20. A loop height d1 of the wire 30 thus formed is reduced as shown in
In this embodiment, the loop height d1 of the wire 30 extending from the electrode pad 22 of the first semiconductor chip 20 is about less than 50 μm to 25 μm. In
Next, as shown in
As shown in
Next, as shown in
The loop height of the wire 30 thus formed by reverse bonding can be reduced as compared with the case of employing the conventional normal bonding, in the same manner as the loop height d1 of the first semiconductor chip 20.
Next, as shown in
As described above, according to the semiconductor device 100 of the embodiment of the present invention, and according to the method of manufacturing the same, by employment of reverse bonding, the height of the semiconductor device 100 can be reduced, thereby making it possible to mounting the plurality of semiconductor chips in compact on the leadframe. In addition, by eliminating the necessity of the spacer, the material costs for the spacer and the process for providing the spacer can be omitted, thereby reducing the manufacturing costs.
Further, in a conventional semiconductor device having a laminated structure, the semiconductor chip disposed above is formed with a shape smaller than that of the semiconductor chip disposed below so that the electrode pads of the lower semiconductor chip do not overlap the upper semiconductor chip. However, in the semiconductor device 100 according to this embodiment, it is unnecessary to form the upper semiconductor chip to be smaller than the lower semiconductor chip, and the second semiconductor chip 10 can be formed with the same shape as the first semiconductor chip 20. Further, irrespective of mounting the second semiconductor chip 10 and the first semiconductor chip 20 on both surfaces of the island portion 3 of the leadframe 1, it is possible to set directions in which the wires 30 are connected to the semiconductor chips to be the same directions. Accordingly, in the process for manufacturing the semiconductor device 100, it is unnecessary to place the second semiconductor chip 10 upside down to be bonded after the first semiconductor chip 20 is bonded to the leadframe 1, which simplifies the manufacturing process.
As described above, the embodiments of the present invention has been described with reference to the drawings. However, the embodiments are merely illustrative of the present invention, and various structures other than the above-mentioned structures can also be employed.
Claims
1. A method of manufacturing a semiconductor device, comprising:
- mounting a first semiconductor chip having a top surface provided with a plurality of electrode pads on a periphery thereof, and an under surface provided on an opposite side of the top surface, with a side of the top surface being opposed to an under surface of a substance;
- mounting a second semiconductor chip having a top surface provided with a plurality of electrode pads on a periphery thereof, and an under surface provided on an opposite side of the top surface, with a side of the under surface being opposed to a top surface of the substance; and
- connecting wires to each an associated one of leads of a leadframe and an associated one of the electrode pads by reverse bonding, with a point on each lead of the plurality of leads being a starting point, and with each electrode pad of the first semiconductor chip being an ending point.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising:
- connecting wires to each an associated one of the leads and an associate done of the electrode pads by the reverse bonding, with a point on each lead of the plurality of leads being a starting point, and with each electrode pad of the second semiconductor chip being an ending point,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the substance is an island portion of the leadframe.
4. A method of manufacturing a semiconductor device comprising:
- preparing first and second semiconductor chips and a plurality of leads, each of the first and second semiconductor chips having a first main surface on which a plurality of electrode pads are formed and a second main surface;
- connecting by use of a first wire each of the electrode pads of the first semiconductor chip to an associated one of the leads, the connecting of the first wire being performed by a reverse boding method in which each of the electrode pads of the first semiconductor chip and the associated one of the leads are made respectively as an ending point and a starting point of wiring boding; and
- mounting the second semiconductor chip over the first semiconductor chip with an intervention of a spacer therebetween.
5. The method as claimed in claim 4, further comprising: connecting by use of a second first wire each of the electrode pads of the second semiconductor chip to an associated one of the leads, the connecting of the second wire being performed by a reverse boding method in which each of the electrode pads of the second semiconductor chip and the associated one of the leads are made respectively as an ending point and a starting point of wiring boding.
6. The method as claimed in claim 5, further comprising: encapsulating the first and second semiconductor chips, the spacer, the first and second wires and respective portions of the leads.
7. The method as claimed in claim 4, wherein said spacer is formed a part of a lead frame having the leads, said spacer being made of the same material as each of the leads.
8. The method as claimed in claim 4, wherein the spacer intervenes between the first main surface of the first semiconductor chip and the second main surface of the second semiconductor chip.
9. The method as claimed in claim 4, wherein each of the leads positions at a level that is higher than the first main surface of the first semiconductor chip.
10. The method as claimed in claim 9, wherein each of the leads positions at a level that is lower than the second main surface of the second semiconductor chip.
Type: Application
Filed: Aug 6, 2007
Publication Date: Feb 14, 2008
Applicant: NEC ELECTRONICS CORPORATION (Kanagawa)
Inventor: Naoto Kimura (Fukuoka)
Application Number: 11/882,845
International Classification: H01L 21/00 (20060101);