Method of manufacturing a nonvolatile semiconductor memory device and select gate device having a stacked gate structure
A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells. The select gate is formed with a STI recess process in advance locally in the select area.
Latest Eon Silicon Solution Inc. Patents:
- Memory erasing method and driving circuit thereof
- Method of identifying damaged bitline address in non-volatile
- Semiconductor device for accelerating erase verification process and method therefor
- NON-VOLATILE MEMORY HAVING DISCRETE ISOLATION STRUCTURE AND SONOS MEMORY CELL, METHOD OF OPERATING THE SAME, AND METHOD OF MANUFACTURING THE SAME
- Local word line driver and flash memory array device thereof
This application is a divisional of U.S. Pat. No. 6,720,610, and U.S. Pat. No. 5,150,178.
FIELD OF THE INVENTIONThe present invention generally relates to nonvolatile semiconductor memory device. More particularly, it pertains to a method and structure for an improve NAND select gate formation.
BACKGROUND OF THE INVENTIONThis invention relates to a nonvolatile semiconductor memory device and its manufacturing method.
There is known an electrically rewritable, nonvolatile semiconductor memory (Flash) using memory cells of a stacked-gate structure stacking floating gates and control gates. This kind of Flash uses a tunneling insulation film as a first gate insulating film between floating gates and a semiconductor substrate and typically uses, as the second gate insulating film between floating gates and control gates, an ONO film which is a multi-layered film of a silicon oxide film (O) on a silicon nitride film (N) on a silicon oxide film (O).
Each memory cell is formed in an element-forming region partitioned by an element isolation/insulation film. In general, a floating gate electrode film is divided in the direction of control gate line (word line) by making a slit on the element isolation/insulation film. In the step of making the slit, division of floating gates in the bite-line direction is not yet done. Then a control gate electrode film is stacked via an ONO film on all surfaces of the substrate including the top of the slit-processed floating gate electrode film, and by sequentially etching the control gate electrode film, ONO film, and floating gate electrode film, control gates and floating gates are then isolated in the bit-line direction. After that, source and drain diffusion layers are formed in self-align-ment with the control gates.
SUMMARY OF THE INVENTIONIt is therefore an object of the invention to provide a nonvolatile semiconductor memory device improved in reliability by preventing destruction of data caused by movements of electric charges between floating gates, and also relates to its manufacturing method.
According to the first aspect of the invention, there is provided a nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;
floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;
second gate insulating films formed on said floating gates, and divided and separated above said element isolation/insulation films;
control gates formed on said floating gates via said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control gates.
According to the second aspect of the invention, there is provided a nonvolatile semiconductor memory device comprising:
a semiconductor substrate; a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;
floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;
second gate insulating films formed on said floating gates to continuously extend over a plurality of element-forming regions along recesses made into surfaces of said element isolation/insulation films;
control gates formed on said floating gates via said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control gates.
According to the third aspect of the invention, there is provided a manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:
making element isolation/insulation films that partition element-forming regions in a semiconductor substrate;
stacking a first gate electrode material film and a second gate insulating film on said semiconductor substrate via a first gate insulating film;
etching said second gate insulating film and the underlying first gate electrode material film to make slits that separate said first gate electrode material film above said element isolation/insulation films;
forming an insulating film on side surfaces of said first gate electrode material film, and thereafter stacking a second gate electrode material film;
sequentially etching said second gate electrode material film, said second gate insulating film and first gate electrode material film to pattern said first gate electrode film into floating gates and said second gate electrode material film into control gates;
and making source and drain diffusion layers in self alignment with said control gates.
According to the fourth aspect of the invention, there is provided a manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of: making element isolation/insulation films that partition element-forming regions in a semiconductor substrate;
stacking a first gate electrode material film on said semiconductor substrate via a first gate insulating film;
etching said first gate electrode material film to make slits that separate said first gate electrode material film on said element isolation/insulation films;
etching surfaces of said element isolation/insulation films exposed to said slits to make recesses;
stacking a second gate electrode material film on said first gate electrode material film and said element isolation/insulation films via said first gate insulating film;
sequentially etching said second gate electrode material film, said gate insulating film and said first gate electrode material film to pattern said first gate electrode material film into floating gates and said second gate electrode material film into control gates;
and making source and drain diffusion layers in self-alignment with said control gates.
According to the fifth aspect of the invention, there is provided a manufacturing method of a select gate. Semiconductor device, comprising the steps of: making element isolation/insulation films that partitions element-forming regions in a semiconductor substate; stacking a first gate electrode material film on said semiconductor Substrate via a first gate insulating film; second gate insulating films formed on said, First gate electrode film, and second gate formed on said, First gate via said second gate insulating film, and source and drain diffusion area formed in self-alignment with said select gate.
According to the invention, by partially etching element insulation films in the select gate area, followed by first gate formed in said element-forming region and select gate region via a first gate insulating film, and followed by a CMP (Chemical Mechanical Polish) process, both non-volatile memory floating gate and select gate device is hereby formed simultaneously.
second gate insulating films formed on said floating gates and control gate devices;
control gates formed on said floating gates via said second gate insulating films; and
source and drain diffusion layers formed in self-alignment with said control gates.
Thereby, also when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.
BRIEF DESCRIPTION OF THE DRAWINGSThe above objects and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments, and by reference to the attached drawings in which:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention.
The embodiments are described below by reference to NAND type nonvolatile memory devices.
Referring to the respective sectional views in
Referring to
For example, in
For example, in
The select transistors operate as typical transistors rather than as floating gate storage devices. Therefore, in the areas where select transistors are to be formed part of, the control gate 501 and interdielectric 450 is patterned to create contact holes so that contact can be connected to 401 for the select transistor.
In
Claims
1. A non-volatile semiconductor device structure comprising:
- a semiconductor substrate;
- a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;
- floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;
- Second gate insulating films formed on said floating gates, and divided and separated above said element isolation/insulation films;
- Control gates formed on said floating gates via said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control gates.
2. The method according to claim 1, wherein the floating gate is divided and separated by increasing the height of element insulation films (301), followed by first gate formed in said element-forming region via a first gate insulating film, and followed by a CMP (Chemical Mechanical Polish) process to divide and separate the floating gates.
3. The method according to claim 2, wherein the division and separation of floating gates is processed by floating gate material etch back process.
4. The method according to claim 2, wherein the height of element insulation films (301) is increased for the division and separation of floating gates during CMP or floating gate material etch back process.
5. The method according to claim 2, wherein the height of element insulation films (301) is increased by increasing the thickness of STI pad nitride 800, or reducing the oxide loss after STI pad nitride removal
6. A semiconductor device structure for select gate comprising:
- forming a first layer of polysilicon over a tunnel oxide layer, said tunnel oxide layer being situated on a substrate; the first layer of polysilicon is not patterned during the division and separation of floating gates;
- fabricating an ONO stack and 2nd layer of polysilicon over said first layer of polysilicon; the 2nd layer of polysilicon can either be electrically connected to 1st layer of polisilicon or not.
7. The method according to claim 6 wherein said the 1st polysilicon in select gate area is protected during the process of division and separation of floating gates.
8. The method according to claim 7, wherein the height of element insulation films (301) in the select gate area is intentionally reduced before the formation of a first gate insulating film.
9. The method according to claim 8, wherein the reduction of the height of element insulation films (301) can be either by wet etch process or dry etch process
10. The method according to claim 2 and claim 7, wherein the height of element insulation films in non-volatile semiconductor device area is protected during the reduction of the height of element insulation films (301) in the select gate area.
11. The method according to claim 10, wherein the height of element insulation films in non-volatile semiconductor device area can be protected by photoresist, while the select gate area is exposed to the etch process
Type: Application
Filed: Apr 20, 2007
Publication Date: Apr 3, 2008
Applicant: Eon Silicon Solution Inc. (Chupei)
Inventor: Yider Wu (Taipei)
Application Number: 11/789,471
International Classification: H01L 29/76 (20060101); H01L 21/336 (20060101);