Plating Device, Plating Method, Semiconductor Device, And Method For Manufacturing Semiconductor Device

An object of the present invention is to provide a face-down type jet plating device in which deterioration in plating quality due to minute solid foreign matters derived from a black film etc. is prevented without impairing operativity. The plating device is designed such that a partition (7) is provided between a semiconductor wafer (1) and an anode (5) so that the anode (5) and the semiconductor wafer (7) are separated from each other and a plating tank (100) is divided into a substrate-to-be-plated chamber and an anode chamber.

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Description
TECHNICAL FIELD

The present invention relates to a plating device, a plating method, a semiconductor device, and a method for manufacturing a semiconductor device. Specifically, the present invention relates to: a plating device and a plating method allowing minute plating for wiring to be formed on a surface to be plated; and a semiconductor device and a method for manufacturing the semiconductor device

BACKGROUND ART

Recently, metal plating is used for forming wiring on a semiconductor wafer and the like. Examples of a conventional device for metal plating include: a face-down type jet plating device; a rack-type vertical plating device; and a face-up type jet plating device.

As shown in FIG. 7, the face-down type jet plating device includes: a wafer holder 2′ for holding a semiconductor wafer 1′; a cup 3′; a plating solution jetting pipe 4′ for supplying a plating solution into the cup 3′; and an anode 5′. The anode 5′ is generally made of high phosphorous copper. The anode 5′ is provided in the cup 3′. The cup 3′ is provided with the wafer holder 2′. The semiconductor wafer 1′ is held by the wafer holder 2′ so as to be above the cup 3′. The plating solution jetting pipe 4′ is provided under the semiconductor wafer 1′ in the face-down type jet plating device. Consequently, a plating solution jetted out of the plating solution jetting pipe 4′ is supplied from under the semiconductor wafer 1′. As a result, plating is performed on a surface to be plated.

Note that, although not shown in FIG. 7, the face-down type jet plating device includes: a plating solution tank for containing the cup 3′ therein; a plating solution storage tank for supplying a plating solution; a pump for circulating the plating solution through the plating device; a filter for filtering solid foreign matters in the plating solution; and a pipe for connecting these members.

In the face-down type jet plating device, a plating solution in the plating solution storage tank is supplied by the pump to the lower part of the cup 3′ through the filter. The plating solution is supplied from the lower part of the cup 3′, flows through the plating solution jetting pipe 4′, and reaches, via the anode 5′, a surface of the semiconductor wafer 1 to be plated. Thereafter, the plating solution leaks from a border of the upper part of the cup 3′ (a space between the wafer holder 2′ and the cup 3′) to the outside of the cup 3′, is recovered into the plating solution tank, and reflows into the plating solution storage tank.

Such face-down type jet plating device is disclosed in Patent Document 1 for example. Patent Document 1 (Japanese Unexamined Patent Publication No. 24307/2001 (Tokukai 2001-24307; published on Jan. 26, 2001)) discloses a face-down type jet plating device, which includes “a flowing-out port through which part of the plating solution flowing in the plating tank is made to flow out of the tank from a through-hole of the anode or the periphery of the anode”. Furthermore, a plating device in which an anode is an insoluble electrode such as platinum is known.

As shown in FIG. 8, the rack-type vertical plating device includes an anode 6″, a rack 24, and a plating tank 12. The anode 6″ is generally provided in an anode bag 13 made of a cloth having internal raising. Examples of the anode 6″ include: spherical high phosphorous copper in a titan basket; and a copper plate made of high phosphorous copper. The rack 24 is a plate-shaped jig which includes a power feeding section for the semiconductor wafer 1 and which has a hole whose inside diameter is a bit smaller than the semiconductor wafer 1. The plating tank 12 includes: a wafer suppresser 25 which serves to fix the semiconductor wafer 1 to the rack 24 as well as serves to insulate the back surface of the semiconductor wafer 1; and a squeegee (not shown) for stirring a plating solution.

Note that, although not shown in FIG. 8, the rack-type vertical plating device includes: a plating solution tank; a plating solution storage tank for supplying a plating solution; a pump for circulating a plating solution through the plating device; a filter for filtering solid foreign matters in the plating solution; a pipe for connecting these members; and additional devices.

The plating solution is supplied by the pump from the storage tank to a flowing-in port 14 through the filter. Then, the plating solution flows near the anode bag 13 including the anode 6 in the plating tank 12. Thereafter, the plating solution reaches a surface of the semiconductor wafer 1 to be plated, flows from an upper edge of the plating tank 12 to a dam 15, and reflows to the plating solution storage tank through a return pipe (not shown) which is a part of the dam 15. Such rack-type vertical plating device is disclosed in Patent Document 2 (Japanese Unexamined Patent Publication No. 87299/2000 (Tokukai 2000-87299; published on Mar. 28, 2000)) for example.

A face-up type jet plating device is designed such that a surface-to-be-plated of a semiconductor wafer is positioned to face upward, an anode is positioned to face the surface-to-be-plated, and a plating solution is supplied from above the semiconductor wafer.

Such face-up type jet plating device is disclosed in Patent Document 3 (Japanese Unexamined Patent Publication No. 49498/2001 (Tokukai 2001-49498; published on Feb. 20, 2001)) and Patent Document 4 (Japanese Unexamined Patent Publication No. 24308/2001 (Tokukai 2001-24308; published on Jan. 26, 2001)). The face-up type jet plating device disclosed in Patent Document 3 is designed such that an ion exchange membrane or a porous neutral membrane is provided at the bottom of an anode chamber and the anode chamber is filled with a plating solution, thereby preventing a black film from being dried and detached. The face-up type jet plating device disclosed in Patent Document 4 is designed such that a porous member having multiple pores is provided at the bottom of an anode chamber.

Furthermore, a plating device having different structure from the above plating devices is disclosed in Patent Document 5 (Japanese Unexamined Patent Publication No. 73889/2003 (Tokukai 2003-73889; published on Mar. 12, 2003)) for example. This plating device is an electrolytic copper plating device for a semiconductor wafer, in which a plating tank is divided into a cathode chamber and an anode chamber by using a negative ion exchange membrane and electrolytic copper plating is performed by using an insoluble electrode as an anode.

In these plating devices, it is very important to form an even laminar flow on a whole surface-to-be-plated of the semiconductor wafer. Therefore, finish of plating is greatly influenced by whether a laminar flow is made from a center to peripheral of the surface-to-be-plated of the semiconductor wafer.

A conventional face-up type jet plating device is designed such that a semiconductor wafer is rotated so that a laminar flow of a plating solution is formed, via a side flowing-in port/flowing-out port, on a whole surface-to-be-plated of a semiconductor wafer. For that reason, the conventional face-up type jet plating device requires not only a mechanism for holding a semiconductor wafer but also a mechanism for rotating the semiconductor wafer, resulting in large-scale device.

On the other hand, a conventional face-down jet plating device is so designed as to jet a plating solution from a central part of a surface-to-be-plated of a semiconductor wafer, and therefore the plating device and the semiconductor wafer are fixed with each other, resulting in a simpler device.

However, the conventional face-down type jet plating device has the following problem.

In the face-down type jet plating device, minute solid foreign matters attach to a surface-to-be-plated, resulting in deterioration in plating quality. It is attributable to a surface of an anode in a route in which a plating solution is supplied by a pump from a plating solution storage tank, is filtered by a filter, is supplied from the bottom of a cup, flows near the anode, and reaches a surface-to-be-plated of a semiconductor wafer. When the anode includes high phosphorous copper, a black film is formed on the surface of the anode. The black film is made of a monovalent copper complex (Cu+) including chlorine (Cl) and phosphorous (P). The black film is made as a result of combination between chlorine and phosphorous and monovalent copper ions generated by anode melting.

The black film can suppress generation of slime by suppressing disproportionation of copper which is indicated by the following formula (1).


2Cu+→Cu+Cu2+  (1)

However, the black film once formed tends to be detached from the surface of the anode. The detached minute black film is conveyed along with a flowing plating solution to the surface-to-be-plated of the semiconductor wafer. Consequently, the black film attaches to the plated surface of the semiconductor wafer.

The above problem of the black film can be prevented by using an insoluble electrode as an anode. However, at that time, an additive in the plating solution is subjected to oxidative decomposition. Consequently, more amount of the plating solution is consumed or a decomposition product due to the oxidative decomposition contaminates the plating solution.

On the other hand, in the conventional rack-type vertical plating device, an anode including high phosphorous copper is provided in an anode bag made of a cloth having internal raising. Consequently, it is possible to prevent solid foreign matters derived from a black film from attaching to a semiconductor wafer. However, such vertical plating device requires fixing a semiconductor wafer to a rack so that the semiconductor wafer is held in a plating tank. This fixation drops productivity and plating quality and prevents automation.

DISCLOSURE OF INVENTION

The present invention was made in view of the foregoing problems. An object of the present invention is to provide: a plating device and a plating method each of which prevents minute solid foreign matters derived from a black film etc. from deteriorating plating quality, without impairing operativity in a face-down type jet plating device; and a semiconductor device and a method for manufacturing the semiconductor device.

In order to solve the foregoing problems, the plating device of the present invention is a plating device, including a plating tank which has an anode therein and causing a plating solution to flow into the plating tank and to jet upward to touch a surface-to-be-plated of a substrate-to-be-plated while electrifying between the anode and the substrate-to-be-plated, so that plating is performed, the plating tank including a partition between the substrate-to-be-plated and the anode, the partition separating the anode from the substrate-to-be-plated, and the plating tank being divided into a substrate-to-be-plated chamber and an anode chamber.

The plating device of the present invention causes the plating solution to jet upward to touch the surface-to-be-plated of the substrate-to-be-plated while electrifying between the anode and the substrate-to-be-plated, so that plating is performed. That is, the plating device of the present invention performs plating in a face-down manner.

Note that, the “substrate-to-be-plated chamber” is a space including the substrate-to-be-plated out of two areas separated by the partition. The “anode chamber” is a space including the anode out of the two areas separated by the partition.

Further, with the arrangement, the anode and the substrate-to-be-plated are separated from each other by the partition, and the plating tank is divided into the substrate-to-be-plated chamber and the anode chamber. Consequently, it is possible to prevent particles etc. derived from the anode from contaminating the plated surface.

As described above, with the arrangement, it is possible to provide a plating device capable of preventing deterioration in plating quality due to minute solid foreign matters derived from a black film etc., without impairing operativity.

In order to solve the foregoing problems, the plating method of the present invention is a plating method for causing a plating solution to flow into a plating tank and jet upward to touch a surface-to-be-plated of a substrate-to-be-plated while electrifying between an anode in the plating tank and the substrate-to-be-plated, so that plating is performed, said method comprising the step of dividing a laminar flow of the plating solution into a laminar flow of the plating solution jetted to the surface-to-be-plated and a laminar flow of the plating solution flowing to a neighbor of the anode.

With the arrangement, plating is performed while dividing a laminar flow of the plating solution into a laminar flow of the plating solution jetted to the surface-to-be-plated and a laminar flow of the plating solution flowing to a neighbor of the anode. Consequently, it is possible to prevent particles etc. derived from the anode from contaminating the plated surface. As a result, it is possible to prevent deterioration in plating quality due to minute solid foreign matters derived from a black film etc.

In order to solve the foregoing problems, the method of the present invention for manufacturing a semiconductor device is a method, comprising the step of causing a plating solution to flow into a plating tank and to jet upward to touch a surface-to-be-plated of a substrate-to-be-plated while electrifying between an anode and the substrate-to-be-plated in the plating tank, so that plating is performed, in the step, the anode and the surface-to-be-plated are positioned to be separated from each other in the plating tank by a partition.

With the arrangement, in the step, plating is performed while the anode and the surface-to-be-plated are separated from each other in the plating tank by the partition. Consequently, it is possible to prevent particles etc. derived from the anode from contaminating the plated surface.

As a result, with the arrangement, it is possible to obtain a semiconductor device which is free from minute solid foreign matters derived from a black film etc. on the surface of the anode and which has plated wiring with high quality.

In order to solve the foregoing problems, the semiconductor device of the present invention is manufactured through the method for manufacturing a semiconductor device.

With the arrangement, the semiconductor device is manufactured through the method. Consequently, it is possible to provide a semiconductor device which is free from minute solid foreign matters derived from a black film etc. on the surface of the anode and which has plated wiring with high quality.

Additional objects, features, and strengths of the present invention will be made clear by the description below.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross sectional drawing schematically illustrating a structure of a plating tank provided in a plating device of an embodiment of the present invention.

FIG. 2 is a cross sectional drawing illustrating an example of a structure of a wafer holder of the plating tank.

FIG. 3 are drawings illustrating a structure of an area surrounded by an internal cylinder and a partition. The upper drawing is a top plan drawing seen from a surface of a semiconductor wafer to be plated. The lower drawing is a cross sectional drawing.

FIG. 4 is a drawing schematically illustrating a structure of a plating device of an embodiment of the present invention.

FIG. 5 is an explanatory drawing of a structure of an ion exchange membrane.

FIG. 6 is an explanatory drawing of permselectivity of the ion exchange membrane.

FIG. 7 is a cross sectional drawing schematically illustrating a conventional face-down type jetting plating device.

FIG. 8 is a cross sectional drawing schematically illustrating a conventional rack-type vertical plating device.

FIG. 9 is a drawing schematically illustrating a structure of a semiconductor wafer used in the present invention.

FIG. 10(a) is a plan drawing schematically illustrating a semiconductor chip formed on a semiconductor wafer after a plating step.

FIG. 10(b) is a cross sectional drawing schematically illustrating the semiconductor chip.

FIG. 11(a) is a cross sectional drawing schematically illustrating a structure of a part of a semiconductor chip before a seed layer forming step of a method of the present invention for manufacturing a semiconductor wafer.

FIG. 11(b) is a cross sectional drawing schematically illustrating a structure of a part of a semiconductor chip after the seed layer forming step of the method of the present invention for manufacturing a semiconductor wafer.

FIG. 11(c) is a cross sectional drawing schematically illustrating a structure of a part of a semiconductor chip after a photoresist applying step of the method of the present invention for manufacturing a semiconductor wafer.

FIG. 11(d) is a cross sectional drawing schematically illustrating a structure of a part of a semiconductor chip after a photoresist pattern forming step of the method of the present invention for manufacturing a semiconductor wafer.

FIG. 11(e) is a cross sectional drawing schematically illustrating a structure of a part of a semiconductor chip after a plating step of the method of the present invention for manufacturing a semiconductor wafer.

FIG. 11(f) is a cross sectional drawing schematically illustrating a structure of a part of a semiconductor chip after a stripping step of the method of the present invention for manufacturing a semiconductor wafer.

FIG. 11(g) is a cross sectional drawing schematically illustrating a structure of a part of a semiconductor chip after an etching step of the method of the present invention for manufacturing a semiconductor wafer.

FIG. 12(a) is a cross sectional drawing schematically illustrating a part of a semiconductor chip having a wiring plating layer thereon before an overcoat layer forming step in an external connection terminal providing step of providing a semiconductor wafer having the wiring plating layer thereon with an external connection terminal.

FIG. 12(b) is a cross sectional drawing schematically illustrating a part of a semiconductor chip after the overcoat layer forming step in the external connection terminal providing step.

FIG. 12(c) is a cross sectional drawing schematically illustrating a part of a semiconductor chip after an overcoat layer pattern forming step in the external connection terminal providing step.

FIG. 12(d) is a cross sectional drawing schematically illustrating a part of a semiconductor chip after an external connection terminal forming step in the external connection terminal providing step.

 BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1

With reference to FIGS. 1 to 6, the following explains an embodiment of the present invention.

FIG. 1 is a cross sectional drawing schematically illustrating a structure of a plating tank provided in a plating device of the present embodiment. As shown in FIG. 1, a plating tank 100 includes: a wafer holder 2 for holding a semiconductor wafer (substrate-to-be-plated) 1; a cup 3; a plating solution jetting pipe 4; an anode 5; a supporter 6 for supporting the anode 5; and a partition 7. The cup 3 includes an internal cylinder 31 and an external cylinder 32.

The internal cylinder (second cylindrical cup) 31 and the external cylinder (first cylindrical cup) 32 are cups each having substantially a cylindrical shape, with its upper end open. The diameter of the internal cylinder 31 is smaller than the diameter of the external cylinder 32. The external cylinder 32 has at its lowest central part a plating solution flowing-in port E through which a plating solution flows in.

The internal cylinder 31 has at its bottom the partition 7 having a donut shape, which separates the internal cylinder 31 from the external cylinder 32. That is, the partition 7 is provided between a surface-to-be-plated W of the semiconductor wafer 1 and the anode 5, and separates the anode 5 from the semiconductor wafer 1. Consequently, the plating tank 100 is divided into a substrate-to-be-plated chamber and an anode chamber. The “substrate-to-be-plate chamber” means a space surrounded by the internal cylinder 31 and the partition 7. The “anode chamber” means a space surrounded by the external cylinder 32 and the partition 7.

As shown in FIG. 1, the plating solution jetting pipe 4 is provided so as to penetrate a hole at the center of the partition 7. The supporter 6 is connected with the external cylinder 32 and has a structure through which a plating solution flows. The anode 5 is provided on the supporter 6. The anode 5 is positioned above the lower end of the plating solution jetting pipe 4.

The partition 7 includes hydrocarbon cation exchange membrane. However, the partition 7 is not particularly limited as long as it includes a permeation member allowing metal ions in a plating solution flowing near the anode 5 and the supporter 6, that is, flowing in the anode chamber, to permeate the permeation member. For example, the partition 7 may include an ion exchange membrane, a neutral membrane, a porous ceramics, etc. In the case where the partition 7 includes a hydrocarbon cation exchange membrane, examples of the hydrocarbon cation exchange membrane include SELEMION® (manufactured by ASAHI GLASS ENGENEERING Co., Ltd., hydrocarbon cation exchange membrane) and NEOSEPTA CM-1® (manufactured by ASTOM Corporation, hydrocarbon cation exchange membrane). The structure of the partition 7 is specifically explained later.

Furthermore, the partition 7 may allow not only metal ions but also positive ions (ions having the same electric nature as metal ions) which are components of an additive to permeate the partition 7.

The plating solution jetting pipe 4 and the supporter 6 are made of polypropylene. The anode 5 is a soluble anode made of high phosphorous copper. However, the plating solution jetting pipe 4 and the supporter 6 are not particularly limited as long as they have dimensional stability and are resistive to a plating solution. For example, the plating solution jetting pipe 4 and the supporter 6 may be made of hard vinyl chloride.

The dimension of the semiconductor wafer 1 applicable to the present invention may be set according to the dimension of each member of the plating tank 100. For example, the diameter of the semiconductor wafer 1 may range from approximately 100 mm to 500 mm. More specifically, the diameter may be approximately 150 mm.

The internal cylinder 31 has a bottom to which the partition 7 is attached and fixed. The internal diameter of the internal cylinder 31 should be smaller than the surface-to-be-plated W of the semiconductor wafer 1.

In this way, when the internal diameter of the internal cylinder 31 is smaller than the surface-to-be-plated W of the semiconductor wafer 1, a plating solution jetted from the plating solution jetting pipe 4 is directed to the surface-to-be-plated W of the semiconductor wafer 1 without being exposed to the air. Consequently, the plating device of the present invention allows plating without exposure to the air. This prevents contamination of a plating solution due to floating foreign matters in the air, evaporation of the plating solution, and contamination of surrounding environments due to the evaporation or the mist of the plating solution.

The height of the internal cylinder 31 may range from 50 mm to 100 mm. Here, the dimension of the internal cylinder 31 is as follows: the external diameter is 150 mm, the internal diameter is 140 mm, the thickness is 5 mm, and the height is 80 mm. The internal cylinder 31 has a cylindrical shape.

As mentioned later, the height of the external cylinder 32 is not particularly limited as long as the height allows the plating solution from the plating solution jetting pipe 4 to sufficiently cover the surface-to-be-plated W from its central part to its peripheral part and the upper end of the external cylinder 32 is lower than the upper end of the internal cylinder. Here, the internal diameter of the external cylinder 32 is 160 mm. The external cylinder 32 is designed such that the height of the external cylinder 32 allows the plating solution from the plating solution jetting pipe 4 to sufficiently reach the peripheral surface of the semiconductor wafer 1 and the upper end of the external cylinder 32 is lower than the upper end of the internal cylinder 31.

The external diameter of the internal cylinder 31 is 150 mm and the internal diameter of the external cylinder 32 is 160 mm. The gap (plating solution flowing-out port) between the internal cylinder 31 and the external cylinder 32 is 5 mm. However, the gap between the internal cylinder 31 and the external cylinder 32 is not limited to this. By narrowing the gap between the internal cylinder 31 and the external cylinder 32, it is possible to increase a difference between the heights of the upper ends of the internal cylinder 31 and the external cylinder 32, which will be mentioned later. By narrowing the gap between the internal cylinder 31 and the external cylinder 32, resistance (pressure) increases due to viscosity of the plating solution. Consequently, even when the internal cylinder is made to have higher height, the plating solution reaches to the upper end of the internal cylinder. As a result, flexibility in designing the plating device increases.

The partition 7 has a donut shape whose external diameter is 140 mm and internal diameter is 40 mm. The external periphery of the partition 7 is attached to the internal cylinder 31 and the internal periphery of the partition 7 is attached to the plating solution jetting pipe 4, so that the partition 7 is fixed. However, the dimension of the partition 7 is not limited to this.

The supporter 6 is provided between the external cylinder 32 and the plating solution jetting pipe 4. The supporter 6 is provided above the bottom of the external cylinder 32 so that the gap between the supporter 6 and the bottom of the external cylinder 32 ranges from at least 5 mm to 20 mm. The supporter 6 has multiple penetrating holes in a vertical direction.

The thickness of the partition 7 preferably ranges from 50 μm to 200 μm, more preferably ranges from 50 μm to 100 μm. When the thickness of the partition 7 is smaller than 50 μm, an electric current for plating is required more than necessary, which deteriorates efficiency in plating. When the thickness of the partition 7 is larger than 200 μm, a black defective appearance called “discoloration” is seen on the plated surface.

Attachment of the partition 7 to the internal cylinder 31 makes a cup member whose thickness is 2 to 10 mm and whose opening is a circle with a diameter of 0.2 to 9 mm or a square, a rectangle, or a quadrangle with a side of 0.2 to 9 mm. The partition 7 (SELEMION partition) is not necessarily a perfect circle. The partition 7 may be a quadrangle at the extreme.

The dimension of the anode 5 made of high phosphorous copper is as follows: the external diameter is 150 mm, the internal diameter is 50 mm, and the thickness is 8 m. However, the dimension of the anode 5 is not limited to this. The dimension may be any value as long as the dimension does not prevent the plating solution from flowing through the gap between the supporter 6 and the partition 7 and the gap between the external cylinder 32 and the anode 5. High phosphorous copper in the anode 5 is not particularly limited as long as it includes 0.04 to 0.06% of phosphorous.

The plating solution jetting pipe 4 penetrates the partition 7 and extends above the partition 7 by 20 mm. However, the plating solution jetting pipe 4 is not limited to this as long as the plating solution jetting pipe 4 extends from under the anode 5 to the partition 7.

The dimensions and other factors of the semiconductor wafer 1, the cup 3 (the internal cylinder 31 and the external cylinder 32), the plating solution jetting pipe 4, the anode 5, the supporter 6, and the partition 7 in the plating tank 100 were explained above. The dimensions of the members in the plating tank 100 may be set according to the dimension of the plating tank 100 or the dimension of the semiconductor wafer 1 applied to the plating tank 100.

With reference to FIG. 2, the following specifically explains a structure of the wafer holder 2 for holding the semiconductor wafer 1. FIG. 2 is a cross sectional drawing illustrating an example of the structure of the wafer holder 2 in the plating tank 100. As shown in FIG. 2, the wafer holder 2 includes an O ring 21, contact members 22, and a wafer holding ring 23. The wafer holding ring 23 is held by a supporter (not shown) so that there exists a predetermined gap between the upper part of the internal cylinder 31 and the wafer holding ring 23. The O ring 21 and the contact members 22 are provided on the wafer holding ring 23 and keep attachment to the semiconductor wafer 1 to be held.

Three contact members 22 are provided on a peripheral part of the semiconductor wafer 1 with the same distance among them. However, the number of the contact members 22 is not limited to three. Four or more contact members 22 may be provided on the peripheral part of the semiconductor wafer 1 with the same distance between them. Furthermore, the contact member 22 may attach to the whole peripheral part of the semiconductor wafer 1.

The internal diameter of the wafer holding ring 23 is 140 mm, but not limited to this. The wafer holding ring 23 does not necessarily have a circular shape. The wafer holding ring 23 may be integral with a main body of the device.

The following explains the members of the wafer holder 2.

The O ring 21 is not particularly limited as long as it keeps attachment to the semiconductor wafer 1 and is resistive to a plating solution. The O ring 21 may be made of silicone gum for example. A specific example is Viton® (manufactured by Dupont Dow Elastomers Japan).

The contact member 22 is not particularly limited as long as it keeps attachment to the semiconductor wafer 1, it is conductive, and it is resistive to a used plating solution. The contact member 22 may be made of titan with metal plating for example. Specifically, examples of the contact member 22 include titan with platinum plating, titan with gold plating, resin with gold plating etc, and combinations thereof.

The wafer holding ring 23 is not particularly limited as long as it has dimensional stability and is resistive to a plating solution. The wafer holding ring 23 may be made of hard vinyl chloride or polypropylene for example.

With reference to FIG. 3, the following explains an example of the structure of the partition 7 provided between the surface-to-be-plated W of the semiconductor wafer 1 and the anode 5. FIG. 3 illustrates the structure of an area (substrate-to-be-plated chamber) surrounded by the internal cylinder 31 and the partition 7 in the plating tank 100. The upper drawing is a top plan drawing seen from the surface-to-be-plated W of the semiconductor wafer 1. The lower drawing is a cross sectional drawing.

As illustrated in FIG. 3, the partition 7 has a donut shape seen from the surface-to-be-plated W. The plating solution jetting pipe 4 penetrates the central part of the partition 7. The periphery of the partition 7 is fixed with the bottom of the internal cylinder 31.

The partition 7 includes a semipermeable membrane (permeation member) 71 and semipermeable membrane supporters 72 and 73. The partition 7 is made by the semipermeable membrane supporters 72 and 73 holding the semipermeable membrane 71 between them. The semipermeable membrane supporter 72 is positioned at the anode 5 side and the semipermeable membrane supporter 73 is positioned at the surface-to-be-plated W side of the semiconductor wafer 1.

By electrifying between the semiconductor wafer 1 and the anode 5, the plating solution having flowed to the anode 5 permeates the semipermeable membrane supporter 72. Metal ions of the plating solution permeate the semipermeable membrane 71. The metal ions permeate the semipermeable membrane supporter 73 and flows toward the surface-to-be-plated W (into the substrate-to-be-plated chamber) of the semiconductor wafer 1. At that time, the metal ions of the plating solution permeate the semipermeable membrane 71, but particles of the plating solution do not permeate the semipermeable membrane 71. Consequently, the partition 7 allows for separation of metal ions and particles in the plating solution. This prevents particles due to the anode 5 from contaminating the surface-to-be-plated.

The semipermeable membrane 71 is not particularly limited as long as metal ions of the metal solution can permeate the semipermeable membrane 71 when the semipermeable membrane 71 is immersed in the plating solution. Examples of the semipermeable membrane 71 include a hydrocarbon cation exchange membrane, a neutral membrane, and porous ceramics. In the case where the semipermeable membrane 71 is a hydrocarbon cation exchange membrane, specific examples of the semipermeable membrane 71 include SELEMION® (manufactured by ASAHI GLASS ENGENEERING Co., Ltd., hydrocarbon cation exchange membrane) and NEOSEPTA CM-1® (manufactured by ASTOM Corporation, hydrocarbon cation exchange membrane).

The semipermeable membrane supporters 72 and 73 are not particularly limited as long as they are permeated by a plating solution, they have dimensional stability, and they are resistive to the plating solution. Examples of materials of the semipermeable membrane supporters 72 and 73 include polypropylene and hard vinyl chloride.

The following explains a structure of the semipermeable membrane 71 using an ion exchange membrane including an ion exchange membrane as an example. FIG. 5 is an explanatory drawing of a structure of the ion exchange membrane. FIG. 6 is an explanatory drawing of permselectivity of the ion exchange membrane.

As illustrated in FIG. 5, the “ion exchange membrane” is a membrane which selectively allows ions to permeate it. The ion exchange membrane is roughly classified into a positive ion exchange membrane and a negative ion exchange membrane. As illustrated in FIG. 5, when the positive ion exchange membrane immersed in the plating solution is electrified, the positive ion exchange membrane selectively allows positive ions (M+) to permeate it and does not allow negative ions (B−) to permeate it.

As illustrated in FIG. 6, substituents with negative electric charge are fixed with the positive ion exchange membrane. Consequently, the negative ions (B−) are repulsed by the substituents with negative electric charge and accordingly cannot permeate the positive ion exchange membrane. On the other hand, the positive ions (M+) are not repulsed by the substituents with negative electric charge and accordingly can permeate the positive ion exchange membrane. That is, only the positive ions (M+) can permeate the positive ion exchange membrane.

In contrast, the negative ion exchange membrane has the opposite function. Selective permeation in these ion exchange membranes is caused by electric energy of an electrodialyzer. The electric energy of the electrodialyzer is not particularly limited. The electric energy may be derived from a direct current, a pulse current, or an alternative current.

With reference to FIG. 4, the following explains a structure of a plating device of the present invention. FIG. 4 is a drawing schematically illustrating a structure of the plating device of the present invention.

As illustrated in FIG. 4, the plating device of the present invention includes: the plating tank 100; a plating solution tank 8 for containing the plating tank 100 therein; the plating solution storage tank 9 for supplying a plating solution; a pump 10 for circulating the plating solution through the plating device; a filter 11 for filtering solid foreign matters in the plating solution; and a pipe T connecting these members.

In the plating device of the present invention, a plating solution in the plating solution storage tank 9 is supplied by the pump 10, via the filter 11, to a plating solution flowing-in port E provided at the lower part of the plating tank 100. The plating solution is supplied from the plating solution flowing-in port E, flows through the plating solution jetting pipe 4, and reaches the surface-to-be-plated W of the semiconductor wafer 1. Thereafter, the plating solution leaks from a border of the upper part of the internal cylinder 31 (a space between the wafer holder 2 and the internal cylinder 31) to the outside of the plating tank 100, is recovered into the plating solution tank 8, and returns to the plating solution storage tank 9.

The plating solution tank 8, the plating solution storage tank 9, and the pipe T are not particularly limited as long as they have dimensional stability and are resistive to a used plating solution. Examples of materials of them include hard vinyl chloride and polypropylene.

Further, the pump 10 is not particularly limited as long as it is resistive to a used plating solution and causes the plating solution to flow without having a bad influence on the plating solution. Examples of the pump 10 include magnet pump MD-70R (manufactured by IWAKI CO., LTD.) and magnet pumps MD-30R and MD-100R (manufactured by IWAKI CO., LTD.). The material of the pump 10 is not particularly limited as long as it has dimensional stability and is resistive to a used plating solution. The pump 10 may be made of hard vinyl chloride or polypropylene for example.

The filter 11 is not particularly limited as long as the filter 11 has 100% collection efficiency of particles whose grain size corresponds to approximately ½ of the minimum gap of a target plating pattern, the filter 11 is resistive to a used plating solution, and the filter 11 allows the plating solution to flow without a bad influence on the plating solution. Examples of the filter 11 include: polypropylene cartridge filter HDCII (J012; 100% collection efficiency of 1.2 μm size particles) manufactured by Japan Pall Corporation; polypropylene cartridge filter HDCII (J006; 100% collection efficiency of 1.0 μm size particles) manufactured by Japan Pall Corporation; a Teflon® filter; and a hollow fiber membrane filter. Material of the filter 11 is not particularly limited as long as the material has dimensional stability and is resistive to a used plating solution. Examples of the material include hard vinyl chloride and polypropylene.

Although not shown in FIG. 4, a valve, a flow meter, an air vent pipe etc. are connected in the course of a pipe T. A flow of a plating solution can be controlled by a controller (not shown). A voltage can be applied between a surface-to-be-plated and the anode 5 by a power source for plating (not shown).

As an example of plating in the plating device of the present invention, the following details a case where copper plating is performed on the surface-to-be-plated W of the semiconductor wafer 1.

The semiconductor wafer 1 is placed on the wafer holder 2 so that the surface-to-be-plated W of the semiconductor wafer 1 faces downward. The semiconductor wafer 1 is attached to the O ring 21 and the contact member 22 by a wafer suppressor (not shown).

As shown in FIG. 4, a plating solution in the plating solution storage tank 9 is supplied to the filter 11 by the pump 10 controlled by the controller (not shown). The filter 11 removes, from the plating solution, foreign matters which are larger than mesh size of the filter 11. The plating solution flows into the plating solution flowing-in port E of the plating tank 100 through the pipe. The plating solution having flowed from the plating solution flowing-in port E at the bottom of the external cylinder 32 of the cup 3 flows into the internal cylinder 31 through the plating solution jetting pipe 4. The plating solution is a copper plating solution including an additive and copper which is equivalent to approximately 25 g/L of copper metal (MICROFAB Cu200; manufactured by Electroplating Engineers of Japan).

A part of the plating solution having flowed into the plating solution flowing-in port E flows into a space between the bottom of the external cylinder 32 and the supporter 6. The plating solution flowing in the gap between the bottom of the external cylinder 32 and the supporter 6 (hereinafter referred to as the plating solution flowing in the anode chamber) flows through penetrating holes in the supporter 6, flows upward while enveloping the anode 5, and flows along the partition 7 toward the outer periphery. The anode 5 in the plating device includes high phosphorous copper whose phosphorous is approximately 0.04 to 0.06%.

On the other hand, the plating solution flowing into the internal cylinder 31 via the plating solution jetting pipe 4 (hereinafter referred to as the plating solution flowing into the surface-to-be-plated chamber) has a higher pressure due to kinetic energy of the plating solution and due to a resistance which is caused when the plating solution flowing in the anode chamber flows out of the plating tank 100 through the gap (plating solution flowing-out port) between the internal cylinder 31 and the external cylinder 32. Consequently, a liquid level of the plating solution having flowed in the substrate-to-be-plated chamber reaches the surface-to-be-plated W of the semiconductor wafer 1. Then, the plating solution flows toward the periphery of the surface-to-be-plated W of the semiconductor wafer 1. Then, the solution flows out of the plating tank 100 via the gap between the internal cylinder 31 and the wafer holding ring 23.

The plating solution having flowed out of the plating tank 100 via the gap between the internal cylinder 31 and the external cylinder 32 and the plating solution having flowed out of the plating tank 100 via the gap between the internal cylinder 31 and the wafer holding ring 23 are mixed with each other and are supplied to the plating solution tank 8. The plating solution in the plating solution tank 8 returns to the plating solution storage tank 9 by a vertical interval.

At that time, a voltage is applied between the anode 5 and the surface-to-be-plated W, serving as a cathode, of the semiconductor wafer 1 while controlling an electric current by the power source for plating (not shown). Consequently, an additive in the plating solution works in a predetermined manner on the surface of the anode 5, resulting in generation of copper ions. The generated metal ions permeate the partition 7 and reach, via the inside of the internal cylinder 31, the surface of the semiconductor wafer 1 serving as a cathode. The additive in the plating solution works in a predetermined manner on the surface-to-be-plated W of the semiconductor wafer 1 and accordingly copper ions are deposited as copper and the surface-to-be-plated W is plated with copper.

In the plating device of the present invention, the flow rate of the plating solution supplied by the pump 10 to the filter 11 can be set according to the dimension of the semiconductor wafer 1 or to the dimension of the plating tank 100. Specifically, the flow rate is approximately 20 L per minute or approximately 2 to 20 L per minute.

Furthermore, a voltage to be applied between the surface-to-be-plated W and the anode 5 and a time for applying a voltage can be set according to the dimension of the semiconductor wafer 1 or to the dimension of the plating tank 100. Specifically, a voltage is applied for 25 minutes while controlling an electric current so that current density of the surface-to-be-plated W is 20 mA per 1 cm2.

The internal cylinder 31 is filled with the plating solution which has passed through the filter 11 and has removed solid foreign matters larger than mesh size of the filter. The plating solution having flowed into the anode chamber cannot flow into the internal cylinder 31 due to the partition 7 and the flow of the plating solution. Only copper ions in the plating solution permeate the partition 7 and reach the inside of the internal cylinder 31. Consequently, minute solid foreign matters derived from black film etc. on the surface of the anode 5 do not attach the plated surface. Furthermore, unlike conventional examples, it is unnecessary to use an insoluble electrode so as to prevent attachment of minute solid foreign matters derived from a black film etc. Consequently, it is possible to obtain high-quality plating without an increase in consumption of an additive due to oxidative decomposition of the additive in the plating solution and without deterioration in plating quality due to contamination of the plating solution by decomposition product.

In the above example, a copper plating solution (MICROFAB Cu200; manufactured by Electroplating Engineers of Japan) was used. However, a plating solution in the present embodiment is not limited to this as long as it allows a desired effect.

Explanations were made above as to a case where the partition 7 in the plating device of the present invention is partially or entirely made of a permeation member which allows metal ions in the plating solution to permeate the permeation member. However, the plating device is not limited to this case. The plating device of the present invention may be arranged so that: the internal cylinder 31 whose bottom is the partition 7 has a portion separating the surface-to-be-plated W of the semiconductor wafer 1 from the anode 5 and the portion is partially or entirely made of a permeation member which allows metal ions in the plating solution to permeate the permeation member. That is, the substrate-to-be-plated chamber has a portion separating the anode from the substrate-to-be-plated and the portion is partially or entirely made of a permeation member which allows metal ions in the plating solution to permeate the permeation member. For example, the internal cylinder 31 may be partially or entirely made of such permeation member.

In the face-down type plating device, the plating solution flowing upward from the lower part of the cup flows out of the cup through the gap between the cup and the wafer holder. At that time, a rise of a liquid level by increasing a flow rate of the plating solution is combined with surface tension (hydrophilicity) of the plating solution with the semiconductor wafer, allowing the plating solution to flow toward the periphery of the cup and flow out of the cup, together with wetting the surface-to-be-plated of the semiconductor wafer which is positioned above the gap.

Here, it is very important to form an even flow of the plating solution on a whole surface-to-be-plated of the semiconductor wafer. Therefore, finish of plating is greatly influenced by whether a laminar flow is made from a center to peripheral of the surface.

In a conventional face-down type plating device, providing a partition between an anode and a semiconductor wafer would prevent a plating solution from touching the wafer, which would make plating impossible.

In order to solve the problem, the present invention is designed such that: the structure of a cup is changed from a conventional structure to a double structure including an internal cylinder and an external cylinder, a plating solution jetting pipe is provided so as to penetrate a partition from under an anode toward a wafer, the port of the pipe divides a plating solution into two: a solution which reaches the surface of the wafer and takes part in plating the surface; and a solution which flows near the anode and is drained out of the cup. This allows the plating solution to flow on the surface of the wafer from the center of the wafer with enough flow speed and flow rate and to form a laminar flow, while allowing the plating solution to flow near the anode, to flow along the partition, and to flow out of the cup.

A conventional face-up type jet plating device is designed such that a wafer is rotated so that a flow of a plating solution is evenly formed, via a side flowing-in port/flowing-out port, on a whole surface of a semiconductor wafer to be plated. For that reason, the conventional face-up type jet plating device requires not only a mechanism for holding a semiconductor wafer but also a mechanism for rotating the semiconductor wafer, resulting in a large-scale device.

In contrast, the plating device of the present invention can flow the plating solution from the center of the semiconductor wafer. Consequently, the plating tank and the semiconductor wafer are fixed with each other, realizing a simpler structure.

The plating device of the present invention may be expressed as a face-down type jet plating device for plating a substrate, wherein an anode and a surface-to-be-plated are positioned to be separated from each other in a plating cup. The plating device supplies a plating solution into the plating cup.

As a result, in the plating method in which the plating device causes the plating solution to flow into the plating cup and to touch the surface-to-be-plated while electrifying between the anode in the plating cup and the surface-to-be-plated, the plating solution having flowed to the neighbor of the anode in the plating cup does not reach the surface-to-be-plated by the flow of the plating solution. Alternatively, in the method, the plating solution having flowed into the neighbor of the anode in the plating cup can flow out of the cup without reaching the surface-to-be-plated.

The plating device is designed such that: a structure for separating the anode from the surface-to-be-plated in the plating cup is partially or entirely made of a material which, when immersed in an electrolytic solution, allows ions to permeate the material. Examples of the material include a semipermeable membrane, an ion exchange membrane and other materials.

The plating device is designed such that the plating solution is a conductive solution including copper or a conductive solution in which other component is added to the conductive solution including copper. Further, the plating solution includes 14 to 40 g of copper component as copper metal in 1 litter of the plating solution. In the plating device, the anode is a soluble anode plate made of high phosphorous copper.

Embodiment 2

With reference to FIGS. 9 to 12, the present embodiment will detail the semiconductor wafer 1 used as a substrate to be plated in Embodiment 1 and a method for manufacturing the substrate. They are examples of a semiconductor device and a method for manufacturing the semiconductor device. FIG. 9 is a drawing schematically illustrating a structure of the semiconductor wafer 1 used in the present embodiment. FIG. 10 is a drawing schematically illustrating a structure of a semiconductor chip 33 formed on the semiconductor wafer 1 after a plating step. FIG. 10(a) is a plan drawing. FIG. 10(b) is a cross sectional drawing.

As illustrated in FIG. 9, a plurality of semiconductor chips 41 are formed on a surface of the semiconductor wafer 1. A contact section 42 is provided on the periphery of the semiconductor wafer 1. The contact section 42 includes a plating seed layer (not shown) which is exposed. The contact section 42 touches the contact member 22 illustrated in FIG. 2.

As illustrated in FIG. 10(a), the semiconductor chip 41 includes a photoresist layer 18 which may have any shape. As illustrated in FIG. 10(b), the semiconductor chip 41 after a plating step has a seed layer 19 on its surface. The seed layer 19 has, on its surface, a wiring plating layer 16 and the photoresist layer 18. A pad 17 is formed on the seed layer 19 so as to be opposite to the wiring plating layer 16 and the photoresist layer 18. In the semiconductor chip 41, the wiring plating layer 16 and the pad 17 are electrically connected with each other.

With reference to FIG. 11, the following explains procedures of the method of the present embodiment for manufacturing a semiconductor device. FIG. 11 is a cross sectional drawing which illustrates the procedures.

As illustrated in FIG. 11, the method of the present embodiment for manufacturing a semiconductor device includes: a seed layer forming step of forming the seed layer 19 on the surface of the semiconductor chip 41; a photoresist applying step of applying the photoresist layer 18 on the seed layer 19; a photoresist pattern forming step of forming any pattern on the photoresist layer 18; a plating step of plating the photoresist pattern with metal so that a wiring plating layer is formed; a stripping step of stripping off the photoresist layer 18; and an etching step of etching the seed layer 19. FIG. 11(a) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 before the seed layer forming step. FIG. 11(b) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the seed layer forming step. FIG. 11 (c) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the photoresist applying step. FIG. 11(d) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the photoresist pattern forming step. FIG. 11(e) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the plating step. FIG. 11(f) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the stripping step. FIG. 11(g) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the etching step.

As illustrated in FIG. 11(a), the semiconductor chip 41 before the seed layer forming step has the pad 17 formed thereon via which an electric signal is exchanged with the outside.

As illustrated in FIG. 11(b), in the seed layer forming step, the seed layer 19 is formed on the surface of the semiconductor chip 41. Specifically, the semiconductor wafer 1 including the semiconductor chip 41 is positioned in a sputtering device so that the seed layer is formed on the surface where the pad is formed. Thereafter, 1000 Å of a titan layer serving as barrier metal is formed on the surface of the semiconductor wafer 1 and then 3000 Å of a copper layer is formed on the surface.

The copper layer serves as the seed layer 19 for plating. The seed layer 19 serves to promote growth of a plating member (wiring plating layer 16) in the plating step which will be mentioned later.

In the above example, the titan layer serving as barrier metal is formed in the seed layer forming step. However, the layer serving as barrier metal is not limited to this. The layer may be a chrome layer or a layer made of an alloy of titan and tungsten. Further, the layer may be any layer as long as it is made of metal which assures a barrier effect.

Further, the thickness of the titan layer is not limited to 1000 Å. The thickness may have any value of not less than 500 Å as long as the titan layer assures a barrier effect. Further, the thickness of the copper layer serving as the seed layer 19 for plating is not limited to 3000 Å. The thickness may have any value of not less than 1000 Å as long as the copper layer assures even current density in the plating step.

As illustrated in FIG. 11(c), in the photoresist applying step, the photoresist layer 18 is applied on the semiconductor wafer 1 including the semiconductor chip 41 having the seed layer 19 thereon. In the photoresist applying step, photoresist (PMER P-LA900; manufactured by TOKYO OHKA KOGYO CO., LTD.) is spin-coated on the surface of the semiconductor wafer 1 by a spin coater for 30 seconds at 1500 rotations per minute, and then is heated at 115° C. for 5 minutes.

In the above example, PMER P-LA900 is used as photoresist. However, photoresist is not limited to this as long as it is resistive to the plating step which will be mentioned later. An example of photoresist is PMER N-CA3000 (manufactured by TOKYO OHKA KOGYO CO., LTD.). Further, the method for applying photoresist is not limited to spin-coating. For example, the photoresist layer 18 may be formed on the surface of the semiconductor wafer 1 by using a dry film such as ORDYL MP100 Series (manufactured by TOKYO OHKA KOGYO CO., LTD.).

In the photoresist applying step, photoresist is spin-coated by a spin coater for 30 seconds at 1500 rotations per minute and heated at 115° C. for 5 minutes. However, the spin-coating method is not limited to this.

For example, photoresist may be spin-coated at 1000 to 3000 rotations per minute so that photoresist has a sufficiently even thickness, and then the photoresist is heated at 100 to 120° C. for 5 minutes or so.

As illustrated in FIG. 11(d), in the photoresist pattern forming step, a pattern having any shape is formed on the photoresist layer 18 formed in the photoresist applying step. Specifically, after the photoresist applying step, the semiconductor wafer 1 including the semiconductor chip 41 is set in a photolithography machine (not shown). Then, g-ray (436 nm) is irradiated to the photoresist layer 18. Thereafter, a developing device (not shown) develops the photoresist layer 18 using 2.38%-TMAH aqueous solution, so that photoresist on a portion to be subjected to wiring plating is removed.

In the above example, g-ray (436 nm) is irradiated to the photoresist layer 18. However, the ray irradiated to the photoresist layer 18 for exposure is not limited to this as long as the ray allows photoresist to be exposed. Examples of the ray to be irradiated to the photoresist layer 18 include i-ray (365 nm) and deep ultraviolet ray (approximately 200 to 300 nm). Further, in the photoresist pattern forming step, the photoresist layer 18 is developed using 2.38%-TMAH aqueous solution. However, the concentration of the TMAH aqueous solution is not limited to this. For example, the concentration may be 1 to 3%. Alternatively, 25%-TMAH aqueous solution may be diluted with pure water so that the solution has concentration appropriate for development.

As illustrated in FIG. 11(e), in the plating step, plating is performed on a portion where the seed layer 19 is exposed as a result of forming a pattern having any shape on the photoresist layer 18 in the photoresist pattern forming step. Specifically, after the photoresist pattern forming step, the semiconductor wafer 1 including the semiconductor chip 41 is positioned in a plating device illustrated in FIG. 1. That is, the semiconductor wafer 1 is positioned on the wafer holder 2 in the plating device. Then, the O ring 21 and the contact member 22 are attached to the contact member 42 of the semiconductor chip 41 by a wafer suppressor (not shown). The plating step after the semiconductor wafer 1 has been positioned in the plating device is the same as the plating method explained in Embodiment 1 and therefore the explanation of the plating step is omitted here.

In the stripping step, as illustrated in FIG. 11(f), the photoresist layer 18 on the semiconductor chip 41 after the plating step is stripped. Specifically, the semiconductor wafer 1 including the semiconductor chip 41 in FIG. 11(e) is provided in a stripping device (not shown). Then, the semiconductor wafer 1 is immersed in a stripping solution (stripping solution 104; manufactured by TOKYO OHKA KOGYO CO., LTD.) at 70° C. for 20 minutes and shaken occasionally. Consequently, the photoresist layer 18 formed on the surface of the semiconductor wafer 1 is stripped.

In the above example, the semiconductor wafer 1 is immersed in the stripping solution 104 at 70° C. for 20 minutes and shaken occasionally. However, the time for immersion is not limited to this. For example, the time may be 15 to 25 minutes. Further, the semiconductor wafer 1 may be immersed in R-100 (manufactured by MITSUBISHI GAS CHEMICAL COMPANY, INC.) for example as a stripping solution and shaken occasionally. Alternatively, acetone may be used as a stripping solution.

In the etching step, as illustrated in FIG. 11(g), the seed layer 19 which does not have the wiring plating layer 16 thereon is removed by etching. Specifically, the semiconductor wafer 1 including the semiconductor chip 41 illustrated in FIG. 11(f) is provided in an etching device (not shown). Then, the semiconductor wafer 1 is immersed and shaken in 10%-ammonium persulfate aqueous solution at 25° C. for 1.5 minute, so as to etch the seed layer 19 made of copper (Cu) other than the copper plating wiring section (wiring plating layer 16) (so as to etch the seed layer 19 which does not have the wiring plating layer 16 thereon).

In the above example, in the etching step, the semiconductor wafer 1 is immersed and shaken in 10%-ammonium persulfate aqueous solution at 25° C. for 1.5 minute. However, the aqueous solution for etching is not limited to this. For example, the aqueous solution may be 10%-sodium hydroxide aqueous solution, 40%-iron chloride aqueous solution, or other solution. The temperature of the aqueous solution is not limited to this and may be 15 to 40° C.

Further, in the etching step, the semiconductor wafer 1 is subsequently immersed and shaken in 25%-TMAH at 90° C. for 1 hour. Consequently, the titan layer serving as barrier metal (not shown) other than the copper plating wiring section (wiring plating layer 16) (the titan layer which does not have the wiring plating layer 16 thereon) is etched.

In the above example, the semiconductor wafer 1 is immersed and shaken in 25%-TMAH at 90° C. for 1 hour so that the titan layer is etched. However, the aqueous solution for etching the titan layer is not limited to this. For example, the aqueous solution may be a mixture of: hydrochloric acid; and hydrofluoric acid and nitric acid or other solutions.

As described above, the semiconductor wafer 1 including the semiconductor chip 41 manufactured through the seed layer forming step to the plating step is allowed by the plating step to be free from deterioration in plating quality due to minute solid foreign matters derived from a black film etc. Consequently, in the method of the present embodiment for manufacturing a semiconductor device, it is possible to prevent short between wires or other problems due to minute solid foreign matters derived from a black film etc. As a result, it is possible to form a more minute wiring pattern on the surface of a semiconductor chip.

Further, the semiconductor chip 41 which has the wiring plating layer 16 thereon and which is formed on the semiconductor wafer 1 is provided with an external connection terminal. With reference to FIG. 12, the following details an external connection terminal providing step of providing the semiconductor chip 41 having the wiring plating layer 16 thereon with the external connection terminal. FIG. 12 is a cross sectional drawing illustrating the external connection terminal providing step.

The external connection terminal providing step includes: an overcoat layer forming step of forming an overcoat layer on the surface of the semiconductor chip 41 having the wiring plating layer 16 thereon; an overcoat layer pattern forming step of forming any pattern on the overcoat layer; and an external connection terminal forming step of forming the external connection terminal on the wiring plating layer 16 in line with the pattern of the overcoat layer. FIG. 12(a) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 having the wiring plating layer 16 thereon before the overcoat layer forming step. FIG. 12(b) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the overcoat layer forming step. FIG. 12(c) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the overcoat layer pattern forming step. FIG. 12(d) is a drawing schematically illustrating a partial structure of the semiconductor chip 41 after the external connection terminal forming step.

As illustrated in FIG. 12(a), in the semiconductor chip 41 which has the wiring plating layer 16 thereon and which is formed on the semiconductor wafer 1, the seed layer 19 is positioned below the wiring plating layer 16 (the seed layer 19 is positioned at the side where the pad 17 is positioned). The wiring plating layer 16 is electrically connected, via the seed layer 19, with the pad 17 formed on the semiconductor chip 41.

As illustrated in FIG. 12(b), in the overcoat layer applying step, the overcoat layer 20 is formed on the semiconductor wafer 1 including the semiconductor chip 41 having the wiring plating 16 thereon. Specifically, the overcoat layer 20 (CRC-8000; manufactured by SUMITOMO BAKELITE CO., LTD.) is spin-coated by a spin coater for 30 seconds at 1500 rotations per minute and is heated at 130° C. for 5 minutes.

In the above example, in the overcoat layer applying step, CRC-8000 series is used as the overcoat layer 20. However, the material for the overcoat layer 20 is not limited to this. For example, the material may be HD-8800 series (manufactured by Hitachi Chemical). Further, the overcoat layer 20 may be a photosensitive heat-resistive resin such as HD8000.

In the above overcoat layer applying step, the overcoat layer is spin-coated by the spin coater for 30 seconds at 1500 rotations per minute and is heated at 130° C. for 5 minutes. However, the method for applying the overcoat layer is not limited to this. For example, the semiconductor wafer is rotated at 1000 to 3000 rotations per minute so that the overcoat layer has sufficiently even thickness and then the overcoat layer is heated at 120 to 140° C. for approximately 5 minutes.

As illustrated in FIG. 12(c), in the overcoat layer pattern forming step, any pattern is formed on the overcoat layer 20. Specifically, the semiconductor wafer 1 including the semiconductor chip 41 is set in a photolithography machine (not shown) after the overcoat layer applying step. The photolithography machine irradiates g-ray (436 nm) to the overcoat layer 20. Thereafter, a developing device (not shown) develops the overcoat layer 20 using 2.38%-TMAH aqueous solution, so that the overcoat layer 20 corresponding to a portion where an external connection terminal is to be formed is removed. After the removal, the semiconductor wafer 1 is subjected to a hardening process in a nitrogen atmosphere at 300° C. for 2 hours. With the overcoat layer pattern forming step, the semiconductor chip 41 has the wiring plating layer 16 exposed at a portion where the external connection terminal is to be formed.

In the above example, in the overcoat layer pattern forming step, the photolithography machine irradiates g-ray (436 nm) to the overcoat layer 20. However, the ray irradiated to the overcoat layer 20 is not limited to this as long as the ray can expose the overcoat layer. Examples of the ray irradiated to the overcoat layer 20 include i-ray (365 nm) and deep ultraviolet ray (approximately 200 to 300 nm).

In the overcoat layer pattern forming step, the overcoat layer 20 is developed using 2.38%-TMAH aqueous solution. However, the concentration of TMAH aqueous solution is not limited to this. For example, the concentration may be 1 to 3%. Alternatively, 25%-TMAH aqueous solution may be diluted with pure water so as to have a concentration appropriate for development.

In the overcoat layer pattern forming step, the overcoat layer 20 corresponding to a portion where the external connection terminal is to be formed is removed and then the semiconductor wafer 1 is subjected to a hardening process in a nitrogen atmosphere at 300° C. for 2 hours. However, the step after the removal of the overcoat layer is not limited to this. For example, the step may be such that the semiconductor wafer 1 is held at 250 to 350° C. for 1.5 to 3 hours after the removal of the overcoat layer. Further, a temperature-up process and a temperature-down process may be provided before and after the step, respectively.

As illustrated in FIG. 12(d), in the external connection terminal forming step, an external connection terminal 26 is formed at a portion where the overcoat layer 20 has been removed in the overcoat layer pattern forming step. Specifically, the semiconductor wafer 1 including the semiconductor chip 41 is positioned in a solder ball mounter (not shown). Then, flux (not shown) is applied on a portion where the wiring plating layer 16 is exposed and where the external connection terminal is to be formed. On the portion where the flux has been applied is mounted a solder ball serving as the external connection terminal 26 which is held by a tool (not shown). Thereafter, the semiconductor wafer 1 including the semiconductor chip 41 having the solder ball thereon is provided in a reflow device at 245° C. and the solder ball is remelted and cooled down, so that the solder ball serving as the external connection terminal 26 is attached to the wiring plating layer 16.

In the above example, the solder ball serving as the external connection terminal 26 is made of SnAg3.0Cu0.5 (M705; manufactured by Senju Metal Industry Co., Ltd.). However, the solder ball is not limited to this. For example, the solder ball may be made of Sn63Pb37. Alternatively, the solder ball may be made of other lead-free solder.

In the external connection terminal forming step, heating temperature of the reflow device is 245° C. However, the heating temperature is not limited to this. For example, the heating temperature may be 240 to 250° C.

The present invention is not limited to the above embodiments, and a variety of modifications are possible within the scope of the following claims, and embodiments obtained by combining technical means respectively disclosed in the above embodiments are also within the technical scope of the present invention.

As described above, the plating device of the present invention is designed such that the plating tank includes a partition between the substrate-to-be-plated and the anode, the partition separates the anode from the substrate-to-be-plated, and the plating tank is divided into a substrate-to-be-plated chamber and an anode chamber. Further, as described above, in the plating method of the present invention, plating is performed while the substrate-to-be-plated and the anode are separated from each other by the partition and the plating tank is divided into the substrate-to-be-plated chamber and the anode chamber. Consequently, it is possible to prevent contamination of a plated surface due to particles etc. made by the anode. As a result, it is possible to prevent deterioration in plating quality due to minute solid particles derived from a black film etc., without impairing operativity.

Further, as described above, in the method of the present invention for manufacturing a semiconductor device, in the plating step, plating is performed while the anode and the surface-to-be-plated are separated from each other in the plating tank by the partition. Further, the semiconductor device of the present invention is manufactured through the method. Consequently, it is possible to obtain a semiconductor device which is free from minute solid foreign matters derived from a black film etc. on the surface of the anode and which has plated wiring with high quality.

Further, it is preferable to arrange the plating device of the present invention so as to further include a plating solution jetting pipe for jetting the plating solution to the surface-to-be-plated of the substrate-to-be-plated, the plating solution jetting pipe being provided so as to penetrate the partition and so as to allow the plating solution to flow into both the substrate-to-be-plated chamber and the anode chamber.

With the arrangement, the plating solution jetting pipe is provided so as to penetrate the partition and so as to allow the plating solution to flow into both the substrate-to-be-plated chamber and the anode chamber. Consequently, the plating solution flowing into the plating tank can be divided into a laminar flow of the plating solution to the plated substrate area and a laminar flow of the plating solution to the anode chamber. As a result, when the plating solution flows into the plating tank, it is possible to jet the plating solution to the surface-to-be-plated of the substrate-to-be-plated with sufficient flow speed and flow rate.

An example of the structure allowing “the plating solution to flow into both the substrate-to-be-plated chamber and the anode chamber” is such that: the plating tank includes a first cylindrical cup and a second cylindrical cup, the first cylindrical cup is provided with the anode and has a bottom provided with a plating solution flowing-in port via which the plating solution flows into the plating tank, the second cylindrical cup has a bottom which is the partition, and the plating solution jetting pipe is provided so as to penetrate the partition and so as to allow a laminar flow of the plating solution from the plating solution flowing-in port to be divided into a laminar flow of the plating solution to the first cylindrical cup and a laminar flow of the plating solution to the second cylindrical cup.

It is preferable to arrange the plating device of the present invention so that the plating solution flowing into the anode chamber does not flow into the substrate-to-be-plated chamber.

With the arrangement, the plating solution having flowed into the plating tank is divided by the plating solution jetting pipe into the plating solution to the substrate-to-be-plated chamber and the plating solution to the anode chamber. Electrification between the anode and the substrate-to-be-plated makes the plating solution having flowed into the anode chamber include particles derived from the anode. The plating solution passes through the partition, thereby removing the particles. Consequently, the particles do not reach the surface-to-be-plated. As a result, it is possible to prevent the particles from contaminating the plated surface.

Further, the plating device may be arranged so that the plating tank further includes a plating solution flowing-out port via which the plating solution having flowed into the anode chamber flows out of the plating tank.

Further, it is preferable to arrange the plating device of the present invention so that a portion which separates the anode from the substrate-to-be-plated and which includes the partition in the plating tank is partially or entirely made of a permeation member which, when immersed in the plating solution, allows ions in the plating solution to permeate the permeation member.

With the arrangement, when immersed in the plating solution, the permeation member allows ions in the plating solution to permeate the permeation member. Therefore, when a voltage is applied over the plating solution, ions in the plating solution permeate the permeation member. On the other hand, particles derived from the anode do not permeate the permeation member. Consequently, with the arrangement, it is possible to separate ions from particles in the plating solution having flowed into the anode chamber.

Further, the permeation member may be a semipermeable membrane.

Further, the permeation member may include an ion exchange membrane.

Further, it is preferable to arrange the plating device of the present invention so that the partition has a thickness ranging from 50 to 200 μm.

Further, it is preferable to arrange the plating device of the present invention so that the partition includes a hydrocarbon cation exchange membrane.

Further, it is preferable to arrange the plating device of the present invention so as to further include: a plating solution supplying source for storing a plating solution to be supplied to the plating tank; plating solution supplying means for supplying the plating solution stored in the plating solution supplying source to the plating tank; and plating solution filtering means for filtering the plating solution supplied by the plating solution supplying means, the plating solution stored in the plating solution supplying source being supplied to the plating tank by the plating solution supplying means and via the plating solution filtering means, and the plating solution supplied to the plating tank being supplied again to the plating solution supplying source.

Further, the plating solution preferably includes a copper component and is conductive.

There are various kinds of plating solutions for forming various metals. With the arrangement, by using the plating solution including a copper component, it is possible to form copper plating on the surface-to-be-plated of the substrate-to-be-plated. “Copper component” means copper metal, copper ions, or a composition including copper ions.

Further, it is preferable that the plating solution includes a copper component of not less than 14 g and not more than 40 g per 1 litter of the plating solution.

Further, it is preferable that the anode is a soluble anode made of high phosphorous copper.

When an anode including pure copper is used, the amount of foreign matters generated by the anode increases. On the other hand, with the arrangement, the anode is a soluble anode made of high phosphorous copper, and accordingly a black film is formed on the surface of the anode. The black film traps copper complex ions (Cu+) which are causes of foreign matters.

Further, the substrate-to-be-plated may be a semiconductor wafer.

Further, it is preferable to arrange the method of the present invention for manufacturing a semiconductor device so that in the plating step, a flow of the plating solution is divided into a flow to the surface-to-be-plated and a flow to a neighbor of the anode.

As a result, when the plating solution flows into the plating tank in the plating step, it is possible to jet the plating solution to the surface-to-be-plated of the substrate-to-be-plated with sufficient flow speed and flow rate.

Further, it is preferable to arrange the method of the present invention so that in the plating step, the plating solution having flowed to the neighbor of the anode does not flow to the surface-to-be-plated.

With the arrangement, the plating solution including particles generated by electrifying between the anode and the substrate-to-be-plated does not reach the surface-to-be-plated of the substrate-to-be-plated. Consequently, it is possible to prevent the particles from contaminating the plated surface. Further, the method may be arranged so that in the plating step, the plating solution having flowed to a neighbor of the anode is caused to flow out of the plating tank.

Further, it is preferable to arrange the method of the present invention so that a portion which separates the anode from the substrate-to-be-plated and which includes the partition in the plating tank is partially or entirely made of a permeation member which, when immersed in the plating solution, allows ions in the plating solution to permeate the permeation member.

With the arrangement, when a voltage is applied over the plating solution, ions in the plating solution permeate the permeation member. On the other hand, particles derived from the anode do not permeate the permeation member. Consequently, with the arrangement, it is possible to separate ions from particles in the plating solution having flowed into the anode chamber.

Further, the method of the present invention may be arranged so that the permeation member is a semipermeable membrane.

Further, the method of the present invention may be arranged so that the permeation member includes an ion exchange membrane.

Further, it is preferable to arrange the method of the present invention so that the partition has a thickness of not less than 50 μm and not more than 200 μm.

Further, it is preferable to arrange the method of the present invention so that the partition includes a hydrocarbon cation exchange membrane.

Further, it is preferable to arrange the method of the present invention so that the plating step includes the sub-steps of: (i) supplying a plating solution stored in a plating solution supplying source to the plating tank; (ii) filtering the plating solution supplied in the sub-step (ii); and (iii) supplying again the plating solution supplied to the plating tank to the plating solution supplying source.

The sub-step (iii) is a sub-step in which: a plating solution supplied from the plating solution supplying source in the sub-step (i) is subjected to the sub-step (ii) and is supplied to the plating tank and then is supplied again to the plating solution supplying source. Specifically, the sub-step (iii) is a sub-step in which: in the plating device of the present invention, a plating solution stored in the plating solution supplying source is supplied to the plating tank by the plating solution supplying means and via the plating solution filtering means and the plating solution supplied to the plating tank is supplied again to the plating solution supplying source.

Further, it is preferable to arrange the method of the present invention so that the plating solution includes a copper component and is conductive.

It is preferable that the plating solution includes a copper component of not less than 14 g and not more than 40 g per 1 litter of the plating solution.

Further, it is preferable to arrange the method of the present invention so that the anode is a soluble anode made of high phosphorus copper.

Further, the method of the present invention may be arranged so that the substrate-to-be-plated is a semiconductor wafer.

Further, it is preferable to arrange the method of the present invention so as to further include the steps of: (II) forming a seed layer on the surface-to-be-plated; (III) applying photoresist on a surface of the seed layer formed in the step (II); and (IV) forming a pattern by exposing and developing the photoresist, the steps (II) to (IV) being performed before the plating step.

In order to solve the foregoing problems, the semiconductor device of the present invention is manufactured through the method for manufacturing a semiconductor device.

With the arrangement, the semiconductor device is manufactured through the method. Consequently, it is possible to provide a semiconductor device which is free from minute solid foreign matters derived from a black film etc. on the surface of the anode and which has plated wiring with high quality.

The embodiments and concrete examples of implementation discussed in the foregoing detailed explanation serve solely to illustrate the technical details of the present invention, which should not be narrowly interpreted within the limits of such embodiments and concrete examples, but rather may be applied in many variations within the spirit of the present invention, provided such variations do not exceed the scope of the patent claims set forth below.

INDUSTRIAL APPLICABILITY

As described above, the plating device of the present invention is capable of preventing deterioration in plating quality due to minute solid foreign matters derived from a black film etc., without impairing operativity. Therefore, the present invention is applicable to the semiconductor industry.

Claims

1-32. (canceled)

33. A plating device, comprising a plating tank which has an anode therein and causing a plating solution to flow into the plating tank and to jet upward to touch a surface-to-be-plated of a substrate-to-be-plated while electrifying between the anode and the substrate-to-be-plated, so that plating is performed,

the plating tank having a double structure including a first cylindrical cup and a second cylindrical cup whose external diameter is smaller than that of the first cylindrical cup,
the first cylindrical cup being provided with the anode and having a bottom provided with a plating solution flowing-in port via which the plating solution flows into the plating tank,
a gap between side walls of the first cylindrical cup and the second cylindrical cup serving as a plating solution flowing-out port via which the plating solution having flowed into the anode chamber flows out of the plating tank,
the second cylindrical cup having a bottom which is a partition separating the anode from the substrate-to-be-plated,
the plating tank being divided into an anode chamber surrounded by the partition and the first cylindrical cup and a substrate-to-be-plated chamber surrounded by the partition and the first cylindrical cup, and
a plating solution jetting pipe being provided so as to jet the plating solution to the surface-to-be-plated of the substrate-to-be-plated, the plating solution jetting pipe penetrating the partition and allowing a laminar flow of the plating solution from the plating solution flowing-in port to be divided into a laminar flow of the plating solution to the first cylindrical cup and a laminar flow of the plating solution to the second cylindrical cup.

34. The plating device as set forth in claim 33, wherein the plating solution having flowed into the anode chamber does not flow into the substrate-to-be-plated chamber.

35. The plating device as set forth in claim 33, wherein a portion which separates the anode from the substrate-to-be-plated and which includes the partition in the plating tank is partially or entirely made of a permeation member which, when immersed in the plating solution, allows ions in the plating solution to permeate the permeation member.

36. The plating device as set forth in claim 35, wherein the permeation member is a semipermeable membrane.

37. The plating device as set forth in claim 35, wherein the permeation member includes an ion exchange membrane.

38. The plating device as set forth in claim 33, wherein the partition has a thickness ranging from 50 to 200 μm.

39. The plating device as set forth in claim 33, wherein the partition includes a hydrocarbon cation exchange membrane.

40. The plating device as set forth in claim 33, further comprising:

a plating solution supplying source for storing a plating solution to be supplied to the plating tank;
plating solution supplying means for supplying the plating solution stored in the plating solution supplying source to the plating tank; and
plating solution filtering means for filtering the plating solution supplied by the plating solution supplying means,
the plating solution stored in the plating solution supplying source being supplied to the plating tank by the plating solution supplying means and via the plating solution filtering means, and
the plating solution supplied to the plating tank being supplied again to the plating solution supplying source.

41. The plating device as set forth in claim 33, wherein the plating solution includes a copper component and is conductive.

42. The plating device as set forth in claim 33, wherein the plating solution includes a copper component of not less than 14 g and not more than 40 g per 1 lifter of the plating solution.

43. The plating device as set forth in claim 33, wherein the anode is a soluble anode made of high phosphorous copper.

44. The plating device as set forth in claim 33, wherein the substrate-to-be-plated is a semiconductor wafer.

45. A plating method for causing a plating solution to flow into a plating tank and to jet upward to touch a surface-to-be-plated of a substrate-to-be-plated while electrifying between an anode in the plating tank and the substrate-to-be-plated, so that plating is performed,

the plating tank having a double structure including a first cylindrical cup and a second cylindrical cup whose external diameter is smaller than that of the first cylindrical cup,
said method comprising the steps of:
dividing a laminar flow of the plating solution into a laminar flow of the plating solution jetted to the surface-to-be-plated and a laminar flow of the plating solution flowing to a neighbor of the anode; and
causing the plating solution having flowed into the anode chamber to flow out of the plating tank via a plating solution flowing-out port which is a gap between side walls of the first cylindrical cup and the second cylindrical cup.

46. A method for manufacturing a semiconductor device, comprising the step (I) of causing a plating solution to flow into a plating tank and to jet upward to touch a surface-to-be-plated of a substrate-to-be-plated while electrifying between an anode and the substrate-to-be-plated in the plating tank, so that plating is performed,

the plating tank having a double structure including a first cylindrical cup and a second cylindrical cup whose external diameter is smaller than that of the first cylindrical cup,
in the step (I), the anode and the surface-to-be-plated being positioned to be separated from each other in the plating tank by a partition,
a flow of the plating solution being divided into a flow to the surface-to-be-plated and a flow to a neighbor of the anode, and
the plating solution having flowed into the anode chamber is caused to flow out of the plating tank via a plating solution flowing-out port which is a gap between side walls of the first cylindrical cup and the second cylindrical cup.

47. The method as set forth in claim 46, wherein in the step (I), the plating solution having flowed to the neighbor of the anode does not flow to the surface-to-be-plated.

48. The method as set forth in claim 46, wherein a portion which separates the anode from the substrate-to-be-plated and which includes the partition in the plating tank is partially or entirely made of a permeation member which, when immersed in the plating solution, allows ions in the plating solution to permeate the permeation member.

49. The method as set forth in claim 48, wherein the permeation member is a semipermeable membrane.

50. The method as set forth in claim 48, wherein the permeation member includes an ion exchange membrane.

51. The method as set forth in claim 46, wherein the partition has a thickness ranging from 50 to 200 μm.

52. The method as set forth in claim 46, wherein the partition includes a hydrocarbon cation exchange membrane.

53. The method as set forth in claim 46, wherein the step (I) includes the sub-steps of:

(i) supplying a plating solution stored in a plating solution supplying source to the plating tank;
(ii) filtering the plating solution supplied in the sub-step (i); and
(iii) supplying again the plating solution supplied to the plating tank to the plating solution supplying source.

54. The method as set forth in claim 46, wherein the plating solution includes a copper component and is conductive.

55. The method as set forth in claim 46, wherein the plating solution includes a copper component of not less than 14 g and not more than 40 g per 1 litter of the plating solution.

56. The method as set forth in claim 46, wherein the anode is a soluble anode made of high phosphorous copper.

57. The method as set forth in claim 46, wherein the substrate-to-be-plated is a semiconductor wafer.

58. The method as set forth in claim 46, further comprising the steps of:

(II) forming a seed layer on the surface-to-be-plated;
(III) applying photoresist on a surface of the seed layer formed in the step (II); and
(IV) forming a pattern by exposing and developing the photoresist,
the steps (II) to (IV) being performed before the step (I).

59. A semiconductor device, manufactured through a method as set forth in claim 46.

Patent History
Publication number: 20080105555
Type: Application
Filed: Dec 8, 2005
Publication Date: May 8, 2008
Inventor: Yoshihide Iwazaki (Kyoto)
Application Number: 11/792,812
Classifications
Current U.S. Class: Purifying Electrolyte (205/99); With Feeding And/or Withdrawal Means (204/275.1); Agitating Or Moving Electrolyte During Coating (205/148); Utilizing Specified Mask Material (205/135)
International Classification: C25D 5/02 (20060101); C25D 17/02 (20060101); C25D 5/08 (20060101); C25D 21/06 (20060101);