SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE
A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.
This application is a continuation application claiming priority to Ser. No. 11/276,132, filed Feb. 25, 2006.
BACKGROUND OF THE INVENTION1. Technical Field
The present invention relates to a structure and method to shield a trapped charge from devices within a semiconductor structure.
2. Related Art
Unwanted electrical charges within an electrical structure may cause devices within the electrical structure to malfunction. Therefore there is a need for protecting devices within an electrical structure from the affects of unwanted electrical charges.
SUMMARY OF THE INVENTIONThe present invention provides a semiconductor structure, comprising:
a first field effect transistor (FET) comprising a channel region formed from a portion of a silicon substrate, a source structure formed adjacent to said channel region, a drain structure formed adjacent to said channel region, a gate dielectric formed over said channel region, and a gate electrode formed over said gate dielectric, wherein a bottom surface of said gate electrode is in direct physical contact with said gate dielectric, wherein said channel region comprises a first corner device and a second corner device, wherein a top surface of said channel region is located within a first plane, and wherein said bottom surface of said gate electrode is located within a second plane;
a second FET; and
a shallow trench isolation (STI) structure located adjacent to said channel region, wherein said STI structure isolates said first FET from said second FET, wherein said STI structure comprises a dielectric liner formed in a trench within said silicon substrate, a conductive STI fill structure formed over said dielectric layer, and a dielectric cap layer formed over and in contact with a top surface of said conductive STI fill structure, wherein said top surface of said conductive STI fill structure is above said first plane by a first distance D1 and is above said second plane by a second distance D2 that is less than D1.
The present invention provides method for forming a semiconductor structure, comprising:
providing a silicon substrate;
forming, within said a silicon substrate, a shallow trench isolation (STI) structure comprising a dielectric liner formed in a trench within said silicon substrate, a conductive STI fill structure formed over said dielectric layer, and a dielectric cap layer formed over and in contact with a top surface of said conductive STI fill structure;
forming within said bulk silicon substrate, a first field effect transistor (FET) and a second FET, wherein said first FET comprises a channel region formed from a portion of said silicon substrate, a source structure formed adjacent to said channel region, a drain structure formed adjacent to said channel region, a gate dielectric formed over said channel region, and a gate electrode formed over said gate dielectric, wherein a bottom surface of said gate electrode is in direct physical contact with said gate dielectric, wherein said channel region comprises a first corner device and a second corner device, wherein a top surface of said channel region is located within a first plane, wherein said bottom surface of said gate electrode is located within a second plane, wherein said shallow trench isolation (STI) structure located adjacent to said channel region, wherein said STI structure isolates said first FET from said second FET, wherein said top surface of said conductive STI fill structure is above said first plane by a first distance D1 and is above said second plane by a second distance D2 that is less than D1.
The present invention advantageously provides a system and associated method for protecting devices within an electrical structure from the affects of unwanted electrical charges.
BRIEF DESCRIPTION OF THE DRAWINGS
Semiconductor structures (e.g., semiconductor structure 2) may be used (operated) in any type of circuitry. During operation of semiconductor structures over a period of time, an unwanted electrical charge buildup 26 (see
The STI structure 11 of
While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims
1. A semiconductor structure, comprising:
- a first field effect transistor (FET) comprising a channel region formed from a portion of a silicon substrate, a source structure formed adjacent to said channel region, a drain structure formed adjacent to said channel region, a gate dielectric formed over said channel region, and a gate electrode formed over said gate dielectric, wherein a bottom surface of said gate electrode is in direct physical contact with said gate dielectric, wherein said channel region comprises a first corner device and a second corner device, wherein a top surface of said channel region is located within a first plane, and wherein said bottom surface of said gate electrode is located within a second plane;
- a second FET; and
- a shallow trench isolation (STI) structure located adjacent to and in contact with said channel region, wherein said STI structure isolates said first FET from said second FET, wherein said STI structure comprises a dielectric liner formed in a trench within said silicon substrate, a conductive STI fill structure formed over said dielectric layer, and a dielectric cap layer formed over and in contact with a top surface of said conductive STI fill structure, wherein said top surface of said conductive STI fill structure is above said first plane by a first distance D1 and is above said second plane by a second distance D2 that is less than D1, and wherein said gate dielectric is formed over and in contact with said dielectric cap layer of said STI structure.
2. The semiconductor structure of claim 1, wherein said STI structure is adapted to shield said first corner device and said second corner device from a trapped electrical charge build up within said dielectric cap layer, and wherein said electrical charge build up within said dielectric cap layer is generated during operation of said first FET and said second FET over a period of time.
3. The semiconductor structure of claim 1, wherein said conductive STI fill structure comprises doped polysilicon.
4. The semiconductor structure of claim 1, wherein each of said dielectric liner and said dielectric cap layer comprise silicon dioxide.
5. The semiconductor structure of claim 1, wherein said first distance D1 is configured to prevent a trapped electrical charge build up within said dielectric cap layer from electrically damaging said first corner device and said second corner device.
6. The semiconductor structure of claim 1, wherein said dielectric liner comprises a thickness T configured to prevent trapped electrical charge build up within said dielectric liner from electrically damaging said first corner device and said second corner device.
7. The semiconductor structure of claim 6, wherein said thickness T is in a range of about 2 nanometers to about 20 nanometers.
8. The semiconductor structure of claim 1, wherein said dielectric liner comprises a thickness T, and wherein said distance D1 is in a range of about 1.5*T to about 4*T.
9. The semiconductor structure of claim 8, wherein said distance D1 is in a range of about 5 nanometers to about 80 nanometers.
10. The semiconductor structure of claim 1, wherein a bottom surface of said conductive STI fill structure is electrically connected to said silicon substrate.
11. The semiconductor structure of claim 1, wherein said gate electrode is formed over said dielectric cap layer of said STI structure.
12. The semiconductor structure of claim 1, wherein said dielectric liner is formed in said trench such that said conductive STI fill structure is not in contact with said silicon substrate.
13. The semiconductor structure of claim 1, wherein said second FET comprises a second channel region formed from a second portion of said silicon substrate, and wherein said shallow trench isolation (STI) structure is located adjacent to and in contact with said second channel region.
Type: Application
Filed: Jan 30, 2008
Publication Date: May 22, 2008
Inventors: Ethan Cannon (Essex Junction, VT), Shunhua Chang (South Burlington, VT), Toshiharu Furukawa (Essex Junction, VT), David Horak (Essex Junction, VT), Charles Koburger (Delmar, NY)
Application Number: 12/022,202
International Classification: H01L 27/088 (20060101);