Chip-Stacked Package Structure and Applications Thereof

Abstract

A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.

Description

RELATED APPLICATIONS

The present application is based on, and claims priority from, Taiwan Application Serial Number 96115395, filed at Apr. 30, 2007, the disclosure of which is hereby incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention relates to a semiconductor package structure and the applications thereof, and more particularly relates to a chip stacked package structure and the applications thereof.

BACKGROUND OF THE INVENTION

Nowadays, electronic devices are developed to provide increased functionality. Single chips with multiple integrated functions are therefore required to ensure and the chips can fit into electronic devices of limited. To integrate more functions in a single package, the package structure of the chip has evolved from a two-dimensions to three-dimensions and from a single-die package structure to a multiple-die package structure.

A system-in-package is a chip-stacked package structure with several chips with multiple functions integrated into a package structure, wherein these chips are stacked on a substrate by surface mount technology (SMT), so as to improve the packing process and to decrease the chip size. Whereby the system-in-package has the advantage of a small size, high operating frequency, high speed and low cost.

FIG. 4 illustrates a cross sectional view of a conventional chip stacked structure 400. The chip-stacked package structure 400 comprises a substrate 410, a first chip 420, a second chip 430 and a plurality of bonding wires, such as bonding wires 440 and 450. The first chip 420 set on the substrate 410 is electrically connected to the substrate 410 by the bonding wire 440, and the second chip 430 stacked on the first chip 420 is electrically connected to the substrate 410 by the bonding wire 450.

To accommodate the arrangement of the bonding wire (the bonding wire 440) connected on the lower chip (the first chip 420); the size of the upper chip (the second chip 430 stacked on the first chip 420) must be smaller than that of the lower chip in the conventional design. Thus the design flexibility and the number of chips stacked in a single package are limited. Furthermore, it is necessary to extend the bonding wires in connecting the chips of small size with the substrate, whereby the radian of the bonding wires may be increased. Consequently, when a subsequent stamping process is conducted, the bonding wires may be wrenched off so as to make the electrical connection short and to decrease its manufacture yield.

To resolve the aforementioned problems, an alternative conventional chip stacked structure is provided. FIG. 5 illustrates a cross view cross-section view of an alternative conventional chip stacked structure 500. The chip-stacked package structure 500 comprises a substrate 510, a first chip 520, a second chip 530, a plurality of bonding wires, such as bonding wires 540 and 550, and a dummy chip 560 set between the first chip 520 and the second chip 530. The first chip 520 set on the substrate 510 has a bonding pad 570 electrically connected to the substrate 510 by the bonding wire 540, and the dummy chip 560 is stacked on the first chip 520. The second chip 530 stacked on the dummy chip 560 has a bonding pad 580 electrically connected to the substrate 510 by the bonding wire 550. Since the size of the dummy chip is smaller than the size of the first chip 520 and the second chip 530, there provides enough wiring space between the lower chip (the first chip 520) and the upper chip (the second chip 530) for the bonding wire 540 to electrically bond on the lower chip. Accordingly, in this case the size of the upper chip (the second chip 530) is no longer limited.

However, using the dummy can increase the thickness of the pancake structure and may conflict with the trend of package size minimization. Therefore, it is desirable to provide an advanced chip-stacked package structure designed to improve the process yield so as to lower the manufacturing costs.

SUMMARY OF THE INVENTION

One aspect of the present invention is to provide a chip-stacked package structure. The chip-stacked package structure comprises a substrate, a first chip, a circuit board, a second chip and a molding compound. The substrate has a first surface and an opposite second surface, wherein the first chip is set on the first surface of the substrate. The first chip having a first active surface and a first rear surface opposite to the first active face, wherein the first active surface facing the first surface of the substrate is electrically connected to the substrate by a flip chip bonding process. The circuit board set on the first rear surface of the first chip comprises a dielectric layer formed on the first rear surface and a patterned circuit layer formed on the dielectric layer, wherein the patterned circuit layer is electrically connected to the substrate via at least one bonding wire. The second chip set on the patterned circuit layer has a second active surface and at least one second bonding pad set on the second active surface, wherein the second bonding pad is electrically connected to the patterned circuit layer so as to electrically connected to the substrate via the bonding wire. The molding compound encapsulates the substrate, the first chip, the circuit board and the second chip. The chip-stacked package structure further comprises a plurality of external connecting bumps set on the second surface of the substrate used to connect the substrate with at least one external electronic device, wherein the external connecting bumps may be made of solder.

Another aspect of the present invention is to provide a method for manufacturing a chip-stacked package structure. The method comprises steps as following: first a substrate having a first surface and a second surface opposite thereof is provided. A first chip having a first active surface and a first rear surface opposite to the first active surface is then set on the substrate, and the first active surface facing the first surface of the substrate is electrically connected to the substrate by a flip chip bonding process. Subsequently, a circuit board is formed on the first rear surface of the first chip, wherein the circuit board comprises a dielectric layer formed on the first rear surface and a patterned circuit layer formed on the dielectric layer. The patterned circuit layer comprises of at least one finger connected to at least one bonding pad set on the second chip that is subsequently stacked on the patterned circuit layer. And a bonding wire is then formed to electrically connect the substrate with the patterned circuit layer. Subsequently, the second chip is stacked on the patterned circuit layer and the second bonding pad is electrically connected to the finger of the patterned circuit layer and then to the substrate via the bonding wire that electrically connects the patterned circuit layer with the substrate. A molding compound then encapsulates the substrate, the first chip, the circuit board and the second chip. A plurality of external connecting bumps, such as a plurality of solder bumps, are then formed on the second surface of the substrate used to connect the substrate with at least one external electronic device.

In accordance with above descriptions, the features of the present invention provide a patterned circuit layer set on a rear surface of a lower chip in a chip-stacked package structure, wherein the patterned circuit layer has at least one finger electrically connected to at least one bonding pad set on the upper chip that is stacked thereon, whereby the wiring arrangements of the second chip constituted by the bonding pad can be redistributed by the finger of the patterned circuit layer to shift the bonding area of the bonding pad towards the edge of the upper chip for a bonding wire to electrically connect the bonding pad with the substrate. Accordingly, it is not necessary to extend the length and the radian of the bonding wire when connecting the upper chips with the substrate or to reduce the size of the upper chip for involving more chips in a single package, so as to solve the prior problems in the art. Also, since the lengths of wires are reduced, the disadvantage of wire sweep also can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 illustrates a cross section view of a chip-stacked package structure 100 in accordance with a first preferred embodiment of the present invention.

FIG. 2 illustrates a cross section view of a chip-stacked package structure 200 in accordance with a second preferred embodiment of the present invention.

FIG. 3 illustrates a cross section view of a chip-stacked package structure 300 in accordance with a third preferred embodiment of the present invention.

FIG. 4 illustrates a cross section view of a conventional chip stacked structure 400.

FIG. 5 illustrates a cross view cross-section view of an alternative conventional chip stacked structure 500.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following preferred embodiments of chip-stacked package structures.

FIG. 1 illustrates a cross section view of a chip-stacked package structure 100 in accordance with a first preferred embodiment of the present invention.

The chip-stacked package structure 100 comprises a substrate 101, a first chip 102, a circuit board 123, a second chip 107 and a molding compound 120.

The chip-stacked package structure 100 is formed by the following steps: First, the substrate 101 having a first surface 116 and a second surface 117 opposite to the first surface 116 is provided. In some preferred embodiments of the present invention, the substrate 101 can be a lead frame, a printed circuit board or a die carrier. In the present embodiment, the substrate 101 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board.

The first chip 102 having a first active surface 103 facing the first surface 116 of the substrate 101 and a first rear surface 104 opposite to the first active face 103 is then mounted on the first surface 116 by a flip chip bonding process to electrically connect the first active surface 103 to the first surface 116 of the substrate 101. In the present embodiment, the first active surface 103 has a plurality of first bonding pads 115 electrically connected to the substrate 101 via a plurality of bumps 113. After the first chip 102 is stacked on the first surface 116 of the substrate 101, an underfill material 114 is used to encapsulate the bumps 113 and to fix the first chip 102 over the first surface 116 of the substrate 101.

Subsequently, the circuit board 123 is formed on the first rear surface 104 of the first chip 102, wherein the circuit board 123 comprises a dielectric layer 120 set overt the first rear surface 104 and a patterned circuit layer 105 formed on the dielectric layer 120, and the patterned circuit layer 105 is electrically connected to the substrate 101 by a boding wire 106. In the embodiments of the present invention, the patterned circuit layer 105 having a plurality of fingers, such as fingers 105a and 105b, is a redistribution layer. One end of each finger (for example 105a) is electrically connected to one of the second bonding pads 109 set on the second chip 107 that is subsequently stacked on the patterned circuit layer 105, and the other end of the finger extends towards another area of the first rear surface 104 apart from the second bonding pads 109. For example, the other end of the finger extends towards the edge of the first rear surface 104.

Then, the second chip 107 is stacked on the patterned circuit layer 105 by a flip chip process, wherein the second chip 107 has a second active surface 108 having a plurality of second bonding pads 109 set thereon. Each of the second bonding pads 109 is electrically connected to one of the fingers (105a or 105b) of the pattered circuit layer 105. In the embodiments of the present invention, the pattern contributed by the fingers (105a or 105b) of the pattered circuit layer 105 can altered in corresponding to the various arrangements of the boding pads 109 set on different types of the second chip 107.

After that, the molding compound 120 is then used to encapsulate the substrate 101, the first chip 102, the circuit board 123 and the second chip 107. A plurality of external connecting bumps 111, such as a plurality of solder bumps, are then formed on the second surface 117 of the substrate 101 used to connect the substrate 101 with at least one external electronic device (not shown).

Since one of the boding pads 109 of the second chip 107 is electrically connected to one of the fingers (such as finger 105a or finger 105b) of the pattered circuit layer 105, when the second chip 107 is stacked on the first chip 102 with a size identical to the size of the first chip 102, the fingers of the patterned circuit layer 105 can redistribute the arrangement of the second bonding pads 109 of the second chip 107, so as to shift the bonding area of the bonding pads 109 towards the edge of the second chip 107 for the bonding wire 106 to electrically connect the bonding pads 109 with the substrate 101. For another embodiment of the present invention not drawing in the specification, the first rear surface 104 of the first chip 102 and the second active surface 108 of the second chip 107 can have different sizes.

FIG. 2 illustrates a cross section view of a chip-stacked package structure 200 in accordance with a second preferred embodiment of the present invention.

The chip-stacked package structure 200 comprises a substrate 201, a first chip 202, a circuit board 223, a second chip 207 and a molding compound 220.

The chip-stacked package structure 200 is formed by the following steps: First, the substrate 201 having a first surface 218 and a second surface 219 opposite to the first surface 218 is provided. In some preferred embodiments of the present invention, the substrate 201 can be a lead frame, a printed circuit board or a die carrier. In the present embodiment, the substrate 201 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board.

Next a through hole 217 is formed to penetrate the substrate 201, and the first chip 202 having a first active surface 203 facing the first surface 218 of the substrate 201 and a first rear surface 204 opposite to the first active face 203 is then mounted on the first surface 218 by a flip chip bonding process to electrically connect the first active surface 203 to the first surface 218 of the substrate 201. In the present embodiment, the first active surface 203 has a plurality of first bonding pads 215 electrically connected to the substrate 201 via a plurality of bumps 213. After the first chip 202 is stacked on the first surface 218 of the substrate 201, an underfill material 214 is used to encapsulate the bumps 213 and to fix the first chip 202 over the first surface 218 of the substrate 201.

Since a portion of the first active surface 203 can be exposed by the through hole 217 penetrates the substrate 201. In some preferred embodiment, a heat sink 216 can be extend outward the through hole 217 from the exposed portion of the first active surface 203 to enhance the heat distribution of the chip-stacked package structure 200.

Subsequently, the circuit board 223 is formed on the first rear surface 204 of the first chip 202, wherein the circuit board 223 comprises a dielectric layer 220 set over the first rear surface 204 and a patterned circuit layer 205 formed on the dielectric layer 220, and the patterned circuit layer 205 is electrically connected to the substrate 201 by a boding wire 206. In the embodiments of the present invention, the patterned circuit layer 205 that has a plurality of fingers, such as fingers 205a and 205b, is a redistribution layer. One end of each finger (for example finger 205a) is used to electrically connected to one of a second bonding pad 209 set the second chip 207 that is subsequently stacked on the patterned circuit layer 205, and the other end of the finger 205a extends towards another area of the first rear surface 204 apart from the second bonding pad 209. For example, the other end of the finger 205a extends towards the edge of the first rear surface 204.

Then, the second chip 207 is stacked on the patterned circuit layer 205 by a flip chip process, wherein the second chip 207 has a second active surface 208 having a plurality of second bonding pads 209 set thereon. Each of the second bonding pads 209 is electrically connected to one of the fingers (205a or 205b) of the pattered circuit layer 205. In the embodiments of the present invention, the pattern contributed by the fingers (205a or 205b) of the pattered circuit layer 205 can be altered to correspond to the various arrangements of the boding pads 209 set on different types of the second chip 207.

After that, a molding compound 220 is then used to encapsulate the substrate 201, the first chip 202, the circuit board 223 and the second chip 207. A plurality of external connecting bumps 211, such as a plurality of solder bumps, are then formed on the second surface 219 of the substrate 201 used to connect the substrate 201 with at least one external electronic device (not shown).

Since one of the boding pads 209 of the second chip 207 is electrically connected to one of the fingers (such as finger 205a or finger 205b) of the pattered circuit layer 205, when the second chip 207 is stacked on the first chip 202 with a size identical to the size of the first chip 102, the fingers of the patterned circuit layer 205 can redistribute the arrangement of the second bonding pads 209 of the second chip 207, so as to shift the bonding area of the bonding pads 209 towards the edge of the second chip 207 for the bonding wire 206 to electrically connect the bonding pads 209 with the substrate 201. For another embodiment of the present invention not drawing in the specification, the first rear surface 204 of the first chip 202 and the second active surface 208 of the second chip 207 can have different sizes.

FIG. 3 illustrates a cross section view of a chip-stacked package structure 300 in accordance with a third preferred embodiment of the present invention.

The chip-stacked package structure 300 comprises a substrate 301, a first chip 302, a circuit board 323, a second chip 307 and a molding compound 320.

The chip-stacked package structure 300 is formed by the following steps: First, the substrate 301 having a first surface 316 and a second surface 319 opposite to the first surface 316 is provided. In some preferred embodiments of the present invention, the substrate 301 can be a lead frame, a printed circuit board or a die carrier. In the present embodiment, the substrate 301 is a printed circuit board made of FR4 or BT epoxy, or made of the materials that constitute a flexible printed circuit board.

Next a through hole 317 is formed to penetrate the substrate 301, and the first chip 302 having a first active surface 303 facing the first surface 316 of the substrate 301 and a first rear surface 304 opposite to the first active face 303 is then mounted on the first surface 316 by a flip chip bonding process to electrically connect the first active surface 303 to the substrate 301.

In the present embodiment, a portion of the first active surface 303 mounted on the first surface 316 of the substrate 301 is exposed by the through hole 317 penetrating through the substrate 301, and the first chip 302 has a plurality of first bonding pads 315 set on the exposure portion of the first active surface 303 electrically connected to the substrate 301 via a plurality of bonding wires 318 passing through the through hole 317.

Subsequently, the circuit board 323 is formed on the first rear surface 304 of the first chip 302, wherein the circuit board 323 comprises a dielectric layer 320 set overt the first rear surface 304 and a patterned circuit layer 305 formed on the dielectric layer 320, and the patterned circuit layer 305 is electrically connected to the substrate 301 by a boding wire 306. In the embodiments of the present invention, the patterned circuit layer 305 having a plurality of fingers, such as fingers 305a and 305b, is a redistribution layer. One end of each finger (for example finger 305a) is electrically connected to one of a second bonding pad 309 set the second chip 307 that is subsequently stacked on the patterned circuit layer 305, and the other end of the finger 305a extends towards another area of the first rear surface 304 apart from the second bonding pad 309. For example, the other end of the finger 305a extends towards the edge of the first rear surface 304.

Then, the second chip 307 is stacked on the patterned circuit layer 305 by a flip chip process, wherein the second chip 307 has a second active surface 308 having a plurality of second bonding pads 309 set thereon. Each of the second bonding pads 309 is electrically connected to one of the fingers (305a or 305b) of the pattered circuit layer 305. In the embodiments of the present invention, the pattern contributed by the fingers (305a or 305b) of the pattered circuit layer 305 can altered in corresponding to the various arrangements of the boding pads 309 set on different types of the second chip 307.

After that, a molding compound 320 is then used to encapsulate the substrate 301, the first chip 302, the circuit board 323 and the second chip 307. A plurality of external connecting bumps 311, such as a plurality of solder bumps, are then formed on the second surface 319 of the substrate 301 used to connect the substrate 301 with at least one external electronic device (not shown).

Since one of the boding pads 309 of the second chip 307 are electrically connected to one of the fingers (such as finger 305a or finger 305b) of the pattered circuit layer 305, when the second chip 307 is stacked on the first chip 302 with a size identical to the size of the first chip 302, the fingers of the patterned circuit layer 305 can redistribute the arrangement of the second bonding pads 309 of the second chip 307, so as to shift the bonding area of the bonding pads 309 towards the edge of the second chip 307 for the bonding wire 306 to electrically connect the bonding pads 209 with the substrate 301. For another embodiment of the present invention not drawing in the specification, the first rear surface 304 of the first chip 302 and the second active surface 308 of the second chip 307 can have different sizes.

In accordance with above descriptions, the features of the present invention are providing a patterned circuit layer set on a rear surface of a lower chip in a chip-stacked package structure, wherein the patterned circuit layer has at least one finger electrically connected to at least one bonding pad set on the upper chip that is stacked thereon, whereby the wiring arrangements of the second chip constituted by the bonding pad can be redistributed by the finger of the patterned circuit layer so to shift the bonding area of the bonding pad towards the edge of the upper chip for a bonding wire to electrically connect the bonding pad with the substrate. Accordingly, it is not necessary to extend the length and the radian of the bonding wire in connecting the upper chips with the substrate or to reduce the size of the upper chip for involving more chips in a single package, so as to solve the prior problems in the art. Also, since the lengths of wires are reduced, the disadvantage of wire sweep also can be improved.

As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.

Claims

1. A chip-stacked package structure, comprising:

a substrate having a first surface and a second surface opposite to the first surface;

a first chip set on the first surface of the substrate, having a first active surface, a first rear surface, and at least one first bonding pad, wherein the first active surface faces to the substrate, and the first bonding pad is electrically connected to the substrate;

a circuit board set on the first rear surface comprising: a dielectric layer set on the first rear surface; and a patterned circuit layer formed on the dielectric layer and electrically connected to the substrate via at least one bonding wire;

a second chip set on the patterned circuit layer having a second active surface and at least one second bonding pad set on the second active surface, and the second bonding pad is electrically connected to the patterned circuit layer, and electrically connected to the substrate via the bonding wire; and

a molding compound encapsulates the first chip, the substrate, the circuit board and the second chip.

2. The chip-stacked package structure in accordance with claim 1, further comprising a plurality of external connecting bumps set on the second surface of the substrate.

3. The chip-stacked package structure in accordance with claim 1, wherein the first active surface has a plurality of first bonding pads electrically connected to the substrate via a plurality of bumps.

4. The chip-stacked package structure in accordance with claim 2, further comprising underfill materials used to encapsulate the bumps.

5. The chip-stacked package structure in accordance with claim 2, wherein the substrate has a through hole used to expose a portion of the first active surface.

6. The chip-stacked package structure in accordance with claim 5, wherein the first active surface has a plurality of first bonding pads electrically connected to the substrate via a plurality of bumps.

7. The chip-stacked package structure in accordance with claim 6, further comprising underfill materials used to encapsulate the bumps.

8. The chip-stacked package structure in accordance with claim 7, further comprising a heat sink extending outward the through hole form the exposed portion of the first active surface.

9. The chip-stacked package structure in accordance with claim 5, wherein the first active surface has a plurality of first bonding pads set thereon and electrically connected to the substrate via a plurality of bonding wires passing through the through hole.

10. The chip-stacked package structure in accordance with claim 1, wherein the patterned circuit layer is a redistribution layer.

11. The chip-stacked package structure in accordance with claim 1, wherein the patterned circuit layer comprises a plurality of fingers, and one end of each finger is used to electrically connect to one of the second bonding pad, and the other end of the corresponding finger extends towards the edge of the first rear surface.

12. The chip-stacked package structure in accordance with claim 1, wherein the first rear surface and the second active surface have an identical size.

13. The chip-stacked package structure in accordance with claim 1, wherein the first rear surface and the second active surface have different size.

14. The chip-stacked package structure in accordance with claim 1, wherein the second bonding pad is electrically connected to the patterned circuit layer by at least one bump or by at lest one solder.

15. A method for manufacturing a chip-stacked package structure, comprising:

providing a substrate that has a first surface and a second surface opposite to the first surface;

setting a first chip on the first surface of the substrate, to make a first active surface of the first chip that facing and electrically connecting to the substantiate;

forming a circuit board set on a first rear surface of the first chip opposite to the first active surface, wherein the circuit board comprises a dielectric layer set on the first rear surface and a patterned circuit layer formed on the dielectric layer, and the patterned circuit layer has at least one finger electrically connected to at least one second bonding pad set on a second chip that is subsequently stacked thereon;

forming at least one bonding wire to electrically connect the patterned circuit layer with the substrate;

setting the second chip on the patterned circuit layer to make the second bonding pad electrically connected to the finger and electrically connected to the substrate via the bonding wire; and

using a molding compound to encapsulates the first chip, the substrate, the circuit board and the second chip.

16. The method for manufacturing the chip-stacked package structure in accordance with claim 15, wherein the step of providing the substrate further comprises a step of providing a plurality of external connecting bumps set on the second surface of the substrate.

17. The method for manufacturing the chip-stacked package structure in accordance with claim 16, wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:

forming a plurality of bumps on the first active surface electrically connected to the substrate; and

using underfill materials to encapsulate the bumps.

18. The method for manufacturing the chip-stacked package structure in accordance with claim 15, wherein the step of providing the substrate further comprises a step of forming a though hole penetrating through the substrate to expose a portion of the first active surface.

19. The method for manufacturing the chip-stacked package structure in accordance with claim 18, wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:

forming a plurality of bumps on the first active surface electrically connected to the substrate; and

using underfill materials to encapsulate the bumps.

20. The method for manufacturing the chip-stacked package structure in accordance with claim 19, further comprising setting a heat sink extending outward the through hole from the exposed portion of the first active surface.

21. The method for manufacturing the chip-stacked package structure in accordance with claim 18, wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:

setting the first chip on the substrate to expose a plurality of first bonding pads that are set on the first active surface via the through hole; and

forming at least one bonding wire passing though the though hole to electrically connect the first bonding pads with the substrate.