CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE
A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. Fast program and erase speeds with memory window as great as 7 V are achieved.
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The benefit of U.S. Provisional Patent Application No. 60/955,391, filed on 13 Aug. 2007, is hereby claimed.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to scalable charge trapping memory technology adaptable for high speed erase and program operations.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that does not cause cell-to-cell interference like that encountered with floating gate technology, and is expected to be applied for higher density flash memory.
The typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a stack of dielectric material including a tunnel dielectric layer, the charge storage layer, and a blocking dielectric layer. According to the early conventional designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O), and the gate comprises polysilicon (S). The SONOS device is programmed by electron tunneling using one of a number of well-known biasing technologies, and erased by hole tunneling or electron de-trapping. In order to achieve practical operational speeds for the erase operation, the tunneling dielectric layer must be quite thin (less than 30 Å). However at that thickness, the endurance and charge retention characteristics of the memory cell are poor relative to traditional floating gate technology. Also, with relatively thick tunneling dielectric layers, the electric field required for the erase operation also cause electron injection from the gate through the blocking dielectric layer. This electron injection causes an erase saturation condition in which the charge level in the charge trapping device converges on an equilibrium level. See, U.S. Pat. No. 7,075,828, entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”, invented by Lue et al. However, if the erase saturation level is too high, the cell cannot be erased at all, or the threshold margin between the programmed and erased states becomes too small for many applications.
On one hand, technology has been investigated to improve the ability of the blocking dielectric layer to reduce electron injection from the gate for the high electric fields needed for erase. See, U.S. Pat. No. 6,912,163, entitled “Memory Device Having High Work Function Gate and Method of Erasing Same,” Invented by Zheng et al., issued 28 Jun. 2005; and U.S. Pat. No. 7,164,603, entitled “Operation Scheme with High Work Function Gate and Charge Balancing for Charge Trapping Non-Volatile Memory”, invented by Shih et al., Shin et al., “A Highly Reliable SONOS-type NAND Flash Memory Cell with Al2O3 or Top Oxide,” IEDM, 2003 (MANOS); and Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for a Multi-Gigabit Flash EEPROMs”, IEEE 2005. In the just-cited references, the second Shin et al. article describes a SONOS type memory cell in which the gate is implemented using tantalum nitride and the blocking dielectric layer is implemented using aluminum oxide (referred to as the TANOS device), which maintains a relatively thick tunneling dielectric layer at about 4 nm. The relatively high work function of tantalum nitride inhibits electron injection through the gate, and the high dielectric constant of aluminum oxide reduces the magnitude of the electric field through the blocking dielectric layer relative to the electric field for the tunneling dielectric layer. Shin et al. report a trade-off between the breakdown voltage of the memory cell, the thickness of the aluminum oxide layer and the thickness of the tunneling dielectric layer. With a 4 nm thick silicon dioxide tunneling dielectric in a TANOS device, relatively high erase voltages are proposed in order to achieve erase speeds. An increase in erase speeds would require increasing the voltages applied or decreasing the thickness of the tunneling dielectric layer. Increasing the voltage applied for erase is limited by the breakdown voltage. Decreasing the thickness of the tunneling dielectric layer is limited by issues of charge retention and erase saturation, as mentioned above.
On the other hand, technology has been investigated to improve the performance of the tunneling dielectric layer for erase at lower electric fields. See, U.S. Patent Application Publication No. US 2006/0198189 A1, “Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operating Cells and Arrays,” Invented by Lue et al., publication date Sep. 7, 2006 (describing a “BE-SONOS device”); Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability”, IEEE, December 2005; Wang et al., “Reliability and Processing Effects of the Bandgap Engineered SONOS (BE-SONOS) Flash Memory”, IEEE, May 2007. See also, U.S. Patent Application Publication No. 2006/0261401 A1, entitled “Novel Low Power Non-Volatile Memory and Gate Stack”, by Bhattacharyya, published 23 Nov. 2006.
BE-SONOS technology has been proven to provide excellent performance, overcoming many of the erase speed, endurance and charge retention issues of prior art SONOS type memory. However, the problem of the erase saturation continues to limit operational parameters of the device. Furthermore, as the device sizes shrink, it is expected that erase saturation problems will intensify. Accordingly, is desirable to provide a new memory technology which overcomes the erase saturation issues of prior art technologies, and that can be applied in very small memory devices.
SUMMARY OF THE INVENTIONA band gap engineered, charge trapping memory cell is described including a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant κ, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. The engineered tunneling dielectric includes a combination of materials having negligible charge trapping efficiency, and band offset characteristics. The band offset characteristics include a relatively large hole tunneling barrier height in a thin region at the interface with the semiconductor body, and an increase in valence band energy level so that the hole tunneling barrier height at a first offset less than 2 nm for example from the channel surface, from the interface is relatively low. The band offset characteristics also include an increase in conduction band energy by providing a thin layer of relatively high electron tunneling barrier height at a second offset more than 2 nm from the channel surface, separating the material with a relatively lower hole tunneling barrier height from the charge trapping layer. Very fast erase speed is obtained using the memory cell described herein, without erase saturation, providing a memory window and operating speed much greater than possible in prior art technologies.
The valence band energy level at the first offset is such that an electric field sufficient to induce hole tunneling through the thin region between the interface with the semiconductor body and the offset, is also sufficient to raise the valence band energy level after the offset to a level that effectively eliminates the hole tunneling barrier in the engineered tunneling dielectric after the offset. This structure enables electric field assisted hole tunneling at high speeds while effectively preventing charge leakage through the engineered tunneling dielectric in the absence of electric fields or in the presence of smaller electric fields induced for the purpose of other operations, such as reading data from the cell or programming adjacent cells.
In a representative device, the engineered tunneling dielectric layer consists of an ultrathin silicon oxide layer O1 (e.g. <=15 Å), an ultrathin silicon nitride layer N1 (e.g. <=30 Å) and an ultrathin silicon oxide layer O2 (e.g. <=30 Å), which results in an increase in the valence band energy level of about 2.6 eV at an offset 15 Å or less, from the interface with the semiconductor body. The O2 layer separates the N1 layer from the charge trapping layer, at a second offset (e.g. about 35 to 45 A from the interface), by a region of lower valence band energy level (higher hole tunneling barrier). The electric field sufficient to induce hole tunneling between the interface and the first offset also raises the valence band energy level after the second offset to a level that effectively eliminates the hole tunneling barrier, because the second offset is at a greater distance from the interface. Therefore, the O2 layer does not significantly interfere with the electric field assisted hole tunneling, while improving the ability of the engineered tunneling dielectric to block leakage during low fields.
The blocking dielectric structure in a representative memory device, consists of aluminum oxide which has a dielectric constant (K about 7 or 8) about twice that of silicon dioxide. Therefore, the electric field intensity in the blocking dielectric structure is relatively low compared to that in the tunneling dielectric layer.
The present technology combines techniques for reducing the electric field in the blocking dielectric layer relative to the tunneling dielectric layer, with techniques for reducing the magnitude of the electric field required for erase to achieve high speed erase operations without saturation, enabling a large memory window compared to prior devices. Also, charge retention and endurance characteristics of the memory cell are very good.
A charge trapping memory is described based on this technology that includes an array of memory cells. The memory cells include a semiconductor body having a channel with a channel surface and source and drain terminals adjacent the channel. The tunneling dielectric layer lies on the channel surface, and is characterized by negligible charge trapping efficiency and band offset technology. A charge trapping dielectric layer lies on the tunneling dielectric layer. A blocking dielectric layer lies on the charge trapping layer. The blocking dielectric layer comprises a material having a dielectric constant κ greater than 3.9, and preferably comprises aluminum oxide or other material having a dielectric constant κ of about 7 or higher. The gate lies on the blocking dielectric layer. The gate comprises a metal or other conductive material on the blocking dielectric layer. Embodiments of the technology can employ a material for the gate such as platinum, which has a relatively high work function, i.e. greater than 4.5 eV.
Circuitry is coupled to the array of memory cells to apply bias voltages to selected memory cells for read, program and erase operations.
In the technology described herein, the bias voltages across the gate and substrate of the device are 20 V or less, well below breakdown voltages for erase operations, and demonstrate threshold shifts supporting a memory window of as much as 7 V or more. In addition, for the device described herein, the bias voltages applied during erase operations induce an electric field less than 14 MV/cm across the dielectric tunneling layer, and accomplish a threshold shift of greater than 5 V in less than 10 ms, without erase saturation. Circuitry can be implemented in combination with the charge trapping memory cell described herein to accomplish a negative threshold shift of greater than 5 V in less than 1 ms without erase saturation. Erase speeds of less than 10 ms can be accomplished using bias voltages less than 15 V, enabling the implementation of very small scale devices that have relatively low breakdown voltages.
The bias voltages applied during program operations likewise are capable of very fast program operations by electron tunneling through the tunneling dielectric layer, accomplishing in some embodiments a positive threshold shift of greater than 5 V, and as much as 7 V, in less than 1 ms, and in other embodiments in less than 0.1 ms.
The memory cell described herein can provide flash technology with a relatively large memory window (greater than 7 V) with excellent data retention. Also, the memory cell described herein should be scalable to 50 nm manufacturing nodes, to 40 nm nodes and below.
Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description in the claims which follow.
A detailed description of embodiments of the present invention is provided with reference to the
A gate 18 in this embodiment comprises platinum having a work function of about 8 electron volts eV. Preferred embodiments employ metals or metal compounds for the gate 18, such as platinum, tantalum nitride, aluminum or other metal or metal compound gate materials. It is preferable to use materials having work functions higher than 4.5 eV. A variety of high work function materials suitable for use as a gate terminal are described in U.S. Pat. No. 6,912,163, referred to above. Such materials are typically deposited using sputtering and physical vapor deposition technologies, and can be patterned using reactive ion etching.
Embodiments of the memory cell can also employ other metals, such as aluminum, having a work function of about 4.3 eV, as explained in more detail below.
In the embodiment illustrated in
A layer 14, referred to as a band offset layer, of silicon nitride lies on the first layer 13 of silicon oxide formed for example using low-pressure chemical vapor deposition LPCVD, using for example dichlorosilane DCS and NH3 precursors at 680 degrees C. In alternative processes, the band offset layer comprises silicon oxynitride, made using a similar process with an N2O precursor. The thickness of the layer 14 of silicon nitride is within the range of about 10 Å to 30 Å, and preferably 25 Å or less.
A second layer 15 of silicon dioxide, referred to as an isolation layer, lies on the layer 14 of silicon nitride formed for example using LPCVD high temperature oxide HTO deposition. The thickness of the second layer 15 of silicon dioxide is less than 30 Å, and preferably 25 Å or less. The structure of the dielectric tunneling layer is described in more detail below with reference to
A charge trapping layer 16 in this embodiment comprises silicon nitride having a thickness within the range of about 50 Å to 100 Å, including for example about 70 Å in this embodiment formed for example using LPCVD. Other charge trapping materials and structures may be employed, including for example silicon oxynitride (SixOyNz), silicon-rich nitride, silicon-rich oxide, trapping layers including embedded nano-particles and so on.
The blocking dielectric layer 17 in this embodiment comprises aluminum oxide (Al2O3), having a dielectric constant κ of about 8 or more. The layer 17 of aluminum oxide is greater than the thickness of the layer 17 of silicon nitride, including for example at least twice as thick. In illustrated example, the layer 17 of aluminum oxide is within the range of about 50 Å to 150 Å, and for example about 150 Å in the embodiments described herein, formed by atomic vapor deposition AVD with a post deposition rapid thermal anneal at 900° C. for about 60 seconds to strengthen the film. In other embodiments, high κ dielectric material such as hafnium oxide (HfO2) having a κ of about 10, titanium oxide (TiO2) having a κ of about 60, praseodymium oxide (Pr2O3) having a κ of about 30 may be used. Oxides of zirconium Zr and lanthanum La may used as well. In some embodiments, oxides of more than one metal may be used, including for example, oxides of hafnium and aluminum, oxides or zirconium and aluminum, and oxides of hafnium, aluminum and zirconium.
In a representative embodiment, the first layer 13 is 13 Å of silicon dioxide; the band offset layer 14 is 20 Å of silicon nitride; the isolation layer 15 is 25 Å of silicon dioxide; the charge trapping layer 16 is 70 Å of silicon nitride; and the blocking dielectric layer 17 is 150 Å of aluminum oxide.
The isolation layer 33 isolates the offset layer 32 from a charge trapping layer 34. This increases the effective blocking capability during low electric field for both electrons and holes, improving charge retention.
The offset layer 32 in this embodiment must be thin enough that it has negligible charge trapping efficiency. Also, the offset layer is a dielectric, and not conductive. Thus, for an embodiment employing silicon nitride, the offset layer should be less than 30 Å thick, and more preferably about 25 Å or less.
The hole tunneling layer 31, for an embodiment employing silicon dioxide, should be less than 20 Å thick, and more preferably less than 15 Å thick. For example, in a preferred embodiment, the hole tunneling layer 31 is silicon dioxide about 13 Å thick, and exposed to a nitridation process as mentioned above resulting in an ultrathin silicon oxynitride.
The tunneling dielectric layer can be implemented in embodiments of the present invention using a composite of silicon oxide, silicon oxynitride and silicon nitride without precise transitions between the layers, so long as the composite results in the required inverted U-shape valence band, having a change in valence band energy level at the offset distance from the channel surface needed for efficient hole tunneling. Also, other combinations of materials could be used to provide band offset technology.
The description of the dielectric tunneling layer focuses on “hole tunneling” rather than electron tunneling because the technology has solved the problems associated with the need to rely on hole tunneling in SONOS type memory. For example, a tunnel dielectric consisting of silicon dioxide which is thin enough to support hole tunneling at practical speeds, will be too thin to block leakage by electron tunneling. The effects of the engineering however, also improve performance of electron tunneling. So, both programming by electron tunneling and erasing by hole tunneling are substantially improved using band gap engineering.
Memory cells implemented as described above can be arranged in a NAND-type array as shown in
In the alternative, the memory cells can be arranged NOR-type or virtual ground-type arrays often applied in flash memory devices.
Programming may be accomplished in the NAND array by applying incremental stepped pulse programming ISPP or other processes for inducing Fowler Norheim tunneling. ISPP involves applying a stepped programming voltage, starting at a gate bias of for example about plus 17 V, and incrementing the voltage for each programming step by about 0.2 V. Each pulse can have a constant pulse width of about 10 μs for example. In variations of the technique, the pulse width and the increment applied for each succeeding pulse can be varied to meet the needs of the particular implementation. The memory cells of this type have demonstrated relatively linear programming characteristics, and very large memory windows compared to the prior art, making them particularly well-suited to storing multiple bits per cell with multilevel programming technologies. In alternative embodiments, the so-called voltage pulse self-boosting technique is applied for programming. Other biasing arrangements can be applied as well, selected for compatibility with array characteristics.
Other programming bias techniques can be applied. For NOR array structures, various biasing arrangements for inducing hot electron tunneling or FN tunneling may be applied as well as other techniques known in the art.
The array 812 can be a NAND array, an AND array or a NOR array, depending on the particular application. The very large memory window available supports storing multiple bits per cell, and thus multiple bit sense amplifiers can be included on the device.
A controller implemented in this example, using bias arrangement state machine 834, controls the application of bias arrangement supply voltages and current sources 836, such as read, program, erase, erase verify, program verify voltages or currents for the word lines and bit lines, and controls the word line/source line operation using an access control process. The controller 834 can be implemented using special purpose logic circuitry as known in the art. In alternative embodiments, the controller 834 comprises a general purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller 834.
The examples described above are implemented using n-channel devices, in which the source and drain terminals are doped with n-type impurities. The technology can be implemented using p-channel devices as well, in which the source and drain terminals are doped with p-type impurities.
The examples described above are implemented using devices with flat or planar channel surfaces. The technology can be implemented using non-planar structures, including cylindrical channel surfaces, fin shaped channels, recessed channels and so on.
The examples described above the charge storage stack is implemented so that the tunneling layer is on the channel surface and the blocking dielectric layer is adjacent the gate. In alternatives, the charge storage stack may be reversed, so that the tunneling layer is adjacent the gate terminal and the blocking dielectric is on the channel surface.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
Claims
1. A charge trapping memory, comprising:
- an array of memory cells, respective memory cells in the array including a semiconductor body including channel having a channel surface, and source and drain terminals adjacent the channel; a tunneling dielectric layer on the channel surface, the tunneling dielectric layer a combination of materials having negligible charge trapping efficiency, and arranged to establish a relatively large hole tunneling barrier height in near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface; a charge trapping dielectric layer on the tunnel dielectric layer; a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising a material having a dielectric constant K of 7 or more; and a gate on the blocking dielectric layer, the gate comprising a metal or metal compound on the blocking dielectric layer.
2. The memory of claim 1, including
- circuitry, coupled to the array of memory cells, to apply bias voltages to selected memory cells for read, program and erase operations, including bias voltages across the gate and semiconductor body to induce an electric field of less than 14 MV/cm to cause hole tunneling through the tunneling dielectric layer.
3. The memory of claim 1, wherein the blocking dielectric layer comprises aluminum oxide.
4. The memory of claim 1, wherein the gate comprises platinum.
5. The memory of claim 1, wherein the gate comprises aluminum.
6. The memory of claim 1, wherein the gate comprises tantalum nitride.
7. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness less than 20 Å, a low barrier height layer on the first silicon oxide layer, having a hole tunneling barrier height less than 3 eV, and an isolation layer isolating the low barrier height layer from the charge trapping dielectric layer.
8. The memory of claim 7, wherein the thickness of the first silicon oxide layer is 15 Å or less.
9. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 20 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less.
10. The memory of claim 1, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less.
11. The memory of claim 1, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel, and a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less.
12. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less;
- the charge trapping dielectric layer comprises silicon nitride having a thickness of 50 Å or more; and
- the blocking dielectric layer comprises aluminum oxide having a thickness of 150 Å or more.
13. The memory of claim 1, wherein said bias voltage for inducing hole tunneling is less than 16 Volts, and the hole tunneling current is sufficient to cause reduction in threshold voltage in a selected cell of more than 4 Volts in less than 10 milliseconds.
14. The memory of claim 1, wherein said bias voltage for inducing hole tunneling is less than 20 Volts, and the hole tunneling current is sufficient to cause reduction in threshold voltage in a selected cell of more than 4 Volts in less than 5 milliseconds.
15. The memory of claim 1, wherein the effective oxide thickness EOT of the blocking dielectric layer, the charge trapping dielectric layer and the tunneling dielectric layer is less than 200 Å.
16. A charge trapping memory, comprising:
- an array of memory cells, respective memory cells in the array including a semiconductor body including channel having a channel surface, and source and drain terminals adjacent the channel; a tunneling dielectric layer on the channel surface, the tunneling dielectric layer a combination of materials having negligible charge trapping efficiency, and arranged to establish a relatively large hole tunneling barrier height in near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface; a charge trapping dielectric layer on the tunnel dielectric layer; a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising aluminum oxide; a gate on the blocking dielectric layer, the gate comprising aluminum.
17. The memory of claim 16, including
- circuitry, coupled to the array of memory cells, to apply bias voltages to selected memory cells for read, program and erase operations, including bias voltages across the gate and semiconductor body to induce hole tunneling through the tunneling dielectric layer.
18. The memory of claim 16, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less.
19. The memory of claim 16, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less.
20. The memory of claim 16, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel, and a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less.
21. A charge trapping memory, comprising:
- an array of memory cells, respective memory cells in the array including a semiconductor body including channel having a channel surface, and source and drain terminals adjacent the channel; a tunneling dielectric layer on the channel surface, the tunneling dielectric layer a combination of materials having negligible charge trapping efficiency, and arranged to establish a relatively large hole tunneling barrier height in near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface; a charge trapping dielectric layer on the tunnel dielectric layer; a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising aluminum oxide; a gate on the blocking dielectric layer, the gate comprising platinum;
- circuitry, coupled to the array of memory cells, to apply bias voltages to selected memory cells for read, program and erase operations, including bias voltages across the gate and semiconductor body to induce hole tunneling through the tunneling dielectric layer.
22. The memory of claim 21, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less.
23. The memory of claim 21, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less.
24. The memory of claim 21, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel, and a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less.
Type: Application
Filed: Aug 27, 2007
Publication Date: Feb 12, 2009
Applicant: Macronix International Co., Ltd. (Hsinchu)
Inventors: HANG TING LUE (Hsinchu), Sheng-Chih Lai (Taichung City)
Application Number: 11/845,276
International Classification: H01L 29/792 (20060101);