METHOD FOR PREPARING DYNAMIC RANDOM ACCESS MEMORY STRUCTURE
A method for preparing a dynamic random access memory structure, comprising steps of forming a bottom conductive region in a substrate, removing a predetermined portion of the substrate to form a plurality of pillars having a bottom end lower than a bottom surface of the bottom conductive region, forming a first oxide layer on the substrate and below the bottom conductive region in the pillar, forming a conductive block between two adjacent pillars to electrically connect the two bottom conductive regions in the two adjacent pillars, forming a second oxide layer covering the conductive block, forming a gate oxide layer on a sidewall of the pillar, forming a gate structure on a surface of the gate oxide layer; and forming an upper conductive region on a top portion of the pillar.
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This application is a continuation application of and claims priority to application Ser. No. 11/402,871, filed Apr. 13, 2006.
BACKGROUND OF THE INVENTION(A) Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) structure and method for preparing the same, and more particularly, to a dynamic random access memory structure having vertical floating body memory cells and method for preparing the same.
(B) Description of the Related Art
A memory cell of the DRAM generally consists of a metal oxide semiconductor field effect transistor and a capacitor on a silicon substrate, and the transistor includes a source electrode electrically connected to an upper storage plate of the capacitor. There are two types of capacitors: stack capacitors and deep trench capacitors. The stack capacitor is fabricated on the surface of the silicon substrate, while the deep trench capacitor is fabricated inside the silicon substrate. Recently, the integrity of the DRAM has increased with the innovation of semiconductor fabrication technology rapidly. However, the size of the memory cell must be shrunk to achieve the purpose of high integrity, i.e., increasing the integrity needs to reduce the size of the transistor and the capacitor.
In 2002, Takahsi Ohasawa et al. discloses a new dynamic random access memory cell called floating body cell (FBC) (see: “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC Digest of Technical Paper, PP152-153). The floating body cell consists of a metal oxide semiconductor field effect transistor having a floating body on an expensive substrate of silicon on insulator (SOI), and the floating body serves to store carriers. Compared to the conventional one-transistor/one-capacitor memory cell using the capacitor to storing charges, the floating body cell stores the charges in the floating body without using an additional capacitor. Hence, the floating body cell has a simpler memory structure, smaller occupying area per memory cell and higher integrity than the conventional one-transistor/one-capacitor memory cell.
Further, the conventional one-transistor/one-capacitor memory cell checks whether the stored data is “1” or “0” by comparing a read out voltage from the memory cell with a reference voltage. Comparatively, the floating body cell checks whether the stored data is “1” or “0” based on the magnitude of a read out current. However, the floating body cell stores the carriers around an interface between two different materials, and defects in the interface is likely to recombine with the carriers, which influences the retention time of the carriers in the floating body.
SUMMARY OF THE INVENTIONThe primary objective of the present invention is to provide a dynamic random access memory structure having vertical floating body memory cells and method for preparing the same, which stores the carriers in the center of a vertically disposed floating body rather than in an interface between different material so as to have a longer retention time to the prevention of the recombination of the carrier with defects in the interface.
In order to achieve the above-mentioned objective and avoid the problems of the prior art, one embodiment of the present invention discloses a dynamic random access memory structure having vertical floating body memory cells. The dynamic random access memory structure comprises a substrate having a plurality of cylindrical pillars, a gate oxide layer positioned on a sidewall of each of the cylindrical pillars, and a gate structure positioned on a surface of the gate oxide layer. Each pillar comprises an upper conductive region positioned on a top portion of the pillar, a body positioned below the upper conductive region in the pillar and a bottom conductive region positioned below the body in the pillar. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body is capable of storing carriers. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the substrate, and the bottom conductive region in the pillar contacts the conductive layer.
According to another embodiment of the present invention, the dynamic random access memory structure further comprises an oxide layer positioned on the substrate and in a bottom portion of the pillar, wherein the bottom conductive region is positioned above the oxide layer in the pillar. In addition, the dynamic random access memory structure further comprises a conductive block positioned between two adjacent pillars to electrically connect the two bottom conductive regions in the two adjacent pillars.
According to one embodiment of the present invention, a method for preparing a dynamic random access memory structure comprises steps of forming a bottom conductive region in a substrate, removing a predetermined portion of the substrate to form a plurality of pillars having a bottom end lower than a bottom surface of the bottom conductive region, forming a first oxide layer on the substrate and below the bottom conductive region in the pillar, forming a conductive block between two adjacent pillars to electrically connect the two bottom conductive regions in the two adjacent pillars, forming a second oxide layer covering the conductive block, forming a gate oxide layer on a sidewall of the pillar, forming a gate structure on the surface of the gate oxide layer and forming an upper conductive region on a top portion of the pillar.
The conventional floating body cell is horizontally positioned and prepared on an expensive SOI substrate. Inversely, the dynamic random access memory structure of the present invention possesses one advantage of occupying a smaller area for increasing integrity since the floating body memory cell is vertically positioned. Further, the stored carriers stay in most cases at the center of the cylindrical body, which is not likely to recombine with the defects in the interface such as the surface of the pillar; hence, the carriers will have a longer retention time according to the present invention. In addition, the preparation of the vertical floating body memory cell can use the silicon substrate and the LOCOS process to form silicon on insulator structure rather than using the expensive SOI substrate as the prior art does; therefore, the present invention can dramatically decrease the fabrication cost.
The objectives and advantages of the present invention will become apparent upon reading the following description and upon reference to the accompanying drawings in which:
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According to one embodiment of the present invention, the dynamic random access memory array 90 comprises a plurality of floating body memory cells 40, a plurality of bit lines 32 and a plurality of word lines 34, wherein these floating body memory cells 40 are positioned on the semiconductor substrate 12 in a plurality of columns and rows manner. Each bit line 32 connects the upper conductive regions 30 of the floating body memory cells 40 in the same row and each word line 34 connects the gate structures 24′ of the floating body memory cells 40 in the same column. Further, the bottom conductive regions 38 of the floating body memory cells 40 in a predetermined area are connected to each other via the conductive layer 14′ to form a common source.
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To write data “1” into the vertical floating body memory cell 40 (the same to the other vertical floating body memory cell shown in other embodiment), the bottom conductive region 38 serving as the source electrode is grounded and a positive voltage is applied to the upper conductive region 30 serving as the drain electrode and the gate structure 24′ so that the vertical floating body memory cell 40 operates in the saturation region and holes are injected into the body 36 to write data “1”. To write data “0” into the vertical floating body memory cell 40, the bottom conductive region 38 is grounded, a positive voltage is applied to the gate structure 24′ and a negative voltage is applied to the upper conductive region 30 so that the PN junction is forward biased and holes are ejected to the upper conductive region 30 to write data “0”.
To read data stored in the vertical floating body memory cell 40, the bottom conductive region 38 is grounded and a positive voltage smaller than that is writing process is applied to the upper conductive region 30 and the gate structure 24′ so that the vertical floating body memory cell 40 operates in the linear region and the magnitude of the drain current depends on the number of the holes in the body 36. Consequently, whether the data stored in the vertical floating body memory cell 40 is “1” or “0” can be decided based on the magnitude of the read out drain current. Particularly, a positive voltage is applied to the gate structure 24′ surrounding the cylindrical body 36 that stores the carriers (holes) during the writing and reading process; hence, the carriers in most cases stay at the center of the cylindrical body 36, which is not likely to recombine with the defects at the interface. As a result, the carriers will have a longer retention time.
In addition, the preparation of the vertical floating body memory cell 40 can use the silicon substrate 12 and the LOCOS process to form silicon on insulator structure rather than using the expensive SOI substrate as the prior art does; therefore, the present invention can dramatically decrease the fabrication cost. Further, the width of the transistor in the vertical floating body memory cell 40 can be increased by increasing the height of the cylindrical pillar 18 rather than by increasing the occupied silicon area, which is very suitable to be applied in the advance high integrity design.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.
Claims
1. A method for preparing a dynamic random access memory structure, comprising steps of:
- forming a bottom conductive region in a substrate;
- removing a predetermined portion of the substrate to form a plurality of pillars having a bottom end lower than a bottom surface of the bottom conductive region;
- forming a first oxide layer on the substrate and below the bottom conductive region in the pillar;
- forming a conductive block between two adjacent pillars to electrically connect the two bottom conductive regions in the two adjacent pillars;
- forming a second oxide layer covering the conductive block;
- forming a gate oxide layer on a sidewall of the pillar;
- forming a gate structure on a surface of the gate oxide layer; and
- forming an upper conductive region on a top portion of the pillar.
2. The method for preparing a dynamic random access memory structure of claim 1, wherein the step of forming a bottom conductive region in a substrate is implanting ions into the substrate.
3. The method for preparing a dynamic random access memory structure of claim 1, wherein the step of removing a predetermined portion of the substrate to form a plurality of pillars comprises:
- forming a mask layer on the substrate; and
- performing an etching process to remove the substrate not covered by the mask layer until the bottom end of the pillar is lower than the bottom surface of the bottom conductive region.
4. The method for preparing a dynamic random access memory structure of claim 1, wherein the step of forming a first oxide layer on the substrate and below the bottom conductive region in the pillar comprises:
- forming a collar dielectric layer encapsulating a predetermined portion of the pillar;
- performing a thermal oxidation process to form the first oxide layer on the substrate and in the pillar not covered by the collar dielectric layer; and
- removing the collar dielectric layer.
5. The method for preparing a dynamic random access memory structure of claim 4, wherein the collar dielectric layer encapsulates a portion of the sidewall of the pillar above the bottom surface of the bottom conductive region.
6. The method for preparing a dynamic random access memory structure of claim 1, wherein the step of forming a gate structure on the surface of the gate oxide layer comprises:
- forming a polysilicon layer on the substrate; and
- performing an anisotropic etching process to form the gate structure having a spacer profile.
7. The method for preparing a dynamic random access memory structure of claim 1, further comprising a step of forming a conductive block between two adjacent pillars to electrically connect the two gate structures in the two adjacent pillars.
8. The method for preparing a dynamic random access memory structure of claim 1, wherein the step of forming an upper conductive region on a top portion of the pillar is implanting ions into the top portion of the pillar.
9. A method for preparing a dynamic random access memory structure, comprising steps of:
- preparing a substrate having a plurality of pillars;
- forming a first oxide layer on the substrate and in the pillar;
- forming a conductive block between the two pillars, the conductive block having a top end higher than the first oxide layer in the pillar;
- forming at least one bottom conductive region on the first oxide layer in the pillar;
- forming a second oxide layer covering the conductive block;
- forming a gate oxide layer on a sidewall of the pillar;
- forming a gate structure on a surface of the gate oxide layer; and
- forming an upper conductive region on a top portion of the pillar.
10. The method for preparing a dynamic random access memory structure of claim 9, wherein the step of forming a first oxide layer on the substrate and in the pillar comprises:
- forming a collar dielectric layer encapsulating a predetermined portion of the pillar;
- performing a thermal oxidation process to form the first oxide layer on the substrate and in the pillar not covered by the collar dielectric layer; and
- removing the collar dielectric layer.
11. The method for preparing a dynamic random access memory structure of claim 9, wherein the conductive block is made of polysilicon, and the step of forming at least one bottom conductive region on the first oxide layer in the pillar is performing a thermal treating process to diffuse ions from the conductive block into the pillar to form the bottom conductive region.
12. The method for preparing a dynamic random access memory structure of claim 9, wherein the step of forming a gate structure on a surface of the gate oxide layer comprises:
- forming a polysilicon layer on the substrate; and
- performing an anisotropic etching process to form the gate structure having a spacer profile.
13. The method for preparing a dynamic random access memory structure of claim 9, further comprising a step of forming a conductive block between two adjacent pillars to electrically connect the two gate structures in the two adjacent pillars.
14. The method for preparing a dynamic random access memory structure of claim 9, wherein the step of forming an upper conductive region on a top portion of the pillar is implanting ions into the top portion of the pillar.
Type: Application
Filed: Oct 13, 2008
Publication Date: Mar 5, 2009
Applicant: PROMOS TECHNOLOGIES INC. (HSINCHU)
Inventor: TING SING WANG (HSINCHU COUNTY)
Application Number: 12/250,223
International Classification: H01L 21/8242 (20060101);