Depletion Mode Field Effect Transistor for ESD Protection
The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in the respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.
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The present invention pertains to a field effect transistor. In particular, it pertains to a depletion type n-channel MOS field effect transistor that is used in a circuit to protect against electrostatic breakdown of a magnetic head.
BACKGROUND OF THE INVENTIONFor example, in the case of a magnetic head, such as a GMR magnetic head, incorporated into a magnetic recording device such as an HDD (hard disk drive), a depletion type n-channel MOS field effect transistor is utilized inside a preamplifier IC as a protective circuit to protect the magnetic head from an electrostatic breakdown.
Due to increased speeds and capacities of HDDs, there is a demand for depletion type n-channel field effect transistors with lower on resistances in order to improve the performance of ESD protection elements at low capacitances. To realize this, reductions in the on resistance and the drain capacitance are required, and a technique for reducing the on resistance while keeping the drain capacitance unchanged has been adopted.
As opposed to the field effect transistor with the configuration shown in
However, in recent years, there is a greater demand for faster driving, and further reduction in the on resistance and the drain capacitance is needed. The present invention was devised in light of the aforementioned situation, and its objective is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced.
SUMMARY OF THE INVENTIONIn order to achieve the aforementioned objective, the field effect transistor of the present invention has a first-conductivity type first semiconductor region with a channel formation region, a gate electrode that is formed in a pattern with a plurality of sides above the channel formation region of the first semiconductor region on a gate insulation film, a second conductivity type drain region that is formed on the surface part of the first semiconductor region within the inner region of the gate electrode, and second-conductivity type source regions that are formed in the surface layer part of said first semiconductor region in respective regions outside the plurality of sides of the gate electrode in widths that do not reduce the corresponding channel widths of the drain region when looked at from said respective outside regions.
In the aforementioned field effect transistor of the present invention, the gate electrode with the plurality of sides is formed in the first-conductivity type first semiconductor region with a channel formation region, a drain region is formed on the inner side of the gate electrode, and source regions are formed in respective regions on the outer side of the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. That is, the gate electrode is formed along all the sides of the drain region when the transistor is configured.
Preferably, in the aforementioned field effect transistor of the present invention, the gate electrode is formed repeatedly two-dimensionally in a grid pattern, and drain regions and the source regions are formed alternately and repeatedly two-dimensionally in the inner regions of the aforementioned grids in such a manner that either a drain region or a source region corresponds to a grid. In some instances, the back gates are formed inside the aforementioned first semiconductor region. Furthermore, the back gates and the source regions are connected to each other and a common potential is applied to them.
The field effect transistor of the present invention is used as a switch in a breakdown protection circuit for a magnetic head in order to protect the magnetic head from an electrostatic breakdown.
According to the field effect transistor of the present invention, the gate electrode is formed along all sides of a drain region. The on resistance can be reduced by a quarter with the same drain capacity, that is, the drain capacity per unit gate width can be reduced by a quarter.
Embodiments of the field effect transistor pertaining to the instant invention will be explained below with reference to Figures.
The polysilicon gate electrode 21 (G) is formed in a pattern with a plurality of sides above p-type well 14 having a channel formation region beneath the gate insulation film 20. In addition, a sidewall insulation film 22 is formed on either side part of gate electrode 21 (G). The n+-type source region 18S (S) and drain region 18D (D) containing a high concentration of an n-type conductive impurity substance (e.g. arsenic and/or phosphorous) are formed in the p-type well 14 at either side part of sidewall insulation film 22. Here, as shown in
The p30 -type back gate regions 18 BG (BG), which are electrically connected to p+-type back gate buried layer 13 are formed in the p-type well 14 corner portions of the gate electrode 21 (G). Back gate regions 18 BG (BG) may be configured in such a manner that while they are separated from source regions 18S (S) by element-separating insulation film 15 (I), the aforementioned gate electrode 21 (G) is extended as far as the boundary regions between back gate regions 18 BG (BG) and source regions 18S (S). In this case, gate electrode 21 (G) takes the shape of a grid.
In addition, for example, inter-layer insulation film 23 made of silicon oxide is formed to cover the aforementioned field effect transistor; opening parts that reach source regions 18S (S), drain region 18D (D), and back gate regions 18BG (BG) are formed; and wires (24S, 24D, and 24 BG) connected to source regions 18S (S), drain region 18D (D), and back gate regions 18 BG (BG) are formed as one body with plugs buried inside the opening parts.
According to the depletion type n-channel MOS field effect transistor of the present embodiment described above, because a gate electrode is formed along all the sides of the drain region, when compared with a field effect transistor that has the same drain region area with a gate electrode along a single side, the on resistance can be reduced by a quarter with the same drain capacity, that is, the drain capacity per unit gate width can be reduced by a quarter using the structure of the instant invention.
In the case of the field effect transistor of the present embodiment configured in the aforementioned manner, wires (24S and 24 BG) are connected, back gate regions 18BG (BG) and source regions 18S (S) are connected, and a common potential is applied. In addition, for example, the field effect transistor of the present embodiment is used as a switch in an electrostatic breakdown protection circuit for a magnetic head in order to protect the magnetic head against electrostatic breakdown.
Here, a drain region D is not provided at the outermost circumference. That is, source regions S are formed at the positions corresponding to the sides of a square drain region, and back gate regions BG are laid out between them. As described above, because the sides cannot be used for a drain region at the outermost circumference when configuring the transistor, it is desirable that the outermost region be used for source regions or back gate regions. However, it is also possible to provide drain regions at the outermost circumference.
Although the gate electrode is provided to surround all source regions S and back gate regions BG at the outermost circumferential part in consideration of the ease of removing gate electrode in the aforementioned configuration, the gate electrode between source regions S and back gate regions BG at said outermost circumferential part may be deleted, and back gate regions BG and source regions S may be separated from each other using element-separation insulation film I.
Shown in
Shown in
As shown in the Figure, the gate electrode 21 (G) is formed in the shape of a grid, and extends as far as the boundary between back gate region 18BG (BG) and source region 18S (S) in the aforementioned configuration. Here the back gate region 18BG (BG) and source region 18S (S) may be separated from each other using element-separating insulation film 15 (I). The multiple source regions 18S and drain region 18D are connected into a single system, respectively, using wires to be described later, and back gate regions 18BG are further connected to source regions 18S.
In the aforementioned configuration, the source regions and the drain regions are divided into multiple sections in a so-called a checkered pattern, and the gate electrode is provided at grid-like boundaries between the respective source regions and the drain regions. As such, while the source regions and the drain region that are adjacent to each other via the gate electrode constitute the field effect transistor, the respective source regions and the drain regions are put together into a single system and a single depletion type n-channel MOS field effect transistor is configured as a whole.
In comparison to a field effect transistor that has the same drain region area but only a single drain region, the aforementioned depletion type n-channel MOS field effect transistor of the present embodiment is equivalent to one in which the gate width of the transistor is significantly widened. As such, the on resistance can be reduced with the same drain capacitance, that is, the drain capacitance per unit gate width can be reduced.
In the aforementioned field effect transistors of the first embodiment and the second embodiment, the back gate regions are separated from the source regions by an element-separating insulation film, or the gate electrode extends as far as the boundaries between the back gate regions and the source regions, and the source regions and the back gate regions are connected using upper-layer wirings. However, when connection of the source regions to the back gate regions is assumed, there is no need to divide the source regions and the back gate regions into separate regions using the element-separating insulation film. In the case of the field effect transistor of the present embodiment, the source regions and the back gate regions are provided next to each other without separating them using an element-separating insulation film.
Shown in
As shown in
Shown in
Because the ESD protection circuits become conductive when an excessive voltage is applied to lines 31a and 31b so as to release said excessive voltage to the reference potential, a negative potential is applied to gate terminals 33a and 34a of the depletion type field effect transistors 33 and 34 to keep transistors 33 and 34 non-conductive while under the steady state. A bias current is supplied to magnetic head 30 through a path comprising a positive-side power supply, line 31a, magnetic head 30, line 31b, and a negative-side power supply. At this time, the voltage of the positive-side power supply is +3V to +5V, and the voltage of the negative-side power supply is −2V to −5V. In this case, gate electrodes 33a and 34a of field effect transistors 33 and 34 may be connected to the negative-side power supply. In addition, a voltage difference of roughly 100 mV is created between line 31a and line 31b, that is, across the two ends of magnetic head 30.
While preamplifier 32 and field effect transistors 33 and 34 can be formed on a single semiconductor integrated circuit (IC), magnetic head 30 is attached to said semiconductor integrated circuit externally.
The present invention is not restricted to the explanation given above. For example, a silicide layer may be formed partially or entirely over the surfaces of the source regions, the drain regions, the back gate regions, and the gate electrode. For example, it can be formed over the entire surfaces of the source regions, the drain regions, the back gate regions, and the gate electrode by means of siliciding process. Although depletion type field effect transistors were explained in the aforementioned embodiments, application to an enhancement type by not forming a channel region is also possible. In addition, although an n-channel depletion mode field effect transistor was explained, application to a p-channel depletion mode field effect transistor is also possible by simply reversing the n-type and p-type regions of the structures shown in the Figures.
Claims
1. Claim 1 is a field effect transistor, comprising:
- a semiconductor region of a first conductivity type with a channel formation region;
- a gate electrode that is formed in a pattern with a plurality of sides on a gate insulation film above the channel formation region of the first semiconductor region;
- a drain region that is formed in the first semiconductor region within an inner region of the gate electrode; and
- second-conductivity type source regions that are formed in the first semiconductor region in regions opposite to said inner region of the gate electrode in predetermined widths.
2. The field effect transistor of claim 1, wherein the gate electrode is formed in a two-dimensional grid pattern, and the drain region and the source region are formed alternately and repeatedly in two dimensions in regions of the two-dimensional grid pattern.
3. The field effect transistor of claim 2, wherein back gates are formed in the first semiconductor region.
4. The field effect transistor of claim 3, wherein the back gates and the source regions are connected to each other, and a common potential is applied to them.
5. The field effect transistor of claim 4, wherein the first-conductivity type is p-type and the second-conductivity type is n-type.
6. The field effect transistor of claim 5, wherein a second-conductivity type channel region is formed in the channel formation region of the semiconductor region.
7. An ESD depletion mode field effect transistor, comprising:
- a semiconductor layer of a first conductivity type formed on a semiconductor substrate;
- a square drain region of a second conductivity type formed in the first semiconductor layer;
- a plurality of source regions of a second conductivity type formed in first semiconductor layer at a predetermined distance from the drain region;
- a grid-shaped gate electrode formed on a gate insulating layer above a channel region of the first semiconductor layer, which is positioned between the drain region and the multiple source regions and surrounding the drain region, wherein the multiple source regions are provided at positions that correspond to respective sides of the drain region; and
- the multiple source regions are connected to each other electrically.
8. The transistor of claim 7 further comprising:
- the drain region, the multiple source regions, and the gate electrode all formed in a repetitive pattern;
- the drain regions formed in the repetitive pattern being connected to each other electrically; and
- the multiple source regions formed in the repetitive pattern being connected to each other electrically.
9. The transistor of claim 7 further comprising:
- a back gate region of a first conductivity type formed in the first semiconductor layer; and
- the multiple source regions and the back gate region connected to each other electrically.
10. The transistor of claim 9, wherein the channel region comprises a first-conductivity type semiconductor layer formed in the first semiconductor layer.
11. The transistor of claim 10, wherein the first-conductivity type is p-type and the second-conductivity type is n-type.
Type: Application
Filed: Sep 19, 2007
Publication Date: Mar 19, 2009
Applicant: TEXAS INSTRUMENTS INCORPORATED (Dallas, TX)
Inventors: Yohichi Okumura (Nerima-Ku), Josef Muenz (Muenchen)
Application Number: 11/857,576
International Classification: H01L 29/78 (20060101);