Interconnection element with plated posts formed on mandrel
An interconnection element can be formed by plating a metal layer within holes in an essentially non-metallic layer of a mandrel, wherein posts can be plated onto a metal layer exposed within the holes, e.g., a metal layer covering the holes in the non-metallic layer. The tips of the posts can be formed adjacent to ends or bottoms of the blind holes. Terminals can be formed in conductive communication with the conductive posts. The terminals can be connected through a dielectric layer to the conductive posts. At least a portion of the mandrel can then be removed from at least ends of the holes. In this way, the tips of the conductive posts can become raised above a major surface of the interconnection element such that at least the tips of the posts project beyond the major surface.
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This application claims the benefit of the filing dates of U.S. Provisional Application No. 60/964,823 filed Aug. 15, 2007 and 61/004,308 filed Nov. 26, 2007, the disclosures of which are hereby incorporated herein by reference.
BACKGROUND OF THE INVENTIONThe subject matter of the present application relates to microelectronic interconnection elements and assemblies and fabrication methods therefor, and more particularly to microelectronic interconnection elements and assemblies having protruding metal posts, especially metal posts defined by plating.
A current need exists to provide interconnection elements, e.g., chip carriers, package substrates, substrates of multiple chip modules, and other similar elements suitable for surface-mounting (flip-chip interconnection) of a microelectronic element thereon. Such need is felt especially for microelectronic elements which have fine-pitch contacts. With traditional technologies such as solder-to-solder interconnections, e.g., arrays of solder bumps, or bumps formed by screen-printing technology, it is becoming increasingly difficult to form conductive bumps of sufficient volume for flip-chip interconnection. The need is felt especially where the pitch of the conductive bumps is smaller than 150 microns.
SUMMARY OF THE INVENTIONIn accordance with an embodiment, a method is provided for fabricating an interconnection element, such as a package element, chip carrier, or other such element for interconnection to a microelectronic element, e.g., a semiconductor chip or packaged semiconductor chip.
The interconnection element can have raised conductive posts for conductive interconnection with another element, e.g., an element having least one of microelectronic devices or wiring thereon. In accordance with an embodiment, a first element, e.g., a mandrel, is provided on which features can be plated. The first element can include an essentially non-metallic layer having a top surface, a bottom surface remote from the top surface and a plurality of holes extending between the top and bottom surfaces. A lower metal layer can overlie the bottom surface of the essentially non-metallic layer such that the lower metal layer covers the bottoms of the holes. Within such blind holes of the first element a metal layer can be plated to form conductive posts having tips adjacent to ends or bottoms of the blind holes. Terminals can be formed in conductive communication with the conductive posts. The terminals can be connected through a dielectric layer to the conductive posts. At least a portion of the first element can then be removed from at least the ends of the holes. In this way, the tips of the conductive posts can become raised above a major surface of the interconnection element such that at least the tips of the posts project beyond the major surface.
In one embodiment, the first element can be formed by joining the lower metal layer with the essentially non-metallic layer and then forming the plurality of holes. In one example, the lower metal layer can consist essentially of copper. In a particular embodiment, the holes can have a pitch less than about 150 microns.
In one embodiment, when removing the first element or portion thereof, it can be removed selectively relative to a metal layer that spans the holes. Such hole-spanning metal layer can be disposed entirely between the top and bottom surfaces of the essentially non-metallic layer. In a particular embodiment, such hole-spanning metal layer can be plated onto a surface of the first metal layer which is exposed within the holes. The hole-spanning metal layer may not fully cover interior walls of the holes.
In a particular embodiment, a metal liner lines the holes of the first element when the metal layer is plated within the blind holes of the first element. Subsequently, the first element or portion thereof can be removed selectively relative to the metal liner. The metal layer can be such that it resists attack by an etchant used to selectively etch the first element. In one example, the metal liner can be a first metal layer which contacts a surface of an essentially non-metallic layer exposed within the holes. In such case, the formation of the conductive posts can include forming a second metal layer which contacts the first metal layer. In one embodiment, the first metal layer can be formed by processing including plating. In such case, the second metal layer can be plated onto the first metal layer.
In one embodiment, the second metal layer can fill the space overlying the metal liner within the holes. In a particular embodiment, the metal liner includes nickel. In a particular embodiment, the second metal layer includes copper. In one embodiment, the metal line can include nickel and the second metal layer can include copper.
In one embodiment, a plurality of conductive traces connected to the conductive posts can be formed at locations away from the tips of the conductive posts, such traces being formed simultaneously with the posts. In a particular embodiment, gaps between the conductive traces can be formed by subtractive processing after plating the metal layer. Alternatively, or in addition thereto, gaps between the conductive traces can be defined by plating the metal in an additive manner between features of a mask layer.
In accordance with an embodiment, a method is provided for fabricating an interconnection element. In such method, a metal can be plated within a plurality of blind holes of a first element, e.g., a mandrel, to form a plurality of conductive posts having tips formed adjacent to ends of the blind holes. Each conductive post may include a second metal layer which contacts a first metal layer that lines the holes of the first element. In one embodiment, the second metal layer can be resistant to attack by an etchant which attacks the first metal layer. Terminals can be formed which are exposed at a bottom surface of a dielectric layer of the interconnection element. The formed terminals can be in conductive communication with the conductive posts. At least a portion of the first element which is adjacent to the ends of the holes can then be removed. In such way, at least portions, e.g., at least the tips, of the conductive posts can be caused to protrude beyond a major surface of the interconnection element.
In accordance with an embodiment, a method is provided for fabricating an interconnection element. In such method, a metal can be plated within a plurality of blind holes of a first element, e.g., a mandrel, to form a plurality of conductive posts having tips formed adjacent to ends of the blind holes. In such case, the first element, e.g., mandrel, can include a first metal layer and a second metal layer which extends along the first metal layer. A third layer can overlie the first and second metal layers. The first element can have a plurality of holes extending through the third layer so as to form a plurality of blind holes atop the second metal layer, with the second metal layer exposed within the blind holes at ends thereof.
A metal layer can then be plated within the blind holes to form a plurality of conductive posts having tips formed adjacent to the ends of the blind holes. Each conductive post may further include a third metal layer in contact with the second metal layer. In one embodiment, such third metal layer can be resistant to attack by an etchant which attacks the first metal layer. Terminals can be formed which are exposed at a surface of a dielectric layer of the interconnection element. The terminals can be in conductive communication with the conductive posts. After forming the posts, at least a portion of the first element adjacent to the ends of the blind holes can be removed. In this way, at least portions of the conductive posts may be caused to protrude beyond the surface of the interconnection element.
As used in this disclosure, a terminal, contact, layer or other feature “exposed at” a surface of a dielectric element may be flush with such surface; recessed relative to such surface; or protruding from such surface, so long as that feature is accessible for contact by a theoretical point moving towards the surface in a direction perpendicular to the surface.
In accordance with an embodiment, a method will now be described for fabricating an interconnection element having raised conductive posts formed by plating, the posts usable to conductively connect the interconnection element to another element such as a microelectronic element or a wiring element, e.g., a circuit panel. As will be discussed in detail below, through use of an interconnection element having protruding conductive posts as discussed herein, interconnection can be provided to microelectronic elements or other elements having arrays of contacts arranged at a fine pitch, e.g., at a pitch less than 150 microns as measured center-to-center.
When the patternable layer 104 includes a polymeric layer, the layer may also be a sacrificial layer as used. In an exemplary embodiment, the patternable layer can have a thickness ranging from greater than ten microns up to more than one hundred microns. The metal layer 102 need not be very thick; its thickness can range upwards from a few microns to a few tens of microns, for example. The patternable layer 104 can be formed separately from the metal layer 102 and then joined thereto via a lamination process such as, for example, press lamination or roll lamination. A polymeric patternable layer can be formed by depositing an uncured material onto the metal layer by various means, such as, without limitation, roller coating, spin-coating, spray deposition or by contacting an underlying surface of the metal layer with a bath of the uncured material. The viscosity and characteristics of the deposition can be selected or modulated so as to achieve a patternable layer having the desired thickness. Multiple depositions can be utilized, if necessary to achieve a desired thickness or material characteristics of the patternable layer.
In a variation of the above-described process, the metal layer 102 can be formed by electroplating onto the patternable layer 104 after an appropriate electrically conductive commoning layer (not shown) is formed on layer 104, such as by electroless plating or sputtering, for example.
As illustrated in
Alternatively, the holes can be patterned by optical ablation, e.g., laser drilling, such as by laser light. In some cases, the laser light may have visible or ultraviolet wavelengths or a combination of visible and non-visible wavelengths. For example, the through holes can be formed by drilling using a laser such as an ultraviolet wavelength (UV) YAG laser, i.e., one made from yttrium aluminum garnet (YAG) which typically is doped with neodymium or other dopant. Holes produced by such UV YAG laser can have walls 110 which are nearly vertical, i.e., at relatively small angles to the vertical direction, where “vertical” is defined by a normal angle to the top surface 104. Thus, in the direction from the top surface to the bottom surface the walls 110 slant inward such that the width 110 of the through holes becomes smaller in that direction. Through holes in an element having a thickness 105 of 70 microns can be drilled to widths 112 of 50 microns, for example, and can be arranged at a pitch 116 such as 60 microns. Of course, through holes having greater widths and pitch can be attained within such element, as needed.
In a variation of the above process, the patternable layer 104 can be patterned to form through holes therein prior to joining with the metal layer 102, such as through use of a mechanical drilling or punching apparatus or laser drilling apparatus. After patterning, the layer 104 having through holes therein is joined with the metal layer 102, such as by press lamination or roll lamination, for example.
Subsequently, as illustrated in
As illustrated in
Subsequently, as illustrated in
As illustrated in
Referring to
Subsequently, a third metal layer is electroplated onto the structure to form conductive vias 136 filling the holes 134, as well as a metal layer 142 extending along the top surface 140. In one example, the third metal layer consists essentially of copper. A conductive layer, e.g., a conductive seed layer may be first formed in the openings and exposed surfaces of the dielectric layer as an electrical commoning prior to plating the third metal layer thereon.
Subsequently, as illustrated in
Thereafter, the metal layer 102 then is removed to result in the structure as illustrated in
Subsequently, the remaining layer 104 (
As a result, the conductive posts 130 now extend upwardly away from an exposed bottom surface 152 of the dielectric layer 132. The resulting conductive posts may have different possible shapes. For example, the posts may have frusto-conical shape, of which tips 160 can be flat or essentially flat. Alternatively, the posts may be cylindrical in shape. Other shapes are also possible, which may include posts which are elongated in a horizontal direction, i.e., in a direction parallel to the major surface 152 of the dielectric element, such that the posts may appear as rails protruding from the dielectric element 132.
The conductive posts extend a height 164 from an exposed major surface 152 of the dielectric layer. In one embodiment, the height can range from a few tens of microns to a few hundred microns, depending on the depth of the holes 106 within the mandrel 120 (
Through fabrication of the conductive posts using mandrel 120 having holes of regular height 105 (
In subsequent processing, solder masks 156, 158 may be formed overlying each of the bottom and major surfaces 152, 154 of the dielectric layer, respectively. After forming the solder masks, optionally a finish metal layer 162 such as gold or other metal may be applied to exposed tips 160 of the posts and terminals 151 exposed within openings in solder mask 158, resulting in the interconnection element 170 as illustrated in
The interconnection element 170 (
As shown in plan view in
As further shown in
In one example, interconnection element can function as a package substrate or chip carrier in a package including the microelectronic element and interconnection element.
The tips 160 of the conductive posts, which protrude beyond an upper face 176 of the interconnection element 170, are joined to corresponding conductive pads 174 of the microelectronic element. As illustrated in
The conductive posts 130, which are solid metal structures throughout, have relatively high current-carrying capacity, making the interconnection element suitable for interconnection with microelectronic elements, i.e., chips having high current density. Elements typically included within a processor such as microprocessors, co-processors, logic chips, and the like, have high current density and typically also have high interconnect density (high numbers of relatively fine pitch pads 174). The high current-carrying capacity of the solid metal posts 130 of interconnection element 170 make them suitable for interconnection with such chips.
At a lower face 178 of the interconnection element, terminals 151 are joined to corresponding terminals 182 of a circuit panel, wiring element, packaged microelectronic element or other conductive element. For example, as illustrated in
In another variation, although not specifically depicted in
In yet another variation (
In another variation of the above-described embodiment (
In an embodiment according to another variation of the above-described method (
Subsequently, as illustrated in
The plugs 222 may remain attached to the posts 230 when the mandrel is removed from the posts 230 (
Referring to
Subsequently, as illustrated in
Subsequently, as illustrated in
Referring to
Finally, as illustrated in
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims
1. A method of fabricating an interconnection element having raised conductive posts for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon, comprising:
- a) plating a metal within a plurality of blind holes of a first element to form conductive posts having tips formed adjacent to ends of the blind holes, the first element including an essentially non-metallic layer having a top surface, a bottom surface remote from the top surface and a plurality of holes extending between the top and bottom surfaces, the first element including a lower metal layer overlying the bottom surface of the essentially non-metallic layer, the lower metal layer covering the holes;
- b) forming terminals in conductive communication with the conductive posts, the terminals being connected through a dielectric layer to the conductive posts; and
- c) removing at least a portion of the first element at the ends of the holes to cause the tips of the conductive posts to become raised above a major surface of the interconnection element.
2. The method as claimed in claim 1, wherein the first element is formed by joining the lower metal layer with the essentially non-metallic layer and then forming the plurality of holes.
3. The method as claimed in claim 1, wherein the at least a portion of the first element is removed selectively relative to a hole-spanning metal layer disposed entirely between the top and bottom surfaces of the essentially non-metallic layer.
4. The method as claimed in claim 3, further comprising plating the hole-spanning metal layer onto a surface of the first metal layer exposed within the holes.
5. The method as claimed in claim 4, wherein the hole-spanning metal layer does not fully cover walls of the holes.
6. The method as claimed in claim 1, wherein a metal liner lines the holes of the first element when step (a) is performed and the at least a portion of the first element is removed selectively relative to the metal liner.
7. The method as claimed in claim 6, wherein the metal liner resists attack by an etchant used to selectively etch the first element.
8. The method as claimed in claim 7, wherein the metal liner is a first metal layer contacting a surface of an essentially non-metallic layer exposed within the holes and step (a) includes forming a second metal layer contacting the first metal layer.
9. The method as claimed in claim 8, further comprising forming the first metal layer by processing including plating.
10. The method as claimed in claimed in claim 9, wherein second metal layer is plated onto the first metal layer.
11. The method as claimed in claim 9, wherein the second metal layer fills the space overlying the metal liner within the holes.
12. The method as claimed in claim 9, wherein the metal liner includes nickel and the second metal layer includes copper.
13. The method as claimed in claim 1, wherein the lower metal layer consists essentially of copper and the holes have a pitch less than about 150 microns.
14. The method as claimed in claim 1, wherein the conductive posts have frusto-conical shape.
15. The method as claimed in claim 1, wherein conductive posts have cylindrical shape.
16. The method as claimed in claim 1, wherein step (a) includes forming a plurality of conductive traces connected to the conductive posts at locations away from the tips.
17. The method as claimed in claim 16, wherein step (a) further comprises defining gaps between the conductive traces by subtractive processing after plating the metal layer.
18. The method as claimed in claim 16, wherein gaps between the conductive traces are defined by plating the metal in additive manner between features of a mask layer.
19. A method of fabricating an interconnection element, comprising:
- a) plating a metal within a plurality of blind holes of a first element to form a plurality of conductive posts having tips formed adjacent to ends of the blind holes, each conductive post including a second metal layer contacting a first metal layer lining the holes, the second metal layer being resistant to attack by an etchant which attacks the first metal layer;
- b) forming terminals exposed at a bottom surface of a dielectric layer, the terminals being in conductive communication with the conductive posts; and
- c) removing at least a portion of the first element adjacent to the ends of the holes to cause at least portions of the conductive posts to protrude beyond the surface of the interconnection element.
20. A method of fabricating an interconnection element, comprising:
- a) providing a first element including a first metal layer, a second metal layer extending along the first metal layer and a third layer overlying the first and second metal layers, the first element having a plurality of holes extending through the third layer to form a plurality of blind holes atop the second metal layer and the second metal layer being exposed at ends of the blind holes;
- b) plating a metal within the blind holes to form a plurality of conductive posts having tips formed adjacent to the ends of the blind holes, each conductive post including a third metal layer contacting the second metal layer, the third metal layer being resistant to attack by an etchant which attacks the first metal layer;
- c) forming terminals exposed at a surface of a dielectric layer, the terminals being in conductive communication with the conductive posts; and
- d) removing at least a portion of the first element adjacent to the ends of the blind holes to cause at least portions of the conductive posts to protrude beyond the surface of the interconnection element.
Type: Application
Filed: Aug 15, 2008
Publication Date: Jun 11, 2009
Applicant: Tessera, Inc. (San Jose, CA)
Inventors: Sean Moran (Burlingame, CA), Jinsu Kwon (Campbell, CA), Kimitaka Endo (Yokohama)
Application Number: 12/228,896