NON-VOLATILE MEMORY AND METHODS FOR FABRICATING THE SAME
A non-volatile memory including a substrate, source/drain regions, a first insulating layer, a charge storage layer, a second insulating layer, and a conductive layer is provided. The source/drain regions are respectively disposed in the substrate apart from each other. The first insulating layer is disposed on the substrate between the source/drain regions. The charge storage layer is disposed on the first insulating layer. The second insulating layer is disposed on the charge storage layer, and a thickness of a peripheral region of the second insulating layer is greater than a thickness of an internal region of the second insulating layer. The conductive layer is disposed on the second insulating layer.
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1. Field of the Invention
The present invention relates to a structure of an integrated circuit (IC) and methods for fabricating the same. More particularly, the present invention relates to a structure of a non-volatile memory and methods for fabricating the same.
2. Description of Related Art
A non-volatile memory is characterized by maintaining stored data even when the power is off, and thus has become a mandatory device in many electronic products for providing normal operation when the electronic products are booted. Recently, the non-volatile memory has been widely adopted in personal computers (PCs) and other electronic equipment.
However, when programming the conventional two-bit/cell non-volatile memory, the two bits in the same memory cell are mutually affected. If one bit has been stored in a part near the drain region in the conventional non-volatile memory, a second-bit effect occurs when a reading operation is performed, such that a voltage in the portion where a high current is expected may drop. In other words, when the memory cell is being read, the existing bit poses a direct impact on the memory cell, thus increasing a barrier and a threshold voltage (Vt) for reading.
In view of the above, the second-bit effect not only substantially implicates the operation of devices, but also reduces the device reliability. Moreover, because the second-bit effect reduces a sense margin and a Vt window for operating the left bit and the right bit, thus an operation of multi-level cell memory is more difficult.
One of the current solutions is directed to increasing a drain voltage (Vd) for enhancing a drain-induced barrier lowering (DIBL), and thereby the increased barrier and the increased Vt arisen from the second-bit effect can be decreased. Nevertheless, since a dimension of the device is continuously shrinking, an excessive drain voltage will result in the operation difficulties as well.
SUMMARY OF THE INVENTIONIn light of the foregoing, the present invention is directed to a non-volatile memory capable of reducing a second-bit effect and resolving problems derived therefrom.
The present invention is further directed to several methods for fabricating a non-volatile memory capable of preventing cross interference of two bits in a memory cell of the non-volatile memory, such that the reliability of a memory device is enhanced.
The present invention provides a non-volatile memory including a substrate, a first insulating layer, a charge storage layer, a second insulating layer, and a conductive layer. The first insulating layer is disposed over the substrate and disposed between the source/drain regions. The second insulationg layer is provided with a peripheral region and an internal region. The charge storage layer is disposed between the first insulating layer and the second insulating layer. And, the peripheral region of the second insulating layer is thicker than the internal region of the second insulating layer. The conductive layer is disposed on the second insulating layer.
According to an embodiment of the present invention, the thickness of the internal region of the second insulating layer ranges from 80 angstrom to 100 angstrom, while the thickness of the peripheral region of the second insulating layer ranges from 90 angstrom to 120 angstrom. A thickness of the first insulating layer ranges from 50 angstrom to 60 angstrom. A thickness of the charge storage layer ranges from 60 angstrom to 80 angstrom.
According to an embodiment of the present invention, the first insulating layer is a oxide layer that comprising silicon oxide. The charge storage layer is a dielectric material provides charge trapping ability and the dielectric material is nitride material that comprising silicon nitride. The second insulating layer is a oxide layer that comprising silicon oxide.
The present invention further provides a method for fabricating a non-volatile memory. The method includes providing a substrate at first. A first insulating layer is formed over the substrate and disposed between two source/drain regions. A second insulationg layer is provided with a peripheral region and a internal region. A charge storage layer is formed between the first insulating layer and the second insulationg layer. The peripheral region of the second insulating layer is thicker than the internal region of the second insulating layer. A conductive layer is formed over the second insulating layer.
According to another embodiment of the present invention, the thickness of the internal region of the second insulating layer ranges from 80 angstrom to 100 angstrom, while the thickness of the peripheral region of the second insulating layer ranges from 90 angstrom to 120 angstrom. A thickness of the first insulating layer ranges from 50 angstrom to 60 angstrome. A thickness of the charge storage layer ranges from 60 angstrom to 80 angstrom.
According to an embodiment of the present invention, the first insulating layer is a oxide layer that comprising silicon oxide. The charge storage layer is a dielectric material provides charge trapping ability and the dielectric material is nitride material that comprising silicon nitride. The second insulating layer is a oxide layer that comprising silicon oxide.
The present invention further provides a method for fabricating a non-volatile memory. The method includes forming a stacked structure and a cosuming layer in sequence over a substrate at first. A converting process is performed at a peripheral region of the consuming layer to form a first insulating layer. The consuming layer is removed. A conductive layer is formed over the stacked layer and the first insulating layer.
According to another embodiment of the present invention, the stacked structure comprises a second insulating layer, a charge storage layer, and a third insulating layer formed in sequence over the substrate. A thickness of the third insulating layer ranges from 80 angstrom to 100 angstrom, while a thickness of the first insulating layer ranges from 10 angstrom to 20 angstrom. A thickness of the second insulating layer ranges from 50 angstrom to 60 angstrom. A thickness of the charge storage layer ranges from 60 angstrom to 80 angstrom.
According to another embodiment of the present invention, the second insulating layer is a oxide layer that comprising silicon oxide. The charge storage layer is a dielectric material provides charge trapping ability and the dielectric material is nitride material that comprising silicon nitride. The third insulating layers is a oxide layer that comprising silicon oxide.
According to another embodiment of the present invention, the first insulating layers is a oxide layer that comprising silicon oxide.
According to another embodiment of the present invention, the consuming layer is a polysilicon layer.
According to another embodiment of the present invention, the converting process is an oxidation process.
The present invention further provides a method for fabricating a non-volatile memory. The method includes forming a stacked structure and a cosuming layer in sequence over a substrate at first. A converting process is performed at a peripheral region of the consuming layer to form a first insulating layer. The cosuming layer is removed. A second insulating layer is conformally formed on the stacked structure and the first insulating layer. A conductive layer is formed on the second insulating layer.
According to another embodiment of the present invention, a thickness of the first insulating layer ranges from 10 angstrom to 20 angstrom, while a thickness of the second insulating layer ranges from 80 angstrom to 100 angstrom.
According to another embodiment of the present invention, the stacked structure comprises a third insulating layer and a charge storage layer formed in sequence over the substrate. A thickness of the third insulating layer ranges from 50 angstrom to 60 angstrom. A thickness of the charge storage layer ranges from 60 angstrom to 80 angstrom. The third insulating layer is a oxide layer that comprising silicon oxide. The charge storage layer is a dielectric material provides charge trapping ability, and the dielectric material is nitride material that comprising silicon nitride.
According to another embodiment of the present invention, the first insulating layer is a oxide layer that comprising silicon oxide and the second insulating layers is a oxide layer that comprising silicon oxide.
According to another embodiment of the present invention, the consuming layer is a polysilicon layer.
According to another embodiment of the present invention, the converting process is an oxidation process.
In the present invention, the stacked structure comprising the insulating layer/the charge storage layer/the insulating layer is disposed between the conductive layer and the substrate. The insulating layer disposed between the conductive layer and the dielectric layer has a greater thickness of the peripheral region than the thickness of the internal region of the insulating layer. Accordingly, the thickness of the peripheral region of the insulating layer results in a greater DIBL, which effectively reduces the second-bit effect. On the other hand, the non-volatile memory of the present invention can be further applied to a multi-bit memory device.
In order to make the above and other objects, features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
The insulating layer 204 of the non-volatile memory is disposed on the substrate 200 between the source/drain regions 202a and 202b. The insulating layer 204 is a oxide layer which a material of that is, for example, silicon oxide, and a thickness of the insulating layer 204, for example, ranges from 50 angstrom to 60 angstrom, and is preferably about 54 angstrom. The charge storage layer 206 is disposed on the insulating layer 204. Here, the charge storage layer 206 is a dielectric material provides charge trapping ability, and the dielectric material is nitride material which is silicon nitride, for example. A thickness of the charge storage layer 206, for example, ranges from 60 angstrom to 80 angstrom, and is preferably about 70 angstrom. The insulating layer 208 is disposed on the charge storage layer 206, and the insulating layer 208 is a oxide layer which a material of that is silicon oxide, for example. The conductive layer 210 is disposed on the insulating layer 208, and a material of the conductive layer 210 is polysilicon, for example. Here, the conductive layer 210 serves as a gate of the non-volatile memory.
Note that the difference between the non-volatile memory proposed in the present embodiment and the conventional non-volatile memory lies in that the insulating layer 208 of the non-volatile memory in the present embodiment is not in a uniform thickness. The thickness of the peripheral region (regions 207a surrounded by dotted lines in
It should be noted that since the non-uniform insulating layer 208 has the greater thickness of the peripheral region 207a than at the internal region 207b, a Vt of the non-volatile memory is affected by the thickness of the insulating layer 208 above the charge storage layer 206, resulting in a relatively significant DIBL. Thereby, the second-bit effect is reduced, and a Vt window is increased as well.
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Next, several embodiments are enumerated hereinafter for elaborating methods for fabricating the non-volatile memory of the present invention.
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To sum up, in the present invention, the stacked structure comprising the insulating layer/the charge storage layer/the insulating layer is disposed between the conductive layer and the substrate. The insulating layer disposed between the conductive layer and the charge storage layer has a greater thickness of the peripheral region than the thickness of the internal region of the insulating layer. Accordingly, the thickness of the peripheral region of the insulating layer results in a greater DIBL, which effectively reduces the second-bit effect and resolves the problems derived therefrom. Moreover, the device reliability and the Vt window for operating the left bit and the right bit are increased. Furthermore, the non-volatile memory of the present invention can be applied to a multi-bit memory device as well.
The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.
Claims
1. A non-volatile memory, comprising:
- a substrate;
- a first insulating layer disposed over the substrate and disposed between two source/drain regions;
- a second insulationg layer provided with a peripheral region and a internal region;
- a charge storage layer disposed between the first insulating layer and the second insulationg layer, wherein the peripheral region of the second insulating layer is thicker than the internal region of the second insulating layer; and
- a conductive layer disposed over the second insulating layer.
2. The non-volatile memory as claimed in claim 1, wherein the thickness of the internal region of the second insulating layer ranges from 80 angstrom to 100 angstrom, while the thickness of the peripheral region of the second insulating layer ranges from 90 angstrom to 120 angstrom.
3. The non-volatile memory as claimed in claim 1, wherein a thickness of the first insulating layer ranges from 50 angstrom to 60 angstrom.
4. The non-volatile memory as claimed in claim 1, wherein a thickness of the charge storage layer ranges from 60 angstrom to 80 angstrom.
5. The non-volatile memory as claimed in claim 1, wherein the first insulating layer is a oxide layer that comprising silicon oxide.
6. The non-volatile memory as claimed in claim 1, wherein the charge storage layer is a dielectric material.
7. The non-volatile memory as claimed in claim 6, wherein the dielectric material providing charge trapping ability.
8. The non-volatile memory as claimed in claim 6, wherein the dielectric material is nitride material that comprising silicon nitride.
9. The non-volatile memory as claimed in claim 1, wherein the second insulating layer is a oxide layer that comprising silicon oxide.
10. A method for fabricating a non-volatile memory, the method comprising:
- providing a substrate;
- forming a first insulating layer over the substrate and disposed between two source/drain regions;
- providing a second insulationg layer having a peripheral region and a internal region;
- forming a charge storage layer between the first insulating layer and the second insulationg layer, wherein the peripheral region of the second insulating layer is thicker than the internal region of the second insulating layer; and
- forming a conductive layer over the second insulating layer.
11. The method for fabricating the non-volatile memory as claimed in claim 10, wherein the thickness of the internal region of the second insulating layer ranges from 80 angstrom to 100 angstrom, while the thickness of the peripheral region of the second insulating layer ranges from 90 angstrom to 120 angstrom.
12. The method for fabricating the non-volatile memory as claimed in claim 10, wherein a thickness of the first insulating layer ranges from 50 angstrom to 60 angstrom.
13. The method for fabricating the non-volatile memory as claimed in claim 10, wherein a thickness of the charge storage layer ranges from 60 angstrom to 80 angstrom.
14. The method for fabricating the non-volatile memory as claimed in claim 10, wherein the charge storage layer is a dielectric material and the dielectric material providing charge trapping ability.
15. The method for fabricating the non-volatile memory as claimed in claim 14, wherein the dielectric material is nitride material that comprising silicon nitride.
16. A method for fabricating a non-volatile memory, the method comprising:
- forming a stacked structure and a cosuming layer in sequence over a substrate;
- performing a converting process at a peripheral region of the consuming layer to form a first insulating layer;
- removing the consuming layer; and
- forming a conductive layer over the stacked layer and the first insulating layer.
17. The method for fabricating the non-volatile memory as claimed in claim 16, wherein the stacked structure comprises a second insulating layer, a charge storage layer, and a third insulating layer formed in sequence over the substrate.
18. The method for fabricating the non-volatile memory as claimed in claim 17, wherein a thickness of the third insulating layer ranges from 80 angstrom to 100 angstrom, while a thickness of the first insulating layer ranges from 10 angstrom to 20 angstrom.
19. The method for fabricating the non-volatile memory as claimed in claim 17, wherein a thickness of the second insulating layer ranges from 50 angstrom to 60 angstrom.
20. The method for fabricating the non-volatile memory as claimed in claim 17, wherein a thickness of the charge storage layer ranges from 60 angstrom to 80 angstrom.
21. The method for fabricating the non-volatile memory as claimed in claim 17, wherein the charge storage layer is a dielectric material and the dielectric material providing charge trapping ability.
22. The method for fabricating the non-volatile memory as claimed in claim 17, wherein the dielectric material is nitride material that comprising silicon nitride.
23. The method for fabricating the non-volatile memory as claimed in claim 16, wherein the converting process is an oxidation process.
Type: Application
Filed: Jan 17, 2008
Publication Date: Jul 23, 2009
Applicant: MACRONIX INTERNATIONAL CO., LTD. (Hsinchu)
Inventor: Ming-Chang Kuo (Hsinchu)
Application Number: 12/015,939
International Classification: G11B 5/62 (20060101); B05D 5/12 (20060101);