Deep source electrode MOSFET
A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.
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This application is based on and claims priority to the of U.S. Provisional Application Ser. No. 60/836,639, filed on Aug. 9, 2006, entitled Termination Design for Deep Source Electrode MOSFET, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.
BACKGROUND OF THE INVENTIONUS Patent Publication No. 2006/0033154, assigned to the assignee of the present application and incorporated by reference, discloses a semiconductor power device having deep source electrodes which can be suitable for a power MOSFET with up to a 300V rating and a lower resistivity drift region. For example, a conventional 100V device may use 1.75 ohm-cm drift region while a device employing deep source electrodes may have a 0.25 ohm-cm drift region.
Conventional MOSFET designs may use a termination structure composed of diffused guard rings to reduce the electric field curvature, but still rely on the drift region to block a significant amount of voltage. If a conventional termination were used on a 100V MOSFET designed with a deep source electrode, the termination would only support about 30V due to the low-resistivity drift region.
Thus, a new termination that is capable of blocking a voltage equal or greater than the active cells of a deep source electrode MOSFET is desired. It is also desired to have a simple process to form the termination when fabricating a deep source electrode MOSFET.
SUMMARY OF THE INVENTIONA device, e.g. a MOSFET, that includes deep source electrodes is able to block a high reverse voltage with a low-resistivity drift region because the deep source electrodes create a horizontal electric field that depletes the drift region and enable the creation of a uniform electric field.
According to one aspect of the present invention, the portion of the termination closest to the last active cell is identical to the active cell (except that it does not include a source region) in order to avoid disturbing the depletion effect.
According to another aspect of the present invention, the termination region of the device includes an insulated field plate spaced above the surface of the semiconductor by an insulating material in order to avoid high electric field points outside the active region of the device.
According to yet another aspect of the present invention, the termination region includes an EQR trench and a drain contact at the end of the termination in order to block any leakage that may occur near the semiconductor surface, and to ensure a constant drain voltage on the top edge of the device.
A termination according to the present invention allows a device using deep source electrodes to be terminated using a minimum lateral width. Moreover, a termination according to the present invention mimics the active area features, to avoid adding any process complexity.
Simulations have shown that, when using a termination according to the present invention, the highest electric field occurs in the region between the termination and the active region, and that there are no high field points elsewhere in the termination, which can allow for a short field plate. Thus, unlike conventional guard ring and field plate terminations, the field plate is not relied on to smooth out junction curvature in that all of the high field is contained between the last active cell trench and the termination trench.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
Referring to
According to one aspect of the present invention, termination trenches 14 are as deep as source trenches 10. Furthermore, termination region 58 includes a field relief electrode 26 preferably comprised of polysilicon, that includes a finger 27 residing in each termination trench 14, and a field plate portion 25 that extends away from active region 56 and over an insulation body 66 residing on body 12 between termination trenches 14 and EQR trench 16. Furthermore, an EQR electrode 28, which is preferably comprised of polysilicon, is disposed inside EQR trench 16. An EQR ring 50 is disposed over and ohmically coupled to EQR electrode 28 and may be extended and coupled to body 12 near the edge of the die (to the right of electrodes 28), whereby EQR trench 16 and the electrode contained therein serve to apply a constant drain voltage at the edge of the termination and block any surface leakage that may occur.
The device further includes a gate bus 40, preferably comprised of polysilicon, which is insulated from and disposed over field plate portion 25 of termination electrode 26. Gate bus 40 is electrically connected to gate electrodes 38. A metallic gate runner 52, which resides over bus 40 electrically couples bus 40 to a gate contact pad. The device further includes a drain contact 15, coupled to substrate 13.
Referring now to
Referring next to
Referring next to
Next, the exposed surfaces of electrodes 24, 26, 28 are oxidized leaving a thin oxide layer 30 thereon. Note that in this step the exposed surfaces of the sidewalls of trenches 10, and the sidewall of trench 14 are also oxidized to form gate oxide 32 thereon. Preferably, dopants to form a channel region are then implanted to form a channel implant region 34 before proceeding to the next step.
Referring next to
Thereafter, source implant region 44 is driven in a source drive, high conductivity contact regions 54 are implanted followed by an anneal, and optionally titanium is deposited and a thermal step is applied to obtain a silicide layer atop the exposed surfaces of body 12. Front metal is deposited and patterned to obtain source contact 48, EQR ring 50, and gate runner 52, and drain contact 15 is applied using any known method as illustrated by
Note that in a device according to the present invention, channel region 62 that extends into termination region 58 includes a high conductivity region 54 to short source contact 64 the channel region. Note further that termination trench 14 closest to active region 56 also contains a non-functional insulated gate electrode at a sidewall that is closest to active region 56. The oxide thickness under field plate 25 is preferably the same as the thick oxide inside the trenches in order to support the full breakdown voltage between field plate 56 and semiconductor body 12 under the field plate.
In an alternative embodiment, it is possible to have more than two termination trenches, which would effectively extend the lateral width of field plate 25.
Referring to
Referring to
In all embodiments, preferably, EQR trench 14 is the same depth and width as source trenches 10.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims
1-9. (canceled)
10. A power semiconductor device comprising:
- a semiconductor body having at least one channel region;
- at least one source trench extending into said semiconductor body and being adjacent to said at least one channel region;
- a gate insulation situated adjacent to said at least one source trench;
- a gate electrode situated adjacent to said gate insulation;
- a source electrode disposed adjacent to and insulated from said gate electrode;
- a source region situated adjacent to said at least one source trench;
- a source contact electrically coupled to said source electrode and said source region.
11. The power semiconductor device of claim 10, wherein said gate electrode spans said at least one channel region.
12. The power semiconductor device of claim 10, wherein said source contact is ohmically coupled to said at least one channel region.
13. The power semiconductor device of claim 10, wherein said source electrode is insulated from said semiconductor body by a thick insulation layer disposed inside said at least one source trench.
14. The power semiconductor device of claim 10, wherein said source electrode extends below said gate electrode.
15. The power semiconductor device of claim 13, wherein said thick insulation layer is disposed below said gate electrode.
16. The power semiconductor device of claim 10 further comprising a drain contact underlying said semiconductor body.
17. A power semiconductor device comprising:
- a semiconductor body having a first conductivity and including at least two channel regions, each of said at least two channel regions having a second conductivity;
- at least one source trench extending into said semiconductor body and being situated between two of said at least two channel regions;
- a first gate insulation situated adjacent to a first sidewall of said at least one source trench and situated adjacent to one of said least two channel regions;
- a first gate electrode situated adjacent to said first gate insulation;
- a second gate insulation situated adjacent to a second sidewall of said at least one source trench and situated adjacent to another of said at least two channel regions;
- a second gate electrode situated adjacent to said second gate insulation;
- a source electrode situated inside said at least one source trench and disposed between and insulated from said first and second gate electrodes, said source electrode extending below said first and second gate electrodes;
- a source region situated adjacent to each of said first and second sidewalls of said at least one source trench;
- a source contact electrically coupled to said source electrode and said source regions.
18. The power semiconductor device of claim 17, wherein said first gate electrode spans said one of said at least two channel regions and said second gate electrode spans said another of said at least two channel regions.
19. The power semiconductor device of claim 17, wherein said source contact is ohmically coupled to said at least two channel regions.
20. The power semiconductor device of claim 17, wherein said source electrode is insulated from said semiconductor body by a thick insulation layer disposed inside said at least one source trench.
21. The power semiconductor device of claim 20, wherein each of said first and second gate insulations is thinner than said thick insulation layer.
22. The power semiconductor device of claim 20, wherein said thick insulation layer is disposed below said first and second gate electrodes.
23. The power semiconductor device of claim 17 further comprising a drain contact underlying said semiconductor body.
24. A power semiconductor device comprising:
- an active region including a plurality of source trenches extending into a semiconductor body, said semiconductor body having a first conductivity;
- a plurality of channel regions formed in said semiconductor body, each of said plurality of channel regions having a second conductivity, two of said plurality of channel regions being situated adjacent to each of said plurality of source trenches;
- a first gate insulation situated adjacent to a first sidewall of said each of said plurality of source trenches and situated adjacent to one of said plurality of channel regions;
- a first gate electrode situated adjacent to said first gate insulation;
- a second gate insulation situated adjacent to a second sidewall of said each of said plurality of source trenches and situated adjacent to another of said plurality of channel regions;
- a second gate electrode situated adjacent to said second gate insulation;
- a source electrode situated inside said each of said plurality of source trenches and disposed between and insulated from said first and second gate electrodes, said source electrode extending below said first and second gate electrodes;
- a source region situated adjacent to each of said first and second sidewalls of said each of said plurality of source trenches;
- a source contact electrically coupled to said source electrode and said source region.
25. The power semiconductor device of claim 24, wherein said source electrode is insulated from said semiconductor body by a thick insulation layer disposed inside said each of said plurality of source trenches.
26. The power semiconductor device of claim 25, wherein each of said first and second gate insulations is thinner than said thick insulation layer inside said each of said plurality of source trenches.
27. The power semiconductor device of claim 25, wherein said thick insulation layer is disposed below said first and second gate electrodes in said each of said plurality of source trenches.
28. The power semiconductor device of claim 24 further comprising a termination region situated adjacent to said active region, wherein said termination region includes at least one termination trench extending into said semiconductor body.
29. The power semiconductor device of claim 24 further comprising a drain contact underlying said semiconductor body.
Type: Application
Filed: Jul 16, 2009
Publication Date: Nov 12, 2009
Applicant:
Inventors: Jianjun Cao (Torrance, CA), Timothy Henson (Torrance, CA)
Application Number: 12/460,434
International Classification: H01L 29/78 (20060101);