MOSFET INCLUDING EPITAXIAL HALO REGION
A metal oxide semiconductor field effect transistor structure and a method for fabricating the metal oxide semiconductor field effect transistor structure provide for a halo region that is physically separated from a gate dielectric. The structure and the method also provide for a halo region aperture formed horizontally and crystallographically specifically within a channel region pedestal within the metal oxide semiconductor field effect transistor structure. The halo region aperture is filled with a halo region formed using an epitaxial method, thus the halo region may be formed physically separated from the gate dielectric. As a result, performance of the metal oxide semiconductor field effect transistor is enhanced.
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1. Field of the Invention
The invention relates generally to metal oxide semiconductor field effect transistor (MOSFET) structures, and methods for fabrication thereof. More particularly, the invention relates to metal oxide semiconductor field effect transistor structures that include well defined halo regions, and methods for fabrication thereof.
2. Description of the Related Art
Semiconductor structures include semiconductor substrates within and upon which are formed semiconductor devices, such as but not limited to resistors, transistors, diodes and capacitors. The semiconductor devices are connected and interconnected using patterned conductor layers that are separated by dielectric layers. A particularly common semiconductor device that is used for fabricating semiconductor structures is a metal oxide semiconductor field effect transistor. Such a metal oxide semiconductor field effect transistor comprises a gate located and formed over a gate dielectric that in turn is located and formed over a channel region within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. Metal oxide semiconductor field effect transistors have been successfully scaled in dimension over the period of several decades to provide semiconductor circuits with continuously enhanced functionality and continuously enhanced performance.
A particular structural element that is desirable within a metal oxide semiconductor field effect transistor is a halo region of different, and typically opposite, polarity of the source region and the drain region (which hereinafter will be referred to as source and drain regions). Such a halo region, that is located interposed between the source and drain regions and the channel region, is intended to provide enhanced channel isolation within a metal oxide semiconductor field effect transistor. Unfortunately, since halo regions are typically formed using a large angle tilt ion implantation method when a gate and gate dielectric are in place and used as an ion implantation mask, halo region implantation ions routinely compromise performance of field effect transistor devices insofar as halo region implantation ions provide undesirable residual halo region implantation atoms physically at or near a gate dielectric.
Thus, desirable within the semiconductor fabrication art are metal oxide semiconductor field effect transistor structures that include well defined halo regions that are physically separated from gate dielectrics.
SUMMARYThe invention provides a metal oxide semiconductor field effect transistor structure that includes a well defined halo region that is physically separated from a gate dielectric, and a method for fabricating the metal oxide semiconductor field effect transistor structure that includes the well defined halo region that is physically separated from the gate dielectric. The particular metal oxide semiconductor field effect transistor structure and method in accordance with the invention are predicated upon a halo region within a metal oxide semiconductor field effect transistor that is grown as an epitaxial halo region rather than formed as an ion implanted halo region. By growing the halo region as the epitaxial halo region rather than implanting the halo region as the implanted halo region, the halo region may be formed with better defined boundaries that include well defined boundaries, that in turn are physically separated from a gate dielectric. As a result of the better defined halo region boundaries that comprise well defined boundaries that are physically separated from the gate dielectric, the metal oxide semiconductor field effect transistor may be fabricated to provide enhanced performance within the context of improved carrier mobility.
Within the context of the embodiment and the invention, “well defined” boundaries of an epitaxial halo region in comparison with an implanted halo region are intended as boundaries that are sufficiently contained so that halo dopant atoms are not present within a distance less than 5 nanometers from a gate dielectric. Preferably, such halo atoms are located at a distance at least 15 nanometers, and preferably from 5 to 15 nanometers from the gate dielectric.
A particular metal oxide semiconductor field effect transistor structure in accordance with the invention includes a gate located over a gate dielectric. The gate dielectric in turn is located over a channel region within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. This particular metal oxide semiconductor field effect transistor structure also includes at least one halo region located at least in-part beneath the channel region and physically separated from the gate dielectric.
A particular method for fabricating a metal oxide semiconductor field effect transistor in accordance with the invention includes forming a gate over a gate dielectric. The gate dielectric in turn is formed over a channel region within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. This particular method also includes forming at least one halo region located at least in-part beneath the channel region and physically separated from the gate dielectric.
Another particular method for fabricating a metal oxide semiconductor field effect transistor in accordance with the invention includes forming a gate over a gate dielectric. The gate dielectric in turn is formed over a semiconductor substrate. This other particular method also includes etching vertically the semiconductor substrate while using at least in-part the gate as a mask, to form a channel region pedestal within the semiconductor substrate. This other particular method also includes etching horizontally and crystallographically specifically the channel region pedestal to provide at least one halo region aperture within the channel region pedestal that is defined at least in-part by a crystallographic plane of the semiconductor substrate. The at least one halo region aperture is physically separated from the gate dielectric. This other particular method also includes forming at least in-part horizontally epitaxially a halo region into the halo region aperture.
The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiment, a set forth below. The Description of the Preferred Embodiment is understood within the context of the accompanying drawings, that form a material part of this disclosure wherein:
The invention, which includes a particular metal oxide semiconductor field effect transistor structure and a particular method for fabricating the particular metal oxide semiconductor field effect transistor structure, is understood within the context of the description set forth below. The description set forth below is understood within the context of the drawings described above. Since the drawings are intended for illustrative purposes, the drawings are not necessarily drawn to scale.
Within the schematic cross-sectional diagram of
Each of the first semiconductor material and the second semiconductor material may comprise any of several semiconductor materials. Non-limiting examples of candidate semiconductor materials for each of the first semiconductor material and the second semiconductor material include silicon, germanium, silicon-germanium alloy, silicon-carbon alloy, silicon-germanium-carbon alloy and compound (i.e., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide semiconductor materials.
Typically, and for exemplary purposes, the first semiconductor layer 10 comprises a silicon semiconductor material that has a thickness from 0.05 to 750 micrometers and the third semiconductor layer 14 comprises the same silicon semiconductor material that has a thickness from 20 to 50 nanometers. Typically, and also for exemplary purposes, the second semiconductor layer 12 comprises a silicon-germanium alloy semiconductor material that has a germanium content from 2 to 5 atomic percent and a thickness from 5 to 10 nanometers, and the fourth semiconductor layer 16 comprises a silicon-germanium alloy semiconductor material that also has the germanium content from 2 to 15 atomic percent and a thickness from 5 to 10 nanometers. The foregoing semiconductor materials selections are intended as illustrative of the invention rather than limiting of the invention. Alternative semiconductor materials selections, including but not limited to reversed semiconductor materials selections, are also plausible and not precluded within the embodiment and the invention.
As is also understood by a person skilled in the art, each of the first semiconductor layer 10, the second semiconductor layer 12, the third semiconductor layer 14 and the fourth semiconductor layer 16 comprises a dopant of polarity and concentration appropriate to a metal oxide semiconductor field effect transistor desired to be fabricated incident to further processing of the semiconductor structure whose schematic cross-sectional diagram is illustrated in
Similarly, although the particular embodiment of the invention that is illustrated in
Semiconductor-on-insulator substrates and hybrid orientation substrates may be fabricated using any of several methods, including but not limited to layer laminating methods, layer transfer methods and separation by implantation of oxygen (SIMOX) methods. In contrast, the nominally bulk semiconductor substrate within the semiconductor structure that is illustrated in
The gate dielectric 18 may comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon that have a dielectric constant from about 4 to about 20, measured in vacuum. Alternatively, the gate dielectric 18 may comprise generally higher dielectric constant gate dielectric materials having a dielectric constant from about 20 to at least about 100. Such generally higher dielectric constant dielectric materials may include, but are not limited to hafnium oxides, hafnium silicates, titanium oxides, barium-strontium-titantates (BSTs) and lead-zirconate-titanates (PZTs).
The gate dielectric 18 may be formed using any of several methods that are appropriate to its material of composition. Included, but not limiting, are thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. Typically, the gate dielectric 18 comprises a thermal silicon oxide dielectric material that has a thickness from 0.5 to 2 nanometers or a higher dielectric constant dielectric material, that has a thickness from 1 to 3 nanometers.
The gate 20 may comprise gate conductor materials including, but not limited to, certain metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. The gate 20 may also comprise doped polysilicon and doped polysilicon-germanium alloy materials (i.e., having a dopant concentration from about 1e18 to about 1e22 dopant atoms per cubic centimeter) and polycide materials (doped polysilicon/metal silicide stack materials). Similarly, the foregoing materials may also be formed using any of several methods. Non-limiting examples include salicide methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to evaporative methods and sputtering methods. Typically, the gate 20 comprises a doped polysilicon material or a metal gate material that has a thickness from about 200 to about 1500 angstroms.
The capping layer 22, which may be optional in some embodiments of the invention, may comprise any of several capping materials that will generally comprise hard mask materials. Dielectric capping materials are most common, but are also not limiting. The dielectric capping materials may include, but are not limited to oxides, nitrides and oxynitrides of silicon, but oxides, nitrides and oxynitrides of other elements are not excluded. The dielectric capping materials may be formed using any of the several methods that may be used for forming the gate dielectric 18. Typically, the capping layer 22 comprises a silicon nitride dielectric capping material that has a thickness from 10 to 50 nanometers.
To fabricate the semiconductor structure of
Subsequent to forming the elongated extension regions that include the extension regions 24, the first spacer 26 is formed using a blanket layer deposition and etchback method that (as noted above) will typically and preferably provide the first spacer 26 of the same dielectric material as the capping layer 22. Finally, the fourth semiconductor layer 16 that includes the elongated extension regions that further include the extension regions 24 that in turn are separated by a channel region located beneath the gate 20, is patterned to form the fourth semiconductor layer 16′. Such patterning is typically effected using an anisotropic plasma etch method that uses the gate dielectric 18, the gate 20, the capping layer 22 and the first spacer 26 as a mask.
The foregoing etching of the conformal etch stop layer 28 and the third semiconductor layer 14 to provide the conformal etch stop layer 28′ and the third semiconductor layer 14′ may be effected using methods and materials that are otherwise generally conventional in the semiconductor fabrication art. Included in particular, but also not limiting, are wet chemical etch methods and materials, and dry plasma etch methods and materials. In accordance with disclosure above, anisotropic dry plasma etch methods and materials are generally preferred insofar as anisotropic dry plasma etch methods and materials generally provide straight sidewalls when forming patterned layers.
Within the context of the invention as claimed, the third semiconductor layer 14′, in conjunction with and with respect to the channel portion of the fourth semiconductor layer 16′, may be considered as a channel pedestal.
The foregoing etching of the third semiconductor layer 14′, the second semiconductor layer 12 and the first semiconductor layer 10 may be effected, for example and without limitation, when the first semiconductor layer 10 and the third semiconductor layer 14 comprise a silicon semiconductor material and the second semiconductor layer 12 comprises a silicon-germanium alloy semiconductor material, while using an etchant such as but not limited to an aqueous potassium hydroxide, ethylenediamine pyrocatechol (EDP) or tetramethylammonium hydroxide (TMAH) directionally and crystallographically specific etchant. In particular, silicon is etched directionally (i.e., anisotropically) and crystallographically specifically in the foregoing etchants. These particular alkaline solution etchants are convenient and highly selective etchants for silicon, where a silicon etching reaction proceeds in a <100> or a <110> crystallographic direction, but stops when an etch front reaches a {111} plane. As is illustrated in phantom within the schematic cross-sectional diagram of
Under circumstances where the third semiconductor layer 14/14′ comprises a (111) plane silicon semiconductor material or other semiconductor material, the third semiconductor layer 14″ when etched with the above described etchant provides a plurality of crystallographic plane defined apertures A (i.e., a plurality of counter-opposed apertures) that has a crystallographic plane defined apex angle θ of 109.4 degrees for a (100) wafer, if a source and drain direction is <110>, 70.6 degrees if a source and drain direction is <100>.
For example, and without limitation, when further processing of the semiconductor structure of
Also for example, and also without limitation, when further processing of the semiconductor structure of
Typically and preferably, the epitaxial halo layer 32 is formed to a thickness from 7 to 20 nanometers, where such a thickness is intended as a sufficient thickness to fill the apertures A within the third semiconductor layer 14″ that are illustrated within the schematic cross-sectional diagram of
Typically and preferably, the conformal etch stop layer 28′ when comprising a silicon oxide material may be stripped selectively with respect to the first spacer 26 and the capping layer 22 when comprising a nitride material, by using an aqueous hydrofluoric acid etchant at elevated temperature.
The epitaxial source and drain layers 34 may be formed using epitaxial methods and materials that are otherwise generally conventional in the semiconductor fabrication art.
While by no means intending to limit the embodiment or the invention, under circumstances where the metal oxide semiconductor field effect transistor structure whose schematic cross-sectional diagram is illustrated in
In addition, under circumstances where the metal oxide semiconductor field effect transistor structure whose schematic cross-sectional diagram is illustrated in
The salicide method includes: (1) forming a blanket silicide forming metal layer upon the semiconductor structure of
Typically, the silicide layers 38 comprise a nickel silicide material or a cobalt silicide material that has a thickness from about 10 to about 50 nanometers, although this particular illustrative embodiment is not intended to be so limited. In addition, the silicide layers 38 may comprise different silicide material for p-MOSFET devices and n-MOSFET devices, or alternatively source regions and drain regions with respect to gates, although such is also not intended as a limitation of the embodiment or of the invention.
The metal oxide semiconductor field effect transistor structure whose schematic cross-sectional diagram is illustrated in
In addition, although the schematic cross-sectional diagram of
The preferred embodiment is illustrative of the invention rather than limiting of the invention. Revisions and modifications may be made to methods, materials, structures and dimensions of a metal oxide semiconductor field effect transistor in accordance with the preferred embodiment while still providing a metal oxide semiconductor field effect transistor and a method for fabrication thereof in accordance with the invention, further in accordance with the accompanying claims.
Claims
1. A semiconductor structure comprising:
- a gate located over a gate dielectric, the gate dielectric in turn located over a channel region within a semiconductor substrate that separates a plurality of source regions and drain regions within the semiconductor substrate; and
- at least one halo region located at least in-part beneath the channel region and physically separated from the gate dielectric, wherein the at least one halo region comprises two counter-opposed halo regions each having a triangular shape defined at least in-part by a crystallographic plane of the semiconductor substrate.
2. The semiconductor structure of claim 1 wherein the semiconductor substrate comprises a bulk semiconductor substrate.
3. The semiconductor structure of claim 1 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.
4-5. (canceled)
6. The semiconductor structure of claim 1 wherein:
- the semiconductor structure comprises a p-MOSFET;
- the semiconductor substrate comprises at least in-part a silicon semiconductor material;
- the channel region comprises at least in-part a silicon-germanium alloy semiconductor material;
- the plurality of source regions and drain regions comprises at least in-part a silicon-germanium alloy semiconductor material; and
- the at least one halo region comprises at least in-part a silicon-germanium alloy semiconductor material.
7. The semiconductor structure of claim 1 wherein:
- the semiconductor structure comprises an n-MOSFET;
- the semiconductor substrate comprises at least in-part a silicon semiconductor material;
- the channel region comprises at least in-part a silicon-germanium alloy semiconductor material;
- the plurality of source regions and drain regions comprises at least in part a silicon-carbon alloy semiconductor material; and
- the at least one halo region comprises at least in-part a silicon-carbon alloy semiconductor material.
8-20. (canceled)
21. A semiconductor structure comprising:
- a gate located over a gate dielectric, the gate dielectric in turn located over a channel region within a semiconductor substrate that separates a plurality of source regions and drain regions within the semiconductor substrate; and
- at least one halo region located at least in-part beneath the channel region and physically separated from the gate dielectric, wherein the semiconductor substrate comprises at least in-part a silicon semiconductor material, the channel region comprises at least in-part a silicon-germanium alloy semiconductor material, the plurality of source regions and drain regions comprises at least in-part a silicon-germanium alloy semiconductor material, and the at least one halo region comprises at least in-part a silicon-germanium alloy semiconductor material.
22. The semiconductor structure of claim 21 wherein the semiconductor substrate comprises a bulk semiconductor substrate.
23. The semiconductor structure of claim 21 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.
24. The semiconductor structure of claim 21 wherein the at least one halo region comprises a single halo region comprising a bow-tie shape.
25. The semiconductor structure of claim 21 wherein the at least one halo region comprises two counter-opposed halo regions each having a triangular shape defined at least in-part by a crystallographic plane of the semiconductor substrate.
26. A semiconductor structure comprising:
- a gate located over a gate dielectric, the gate dielectric in turn located over a channel region within a semiconductor substrate that separates a plurality of source regions and drain regions within the semiconductor substrate; and
- at least one halo region located at least in-part beneath the channel region and physically separated from the gate dielectric, wherein the semiconductor substrate comprises at least in-part a silicon semiconductor material, the channel region comprises at least in-part a silicon-germanium alloy semiconductor material, the plurality of source regions and drain regions comprises at least in part a silicon-carbon alloy semiconductor material, and the at least one halo region comprises at least in-part a silicon-carbon alloy semiconductor material.
27. The semiconductor structure of claim 26 wherein the semiconductor substrate comprises a bulk semiconductor substrate.
28. The semiconductor structure of claim 26 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.
29. The semiconductor structure of claim 26 wherein the at least one halo region comprises a single halo region comprising a bow-tie shape.
30. The semiconductor structure of claim 26 wherein the at least one halo region comprises two counter-opposed halo regions each having a triangular shape defined at least in-part by a crystallographic plane of the semiconductor substrate.
Type: Application
Filed: Apr 20, 2009
Publication Date: Oct 21, 2010
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Huilong Zhu (Poughkeepsie, NY), Qingqing Liang (LaGrangeville, NY), Jing Wang (Fishkill, NY)
Application Number: 12/426,467
International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101);