Method of Manufacturing a Fast Recovery Rectifier
A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily doped film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.
This application is a divisional of U.S. patent application Ser. No. 11/801,023, filed on May 8, 2007, which claims priority to U.S. provisional patent application Ser. No. 60/799,252 filed May 10, 2006 and entitled “Fast Recovery Rectifiers”, from which priority is claimed under 35 U.S.C. §119(e) and which applications are incorporated by reference herein in their entireties.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates generally to the structures of a fast recovery rectifier. This invention discloses the method of reducing the reverse recovery time from a conventional fast recovery rectifier by either introducing the Schottky structure at the front and/or the back of the substrate or introducing the junction termination layer to reduce the total space charge of the p-n junction. Furthermore, this invention also provides the low cost manufacturing of a very fast recovery rectifier.
2. Description of Related Art
The diffusion to the doped substrate 100 is generally using opposite polarity species at the p-n junction 103. The depth of this p-n junction 103 must be deeper than the surface damage region for the reduction of the leakage current. The diffusion to the doped substrate 100 is generally using the same polarity as at the backside layer 101. The passivation layer 104 can be formed after the formation of the p-n junction 103 as well as the life time killer process. The irradiation of the electrons and or other species can be done after the process of the wafer or even in the packaged parts. The passivation layer 104 can be done by conventional glass passivation process or multiple CVD process. The top metal layer 105 is deposited, evaporated, sputtered, or plated along with the top of the p-n junction 103. The bottom layer 105B metallization is to be done by similar metallization process or by nickel plating. After the completion of the process, the wafer is diced into chips for assembly.
U.S. Pat. No. 6,261,874, Francis and Ng disclosed the fast recover diode structure with both Beam Radiation defects and He implanted defects to reduce the reverse recovery time. With this structure, the soft recovery time can result. U.S. Pat. No. 6,486,524 Ahmed disclosed the complicated structure using p-n junction as well as the Al or Pd Schottky for the fast reverse recovery time. U.S. Pat. No. 6,603,153, Francis and Ng disclosed the fast recovery rectifier structure that is similar to U.S. Pat. No. 6,261,875. U.S. Pat. No. 6,699,755 Bol disclosed a fast recovery diode structure similar to U.S. Pat. No. 6,486,524. U.S. Pat. No. 6,870,199 Yoshikawa et al disclosed the multiple life time control region for the improvement of di/dt caused breakdown. U.S. Pat. No. 6,927,141 Andoh et al disclosed the termination structure by using equal metal ring.
SUMMARY OF THE INVENTIONIt is therefore an objective of the present invention to provide a low cost and the improvement of the process and device structures. By using the common fast recovery rectifier, a termination structure using glass and/or CVD process is the basic structure to begin with. The substrate is an sawed or non-polished substrate instead of polished wafers for the reduction of the cost. Deep diffusion of opposite polarity to the substrate in one side and the same polarity in the other side are performed. The depth of the diffusion is from less than 10 micron to over 20 microns depending on the surface damage region of the unpolished wafer. This invention adds an etched region with either wet etches or wet/dry etches for the provision of the Schottky contact. This etched region can be a round shape, hexagon, stripe or other shapes. The metallization is then provided for the ohmic contact of the heavily doped rough surface and for Schottky contact of the etched smooth region. The purpose of the Schottky contact is to absorb the minority carrier injections at the forward bias, thus the reverse recovery time is reduced. The similar structure at the other side can also be added for the reduction of the minority carriers. Thus the reduction of the reverse recovery time can be further reduced. In order to improve the reverse recovery time, the conventional method is using the epitaxial wafers and then using life time killing method. The heavily doped substrate is used to decrease the forward voltage drop due to series resistance and in the mean time to reduce the lifetime by reducing the thickness of the lightly doped active epitaxial region. The second objective of this invention is to form a reduced p-n junction space charge region (or depletion region) by using a thin and highly doped film of the same polarity as the top junction layer which has opposite polarity to the base silicon substrate. This early termination of the junction charge region reduces the total space charge of the p-n junction, thus the smaller reverse recovery time can be achieved. This method can be used in conjunction with the life time killers and/or with the Schottky structures.
The p-n junction 103 is deposited, evaporated, sputtered, or plated along with the top metal layer 105. The p-n junction 103 is terminated early by a very thin and heavily doped layer 110 with the same polarity as 103. This layer 105 can be finished by contact metal and/or barrier metal and/or top metal for soldering or wire bonding. The backside layer 101 is to be done by similar metallization process or by nickel plating. After the completion of the process, the wafer is diced into chips for assembly.
Embodiment TwoIn this embodiment, after the formation of the p-n junction anode layer, the life time killer such as Pt, Au or other species with proper thermal treatment can be added to the wafer. On the other hand, after the top layer diffusion, the deep etched structure is to be done by etching, preferably by wet etch prior to the passivation process. The passivation layer 104 is done either by the conventional glass passivation or multiple CVD layers method.
Next, the top metal layer 105 is then opened for the metallization. The top metal layer 105 can be done by the Schottky contact metallization with either Pt, Au, Ni, Mo, W, Cr, Ti etc. followed by the barrier metal layer such as TiW, TiN, and the top metal such as Al, Ag, etc. for either wire bond or soldering. The backside layer 101 can be done by the implantation of similar polarity to the silicon substrate or omitted if the substrate is heavily doped. The bottom layer 105B is done either by Ti—Ni—Ag or Cr—Au or by Ni plating. After the completion of the process, the wafer is then ready for the dicing and assembly.
Referring to embodiments four and five to be described below. The planner termination structure for high voltage guard ring either is using single or multiple guard rings for the epitaxial wafer. The epitaxial layer or multiple epitaxial layers is deposited on the similar polarity substrate under the condition—the implant dose of the opposite polarity region ranging from less than 1E10 per cm2 to 1E16 per cm2 with the implant energy from 100 V to over 100 KeV and time 10 seconds to one hour with the temperature from 600 to 1100 deg C. to form the p-n junction or the Schottky region by blocking the implant species, and the implant condition for the guard ring can be the same as the opposite polarity base material.
Embodiment FourIn this embodiment, the purpose of diode termination layer 103A is to terminate the p region into the narrower space, thus the total charge will be smaller. The lifetime killer such as Pt, Au, or can be added before or after the process. The top metal layer 105 can be either formed by Au, Pt, W, Mo Cr, Ni, Ti and other metal or used to form the silicide.
Next, the diffusion barrier such as TiW, TiN or other layer is done before the contact layer of the 105 is deposited. The contact layer of the 105 can be either Al for wire bonding or Ag or Au for soldering. The backside layer 101 is implanted or diffused with the similar polarity to the doped substrate 100. If the resistivity of the doped substrate 100 is lower enough, this layer 101 can be eliminated. The bottom layer 105B can be made by the similar metallization process used for the top metal layer 105 or by using convention method such as Cr—Au, Ti—Ni—Ag or even with Nickel plating.
Embodiment FiveThe fast recovery rectifier of this invention is accomplished by one or more of following conditions;
Schottky structure is used with the standard fast recovery rectifier by using Pt, Au and/or radiation lifetime killer.
Reduced p-n junction is used with the standard fast recovery rectifier with Pt, Au, and/or radiation lifetime killer.
Reduced p-n junction is used with Schottky structure and standard fast recovery rectifier with Pt, Au and/or radiation lifetime killer.
Reduced p-n junction alone.
Reduced p-n junction is used with Schottky structure.
Reduced p-n junction is used with Schottky structure and standard fast recovery rectifier with Pt, Au and/or radiation lifetime killer with epitaxial substrates.
The fast recovery rectifier of this invention uses the Pt, Au and/or radiation lifetime killer, and combine with Schottky structure to reduce the minority carriers at the forward bias and in the rectifying process condition. The fast recovery rectifier use unpolished rough surface doped substrate and rough diffusion to provide a low cost. This invention is to form a reduced p-n junction space charge region by using a thin and very high doped film of the same polarity as the top junction layer which is opposite polarity to the base silicon substrate. This early termination of the junction charge region reduces the total space charge of the p-n junction, thus the smaller reverse recovery time can be achieved. This method can be used in conjunction with the life time killers and/or with the Schottky structures.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims
1. A method of manufacturing a rectifier, comprising:
- forming a first semiconductor layer with a first type of dopant;
- depositing a second semiconductor layer of a second type of dopant above said first semiconductor layer, wherein said first type of dopant and said second type of dopant have opposite polarity;
- depositing a thin film of a third semiconductor layer of said second type of dopant immediately above said second semiconductor layer, wherein doping concentration of said third semiconductor layer is higher than doping concentration of said second semiconductor layer to create an early termination at the interface of said second semiconductor layer and said third semiconductor layer; and
- depositing a metal layer above said third semiconductor layer, wherein the interface between said metal layer and said third semiconductor layer is an ohmic contact.
2. The method of claim 1, further comprising epitaxial forming a fourth semiconductor layer with said first type of dopant between said first semiconductor layer and said second semiconductor layer, wherein doping concentration of said fourth semiconductor layer is lower than doping concentration of said first semiconductor layer.
3. The method of claim 1, wherein said first type of dopant is n-type.
4. The method of claim 1, wherein said first semiconductor layer further comprising one or more lifetime killer materials including Pt or Au.
5. The method of claim 1, wherein depositing a thin film of said third semiconductor layer further comprises performing an implantation.
6. The method of claim 5, wherein performing implantation includes using implant dose from about 1.0e12 per cm2 to about 1.0e15 per cm2.
7. The method of claim 5, wherein performing implantation includes using implant energy from about 500 eV to about 50 KeV.
8. The method of claim 5, wherein doping concentration of said second semiconductor layer is approximately 2 to 10 times of said first semiconductor layer.
9. The method of claim 1, wherein depositing a thin film of said third semiconductor layer further comprises performing a diffusion.
10. The method of claim 9, wherein performing diffusion includes using diffusion temperature from about 700° C. to about 1100° C.
11. The method of claim 9, wherein performing diffusion includes diffusion time from about 60 second to about 1 hour.
12. The method of claim 9, wherein junction voltage between said first semiconductor layer and said second semiconductor layer is from about 0.5 eV to about 0.9 eV.
13. The method of claim 2, wherein said second semiconductor layer which is above said forth semiconductor layer is formed by performing implantation with implant dose from about 1.0e10 per cm2 to about 1.0e16 per cm2 and implant energy from about 100 V to about 100 KeV and time from about 10 seconds to about 1 hour and temperature from about 600° C. to about 1100° C.
Type: Application
Filed: Dec 4, 2010
Publication Date: Mar 31, 2011
Inventor: Ho-Yuan Yu (Saratoga, CA)
Application Number: 12/960,488
International Classification: H01L 21/20 (20060101);