SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER AND METHOD
Disclosed is a method for forming a buried material layer in a semiconductor body, and a semiconductor arrangement including a buried material layer.
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One aspect of the disclosure relates to a method for forming a buried material layer in a semiconductor body. SOI substrates include a buried insulation layer arranged between two semiconductor layers. For forming an SOI substrate different methods are known.
In a first method a thin semiconductor layer is bonded to the oxidized surface of a semiconductor substrate using a wafer bonding method. The thin semiconductor layer may be obtained by cutting of a thin layer of a semiconductor substrate using the “Smart-Cut” method.
In a second method oxygen is implanted into a semiconductor substrate followed by a temperature process. Due to the temperature process an oxide layer is formed in the region of the substrate into which the oxygen atoms have been implanted. In this method the depth of the buried oxide layer is dependent on the implantation energy of the implantation process, with the maximum depth being limited by the maximum available implantation energy.
For these and other reasons there is a need for the present invention.
SUMMARYOne embodiment relates to a method for forming a buried material layer in a semiconductor body, the method including: providing a semiconductor body having a first side, and having at least one first trench extending from the first surface into the semiconductor body, the at least one first trench having a bottom, and having at least one sidewall; forming a first material layer on the bottom of the at least one trench, material layer leaving at least one segment of at least one sidewall uncovered; filling the at least one first trench by epitaxially growing a semiconductor material from at least one uncovered sidewall segment.
One embodiment relates to a semiconductor arrangement including: a semiconductor body having a first surface; a buried material layer in the semiconductor body. The buried material layer is arranged distant to the first surface, a monocrystalline semiconductor material is arranged between the material layer and the first surface, and a monocrystalline semiconductor material adjoins the material layer in a lateral direction of the semiconductor body.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The drawings should help to understand the basic principle, so that only features necessary for understanding the basic principle are illustrated. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
Referring to
In the example illustrated, the first trench 10 extends from the first surface 101 in a vertical direction into the semiconductor body 100. First trench 10 has a bottom 11, and has sidewalls 12, 13. Sidewalls 12, 13 may be vertical sidewalls, or may be tapered sidewalls. “Tapered” means that the sidewalls 12, 13 are inclined compared to a vertical direction of the semiconductor body, with an angle between the sidewalls 12, 13 and the vertical direction ranging between 0° and 30°, in particular between 0° and 10°. The sidewalls may have a positive or a negative taper, where in the first case the trenches are getting wider in the direction of the first surface, and where in the second case the trenches are getting narrower in the direction of the first surface. Tapered sidewalls of the first trench 10 are illustrated using dash-dotted lines in the drawings.
The first trench 10 may be produced using any known method for producing trenches in a semiconductor body, these methods may involve forming a patterned mask (not illustrated) on the first surface 101 of the semiconductor body 100, and etching the trench in those regions not covered by the mask. A depth d of the first trench 10 is, for example, in the range between 100 nm and 20 μm, and the width of the first trench 10 is, for example, in the range between 50 nm and 10 μm. The depth d of the first trench 10 is its dimension in the vertical direction. In connection with the present disclosure the width w of trench 10 is its smallest lateral dimension. This will be explained in detail with reference to
According to a first embodiment trench 10 illustrated in
Referring to
An oxide layer as the first material layer 21 is, for example, formed by employing a HDP (high density plasma) deposition process. HDP deposition processes are plasma supported deposition/sputter processes that are commonly known, so that no further explanations are required. In a HDP process the deposition rates for depositing material on horizontal surfaces of a semiconductor body, such as bottom 11, and on vertical, or on compared to the vertical direction tapered surfaces, such as sidewalls 12, 13, are different. The HDP process is, in particular, selected to have a higher deposition rate on the bottom 11 than on the sidewalls 12, 13, where in an ideal case no material is deposited on the sidewalls 12, 13. If material is also deposited on the sidewalls 12, 13 then this material may be removed from the sidewalls 12, 13 by an etching process, such as an isotropic etching process. This etching process also etches the first material layer on the bottom 11. However, since due to the properties of the HDP process the first material layer 21 on the bottom 11 is thicker than the material layer deposited on the sidewalls 12, 13 the layer on the sidewalls 12, 13 is completely removed before the first material layer 21 on the bottom 11 is completely removed. As a result the structure illustrated in
As an alternative a sputter process or a vapor deposition process may be used for forming the first material layer.
Alternatively to using a HDP process, a sputter or a vapor deposition process, a first material layer 21 that is an oxide layer may be formed using a thermal oxidation process. During the oxidation process the sidewalls 12, 13 may be covered by a protection layer (not illustrated) that leaves the bottom 11 uncovered. Through this, a first material layer including an oxide is formed on the bottom 11 of the trench 10, but not on the sidewalls 12, 13. The protection layer covering the sidewalls is, for example, a nitride layer. The protection layer is, for example, formed by first depositing the protection layer on the whole surface of the trench, i.e., on the bottom 11 and the sidewalls, and by then removing the protection layer from the bottom 11 of trench. According to an embodiment an anisotropic etching process is used for removing the protection layer from the bottom of the trench 10. Having formed the material layer on the bottom of the trench 10, the protection layer may be removed from the sidewalls using, for example, an isotropic etching process.
Referring to
In subsequent method steps, the result of which is illustrated in
The lateral epitaxial growth process used for filling the trench results in an essentially defect free monocrystalline semiconductor layer above the first material layer. The epitaxial process is, in particular, a selective epitaxial process (SEG, selective epitaxial growth). In a selective epitaxial process the process parameters—such as kind of process gases, temperature, pressure, and gas flow—are adjusted such that a semiconductor layer is selectively grown on a first surface, such as the semiconductor material on the sidewalls 12, 13, but is not grown or is grown with a reduced rate on a second surface, such as on the first material layer 21 on the bottom 11 of the trench. In selective epitaxial processes the temperature is, for example, below 1050° C., or even below 1000° C., and is therefore somewhat lower than in a “usual” epitaxial process. The process gas in a selective epitaxial process includes a precursor for growing the semiconductor layer, and an etching gas that etches the semiconductor layer from the surface on which no epitaxial growth or on which epitaxial growth with a reduced growth rate is desired.
Suitable precursor gases for growing a silicon layer are, for example, dichlorosilane or trichlorosilane. The material on which a semiconductor material should not be grown or should be grown with reduced growth rate is, for example an oxide layer. Suitable additional process gases in such a process are, for example hydrochloric acid (HCl) and hydrogen (H2). In such a process the precursor effects the growth of a semiconductor layer on a semiconductor material, such as on sidewalls 12, 13 of the first trench 10, and on an oxide first material layer 21 at the bottom, while the hydrochloric acid at the same time etches the grown semiconductor layer from the first material layer. By adjusting the flow-rate of the etching gas the growth rate on the first material layer 21 may be adjusted.
According to another embodiment the surfaces are not exposed to the precursor and to the etching gas at the same time, but the surfaces are alternatingly exposed to the precursor and the etching gas.
At the end of these processes first material layer 21 is buried below mono crystalline epitaxially grown semiconductor material 31′. The doping concentration of the epitaxially grown semiconductor material 31′ may correspond to the doping concentration of the semiconductor body 100 in regions adjacent to the sidewalls 12, 13. However, the doping concentration of the epitaxially grown semiconductor material 31′ could also be different from the doping concentration of the surrounding semiconductor material. At the end of the processes illustrated in
In further method steps, that are optional and the result of which is illustrated in
In the method according to
The deposition rate is essentially independent of the depth of the first trench 10. The method is therefore particularly suitable for forming buried material layers 21 that are deeply buried in the semiconductor body.
When epitaxially growing the semiconductor material 31′ on the sidewalls 12, 13 of the trench 10 in a worst case scenario voids may occur in the region of the first material layer 21. However, those voids may be avoided or may at least largely be avoided by forming the first trench 10 with tapered sidewalls.
When filling the first trench 10 by epitaxially growing semiconductor material on uncovered segments of the sidewalls 12, 13 semiconductor material is also grown on uncovered first surface 101. The resulting structure is illustrated in
In the methods illustrated in
In
First and second sidewalls 12, 13 illustrated in
As it has been explained hereinabove trench width w has a significant influence on the deposition time. Reference numbers 14 and 15 in
It goes without saying that more than one buried first material layer 21 can be produced in the semiconductor body 100 by forming several first trenches 10, and forming first material layers on the bottom of these trenches. This is illustrated in
Although the first trenches 10 according to
Rectangular trenches have four sidewalls, where with an increasing ratio of l/w the trench is mainly filled by the semiconductor material grown on the longitudinal sidewalls 12, 13. Hexagonal trenches have six sidewalls.
According to another embodiment (not illustrated) first trench 10 is an elongated trench that in the horizontal section plane has a meander-like geometry or a spiral geometry.
The first trenches 10 in the horizontal direction of the semiconductor body 100 are separated by mesa regions 41. In the following, mesa regions 41 are those regions of the semiconductor body 100 that remain after forming the first trenches 10.
Dependent on whether a first material layer is deposited on the first surface 101 (see 22 in
Referring to
Referring to
The method steps for forming the second material layers 23 on the bottom 51 of the second trenches 50 may correspond to the method steps for forming the first material layers 21 that have been explained with reference to
Referring to
In the example according to
When filling the second trenches 50 by epitaxially growing a semiconductor material on sidewalls of the second trenches 50 these material layers 24 prevent semiconductor material from being grown on the first surface 101, i.e., on top of the mesa regions remaining after forming the second trenches 50.
Optionally the semiconductor arrangement illustrated in
In the two methods according to
The buried material layer, which in the embodiments according to
Referring to
Referring to
Like in the method according to
Referring to
The buried material layer 20 is arranged distant to the first surface 101, a monocrystalline semiconductor material being arranged between the buried material layer 20 and the first surface 101, Further, a monocrystalline semiconductor material adjoins the buried material layer 20 in a lateral direction of the semiconductor body 100, i.e., the buried layer 20 does not extend to the edge (not illustrated) of the semiconductor body 100 in the lateral direction.
Referring to
Referring to
Referring to
In the method according to
Referring to
On the bottom 11 of the first trench 10 the first material layer 21 is formed. Subsequently to forming the first material layer 21 the first trench 10 is filled by epitaxially growing a semiconductor material on at least one of the sidewalls 12, 13 of the first trench 10. The first material layer 21 adjoins the horizontal second section of material layer 70, so that material layer 70 and first material layer 21 completely enclose a semiconductor region of the semiconductor body 100.
A method for forming L-shaped material layer 70 will now be explained with reference to
Referring to
Referring to
Protective layer 91 is composed, in one embodiment, of a material with respect to which the mask layer 71 and the material layers 72 can be etched selectively. In this connection, “selective etching” should be understood to mean that the foreign layers 71, 72 can be etched by an etchant that does not etch the protective layer 91 or etches it to a significantly smaller extent than the layers 71, 72. The protective layer 91 is composed of carbon, for example, and can be deposited in a CVD process (CVD=Chemical Vapor Deposition) by pyrolysis of methane (CH4). During the pyrolysis, from the methane a solid layer of carbon (C), which forms the protective layer 301, and volatile hydrogen (H2) is generated. Material layers 71, 72 that are, for example, composed of an oxide, such as silicon dioxide, can be etched selectively with respect to such a protective layer 91 composed of carbon, for example, by using a solution containing at least one of hydrofluoric acid, and ammonium fluoride.
Referring to
For removing layer 72 from the inner sidewalls via the opening 92 produced in the protective layer 91, material layer 72 is subjected to an etching material which etches the material layer 72 selectively with respect to the protective layer 91 and the semiconductor body 100. When using silicon as material of the semiconductor body 100, a carbon layer as the protective layer 91 and a silicon oxide layer as the foreign material layer 72, the etching material is, for example, a solution containing hydrofluoric acid or containing ammonium fluoride. If the opening 92 of the protective layer 91 is situated offset with respect to the inner sidewall in a lateral direction of the semiconductor body 100, then the etching material firstly removes that section of the mask layer 71 which is situated directly on the front surface 101 before etching material 72 on the inner sidewalls.
The etching materials mentioned each have a high selectivity with respect to a carbon layer as protective layer 301 and a semiconductor body 100 composed of silicon, that is to say that they have a high etching rate with respect to the layers 71, 72 and only a low etching rate with respect to the semiconductor body 100 and the protective layer 91. A ratio of the etching rate of the material layers 71, 72 to the etching rate of the semiconductor body 100 lies, for example, in the range of 500:1 to 10 000:1 or higher. One variant of the method explained provides for reducing the selectivity of the etching material with respect to the material of the semiconductor body 100. In the case of the abovementioned solutions containing hydrofluoric acid or containing ammonium fluoride, this can be done, for example, by adding nitric acid. The result of this reduction of the etching selectivity is that during the etching process the semiconductor body 100 is also etched in the region of the second sidewall 12, which leads as a result to a sidewall that is tapered with respect to the vertical. Such a tapered sidewall facilitates later filling of the trench with a semiconductor material by epitaxially growing a semiconductor layer.
After removing material layer 72 from the inner sidewall protective layer 91 is removed, and a further material layer 73 is formed on the bottom of the trench 81. Forming material layer 73 may, for example, be formed using any of the methods that have been explained with reference to
Referring to
Finally, the arrangement including the semiconductor body 100 and the mask layer 71 on its first surface is planarized down to the first side, thereby removing mask layer 71. The result of this is illustrated in
According to one example layers 72, 73 that have been formed using the method steps according to
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims
1. A method for forming a buried material layer in a semiconductor body, the method comprising:
- providing a semiconductor body having a first surface, and having at least one first trench extending from the first surface into the semiconductor body, the at least one first trench having a bottom, and having at least one sidewall;
- forming a first material layer on the bottom of the at least one trench, the first material layer leaving at least one segment of at least one sidewall uncovered; and
- filling the at least one first trench by epitaxially growing a semiconductor material from at least one uncovered sidewall segment.
2. The method of claim 1, wherein the first material layer is one of an electrically insulating layer, and an electrically conducting layer.
3. The method of claim 1, wherein the electrically insulating layer is an oxide layer, a nitride layer, an oxy-nitride layer, or a stack of one or more of these materials.
4. The method of claim 1, wherein the electrically conducting layer is a metal layer, a carbide layer, a silicide layer, a doped semiconductor layer, or a stack of one or more of these materials.
5. The method of claim 1, wherein forming the first material layer on the bottom of the at least one trench comprises:
- depositing the first material layer on the bottom of the trench using a deposition process.
6. The method of claim 5, further comprising:
- depositing the first material layer on the at least one sidewall;
- removing the first material layer from at least one segment of at least one sidewall before filling the at least one first trench, thereby obtaining the at least one uncovered sidewall segment.
7. The method of claim 5, wherein the deposition process is selected to have a higher deposition rate on the bottom of the at least one trench than on the at least one sidewall.
8. The method of claim 7, wherein the deposition process is an HDP process, a sputter process, or a chemical vapor deposition process.
9. The method of claim 1, wherein forming the first material layer on the bottom of the least one trench involves leaving the first surface uncovered; and
- wherein semiconductor material is grown on the first surface during the step of filling the at least one first trench.
10. The method of claim 1, further comprising:
- forming the first material layer on the first surface while forming the first material layer on the bottom of the at least one first trench, the first material layer preventing semiconductor material from being grown on the first surface when filling the at least one first trench;
- removing the first material layer from the first surface after filling the at least one first trench.
11. The method of claim 12, wherein removing the first material layer from the first surface involves one of an etching process, and a polishing process.
12. The method of claim 1, wherein the at least one sidewall of the at least one first trench is tapered.
13. The method of claim 12, wherein the taper angle is between 0° and 30° or between 0° and 10°.
14. The method of claim 1, further comprising:
- forming a plurality of first trenches, the trenches being distant to one another and separated from one another by mesa regions;
- after filling the first trenches: a) forming second trenches in the mesa regions at least once, the second trenches extending from the first surface in a vertical direction into the semiconductor body, the second trenches each having a bottom, and having at least one sidewall; b) forming second material layers on the bottom of the second trenches, second material layers leaving at least one segment of at least one sidewall of each of the second trenches uncovered; c) filling the second trenches by epitaxially growing a semiconductor material on at least one uncovered sidewall segment of each second trench.
15. The method of claim 14, wherein method steps a) to c) are repeated until the mesa regions left after forming the first trenches are completely removed by forming the second trenches and are replaced by the epitaxially grown semiconductor material.
16. The method of claim 14, wherein the first and the second material layers are of the same material.
17. The method of claim 14, wherein the bottom of the second trenches in the vertical direction lies between the level of an upper surface of the first material layers and below the level of a lower surface of the first material layers.
18. The method of claim 14, wherein the second trenches are formed such that they overlap the first material layers in a lateral direction of the semiconductor body.
19. The method of claim 18, wherein the second trenches are etched, and wherein the first material layers act as etch stop when forming the second trenches.
20. The method of claim 1, wherein the at least one first trench in a horizontal plane has one of a rectangular, an elliptical or a polygonal geometry.
21. The method of claim 1, wherein the at least one first trench in a horizontal plane has one of a ring-shaped, a meander-like or a spiral geometry.
22. A semiconductor arrangement comprising:
- a semiconductor body having a first surface;
- a buried material layer in the semiconductor body;
- the buried material layer being arranged distant to the first surface, a monocrystalline semiconductor material being arranged between the material layer and the first surface, and a monocrystalline semiconductor material adjoining the material layer in a lateral direction of the semiconductor body.
23. The semiconductor arrangement of claim 22, wherein the buried material layer is completely surrounded by a monocrystalline semiconductor material in the semiconductor body.
24. The semiconductor arrangement of claim 22, wherein the semiconductor body has a first surface and the first material layer is essentially parallel to the first surface.
25. The semiconductor arrangement of claim 22, wherein the material layer is a dielectric layer.
26. The semiconductor arrangement of claim 22, wherein the material layer comprises a number of first and second material layers that are arranged next to one another in the lateral direction.
27. The semiconductor arrangement of claim 22, further comprising:
- a further material layer adjoining the material layer and extending in a vertical direction.
28. The semiconductor arrangement of claim 27, wherein the further material extends to the first surface and completely surrounds a semiconductor region between the material layer and the first side.
Type: Application
Filed: Dec 23, 2009
Publication Date: Jun 23, 2011
Applicant: Infineon Technologies Austria AG (Villach)
Inventors: Hans-Joachim Schulze (Taufkirchen), Anton Mauder (Kolbermoor), Helmut Strack (Munich)
Application Number: 12/646,503
International Classification: H01L 27/12 (20060101); H01L 21/762 (20060101);