FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR
A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
This application is a continuation of U.S. patent application Ser. No. 11/240,440, filed Sep. 29, 2005, the entire contents of which are hereby incorporated by reference herein.
FIELD OF THE INVENTIONThe invention is in the field of Field-Effect Transistors.
PRIOR ART AND RELATED ARTThe continuing trend in the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors is to scale the transistors. Examples of transistors having reduced bodies along with tri-gate structures are shown in US 2004/0036127. Other small transistors are delta-doped transistors formed in lightly doped or undoped epitaxial layers grown on a heavily doped substrate. See, for instance, “Metal Gate Transistor with Epitaxial Source and Drain Regions,” application Ser. No. 10/955,669, filed Sep. 29, 2004, assigned to the assignee of the present application.
The ability to continue scaling CMOS transistors to even smaller geometries is hindered by the off-state leakage current. Off-state current reduces the switching efficiency and robs system power. This is particularly significant in planar CMOS transistors, where substrate leakage paths account for most of the current flow in the off state. While three-dimensional structures such as tri-gates and fin-FETs are more scalable, since they have more effective electrostatic control, there still remains a leakage path in the channel.
One structure for providing a more completely wrapped around gate is described in “Nonplanar Semiconductor Device with Partially or Fully Wrapped Around Gate Electrode and Methods of Fabrication,” U.S. patent application Ser. No. 10/607,769, filed Jun. 27, 2003.
A process for fabricating CMOS field-effect transistors and the resultant transistors are described. In the following description, numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as cleaning steps, are not described in detail, in order to not unnecessarily obscure the present invention. Also, in the description below, the fabrication of a single transistor is described. As will be appreciated in the typical integrated circuit, both n and p channel transistors are fabricated.
In one embodiment, transistors are fabricated on a buried oxide layer (BOX) 20 which is disposed on a silicon substrate 21 shown in
As will be seen, the BOX is seeded through ion implantation beneath the channel region of a transistor to make the oxide more readily etchable than the overlying silicon body. An electrically inactive species is implemented so as to not alter the electrical characteristics of the semiconductor body. Then, after removal of the BOX beneath the channel, a gate insulator and gate are formed entirely around the channel. Referring to
A protective oxide is disposed on the silicon layer 24 followed by the deposition of a silicon nitride layer (both not shown). The nitride layer acts as a hard mask to define silicon bodies such as the silicon body 25 of
An oxide (not shown) which subsequently acts as an etchant stop is formed over body 25. A polysilicon layer is formed over the structure of
Now, a layer of silicon nitride is conformally deposited over the structure of
Following the implantation of the main source and drain region, the silicon body 25, to the extent that it extends beyond the spacers 38, receives a silicide or salicide layer 39 as is often done on exposed silicon in field-effect transistors.
An annealing step to activate the source and drain dopant is used, also commonly used cleaning steps common in the fabrication of a field-effect transistor are not shown.
A dielectric layer 40 is now conformally deposited over the structure of
After the deposition and planarization of the dielectric layer 40, a wet etch is used to remove the dummy polysilicon gate 30, leaving the opening 45, as shown in
Referring to
Ions seeded into the upper portion of BOX 20, shown as region 20a, cause BOX 20 to be more readily etched and to provide better selectivity between the region 20a versus the body 25 and the non-implanted regions of BOX 20. The ions alter the crystalline nature of BOX 20, in effect, amorphizing or modifying the structure making it less resistant to selected chemistry without making body 25 or non-implanted regions of the BOX 20 more readily etched. More specifically, by selecting suitable ions and a suitable wet etchant, the implanted region 20a is etched more readily in the presence of the wet etchant compared to the body 25 or unexposed portions of the BOX 20, allowing the implanted portion of the BOX 20 (region 20a), including beneath the body 25 to be removed without substantially affecting the dimensions of the body 25. A discussion of pre-etch implantation may be found in US2004/0118805. Wet etchant discrimination ratio of 6-1 between implanted silicon dioxide and non-implanted silicon dioxide are achievable.
Ions selected for the implantation shown in
Following the implantation, a wet etch is used to remove the region 20a including the region 20a under the body 25. Many wet chemical etchants are known to be effective and controllable on such thin film materials. As would be apparent to one skilled in the art, they may be appropriately matched with substrate and thin film materials, such as those above, to provide desirable selective etching. Suitable etchants include but are not limited to phosphoric acid (H3PO4), hydrofluoric acid (HF), buffered HF, hydrochloric acid (HCl), nitric acid (HNO3), acetic acid (CH3COOH), ammonium hydroxide (NH4OH), alcohols, potassium permanganate (KMnO4), ammonium fluoride (NH4F), and others, as would be listed in known wet chemical etching references such as Thin Film Processes, Academic Press (1978), edited by John L. Vossen and Werner Kern. Mixtures of these and other etchant chemicals are also conventionally used.
The wet etchant of the region 20a of layer 20 defines a trench aligned with the opening 45 which extends beneath the body 25. This trench is best seen in
A gate dielectric 62 may now be formed on exposed surfaces which includes the sides, top and bottom of the body 25. The gate dielectric has a high dielectric constant (k), such as a metal oxide dielectric, for instance, HfO2 or ZrO2 or other high k dielectrics, such as PZT or BST. The gate dielectric may be formed by any well-known technique such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Alternately, the gate dielectric may be a grown dielectric. For instance, the gate dielectric 62, may be a silicon dioxide film grown with a wet or dry oxidation process to a thickness between 5-50 Å.
Following this a gate electrode (metal) layer 63 is formed over the gate dielectric layer 62. The gate electrode layer 62 may be formed by blanket deposition of a suitable gate electrode material. In one embodiment, a gate electrode material comprises a metal film such as tungsten, tantalum, titanium and/or nitrides and alloys thereof. For the n channel transistors, a work function in the range of 3.9 to 4.6 eV may be used. For the p channel transistors, a work function of 4.6 to 5.2 eV may be used. Accordingly, for substrates with both n channel and p channel transistors, two separate metal deposition processes may need to be used. Only approximately 100 Å of the metal needs to be formed through ALD to set the work function. The remainder of the gate may be formed of polysilicon.
Standard processing is now used to complete the transistor of
The formation of the gate beneath the body 25 may not be as well defined as the gate on the sides and top of the body 25. For instance, as shown in
The above described method may also be used on other three dimensional (3D) semiconductor bodies such as semiconducting carbon nanotubes, Group 3-5 nanowires and silicon nanowires. The surface upon which the 3D semiconductor nanostructure rests is ion implanted to alter its etching rate to make it more etchable than the nanostructure.
Thus, a method has been described for forming a gate entirely around a silicon body in a replacement gate process. Ion implantation damages the insulation beneath the semiconductor body in the channel region allowing it to be more readily etched. ALD is then used to form a dielectric and gate entirely around the semiconductor body for one embodiment.
Claims
1. A transistor structure, comprising:
- a semiconductor body disposed on a substrate;
- source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions; and
- a gate stack comprising a gate insulation material and a conductive gate material, the gate stack completely surrounding the channel region of the semiconductor body, wherein a portion of the gate stack between the semiconductor body and the substrate comprises a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.
2. The transistor structure defined by claim 1, wherein the semiconductor body is disposed on an insulator layer of the substrate.
3. The transistor structure defined by claim 2, wherein the portion of the gate stack between the semiconductor body and the substrate is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity.
4. The transistor structure defined by claim 3, wherein the portion of the gate stack between the semiconductor body and the substrate only partially fills the cavity to provide a void in the layer of the conductive gate material of the portion of the gate stack between the semiconductor body and the substrate.
5. The transistor structure defined by claim 3, wherein the portion of the gate stack between the semiconductor body and the substrate completely fills the cavity.
6. The transistor structure defined by claim 1, wherein the gate insulation material comprises a high-k dielectric layer.
7. The transistor structure defined by claim 1, wherein the conductive gate material comprises a metal and has a work function between 3.9 to 5.2 eV.
8. A transistor structure, comprising:
- a semiconductor body disposed on a substrate and having a top surface, a bottom surface, a first side surface and a second side surface;
- source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions;
- a first gate electrode disposed on the top surface of the semiconductor body and comprising a gate insulation material and a conductive gate material;
- a second gate electrode disposed on the first side surface of the semiconductor body and comprising the gate insulation material and the conductive gate material;
- a third gate electrode disposed on the second side surface of the semiconductor body and comprising the gate insulation material and the conductive gate material; and
- a fourth gate electrode disposed on the bottom surface of the semiconductor body and comprising the gate insulation material and the conductive gate material, the fourth gate electrode comprising a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.
9. The transistor structure defined by claim 8, wherein the semiconductor body is disposed on an insulator layer of the substrate.
10. The transistor structure defined by claim 9, wherein the fourth gate electrode is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity.
11. The transistor structure defined by claim 10, wherein the fourth gate electrode only partially fills the cavity to provide a void in the layer of the conductive gate material of the fourth gate electrode.
12. The transistor structure defined by claim 10, wherein the fourth gate electrode completely fills the cavity.
13. The transistor structure defined by claim 8, wherein the gate insulation material comprises a high-k dielectric layer.
14. The transistor structure defined by claim 8, wherein the conductive gate material comprises a metal and has a work function between 3.9 to 5.2 eV.
15. A transistor structure, comprising:
- a semiconductor body disposed on a substrate and having a top surface, a bottom surface, and a pair of side surfaces;
- source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions; and
- a gate stack comprising a gate insulation material and a conductive gate material, the gate stack disposed on the entire top surface, the entire side surfaces, and at least a portion of the bottom surface of the semiconductor body, wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body comprises a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.
16. The transistor structure defined by claim 15, wherein the semiconductor body is disposed on an insulator layer of the substrate.
17. The transistor structure defined by claim 16, wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity.
18. The transistor structure defined by claim 17, wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body only partially fills the cavity to provide a void in the conductive gate material of the portion of the gate stack disposed on the bottom surface of the semiconductor body.
19. The transistor structure defined by claim 17, wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body completely fills the cavity.
20. The transistor structure defined by claim 16, wherein a portion of the insulator layer of the substrate is disposed between a portion of the portion of the gate stack disposed on the bottom surface of the semiconductor body.
Type: Application
Filed: Mar 8, 2011
Publication Date: Jun 30, 2011
Inventors: Marko Radosavljevic (Beaverton, OR), Amlan Majumdar (Portland, OR), Suman Datta (Beaverton, OR), Jack Kavalieros (Portland, OR), Brian S. Doyle (Portland, OR), Justin K. Brask (Portland, OR), Robert S. Chau (Beaverton, OR)
Application Number: 13/042,973
International Classification: H01L 29/78 (20060101);