SEMICONDUCTOR PACKAGE
The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
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This application claims the benefit of U.S. Provisional Application No. 61/498,791 filed Apr. 25, 2011, the entirety of which is incorporated by reference herein.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor package, and in particular, to a conductive bump design for a semiconductor package.
2. Description of the Related Art
For a semiconductor chip package design, an increased amount of input/output (I/O) connections for multi-functional chips is required. The impact of this will be pressure on printed circuit board (PCB) fabricators to minimize linewidth and space or to develop direct chip attach (DCA) semiconductors. However, the increased amount of input/output connections of a multi-functional chip package may induce thermal electrical problems, for example, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference for RF circuits, etc. The thermal electrical problems may affect the reliability and quality of products.
Thus, a novel semiconductor package with better thermal and electrical properties is desirable.
BRIEF SUMMARY OF INVENTIONA semiconductor package is provided. An exemplary embodiment of a semiconductor package comprises a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts.
The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention.
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Additionally, the semiconductor package 500a can be bonded to a substrate 300, for example, a print circuit board (PCB), as shown in
In another embodiment, positions of the metal pads 202 and 204 can be exchanged.
In yet another embodiment, the metal pads 202 and 204 can be arranged both in the the central area 302 and the peripheral area 304. Also, the metal pads 202 and 204 can be alternatively arranged in the central area 302 or the peripheral area 304.
In still yet another embodiment, the metal pads 202 and 204 can be arranged both in the central area 302 and the peripheral area 304. Also, the metal pads 202 and 204 can be randomly arranged in the central area 302 or the peripheral area 304.
Exemplary embodiments provide a semiconductor package. The semiconductor package is designed to arrange conductive bumps with two different areas (sizes) in one semiconductor package. Because the power/ground connections of the semiconductor chip 301 has a number much less than the signal connections, a minimum pitch of the metal pads 204 for power/ground connections may be designed larger than a minimum pitch designed for the metal pads 202 for signal connections. An area A1 of each of the conductive bumps 216a connecting the metal pads 204 is designed to be larger than an area A2 of the conductive bumps 216b connecting the metal pads 202 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500. In one embodiment as shown in
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. A semiconductor package, comprising:
- a semiconductor die; and
- a first conductive bump and a second conductive bump respectively disposed on the semiconductor die, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
2. The semiconductor package as claimed in claim 1, wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the central area, and the second conductive bump is disposed on the semiconductor die in the peripheral area.
3. The semiconductor package as claimed in claim 1, wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the peripheral area, and the second conductive bump is disposed on the semiconductor die in the central area.
4. The semiconductor package as claimed in claim 1, wherein the first conductive bump and the second conductive bump are alternatively disposed on the semiconductor die.
5. The semiconductor package as claimed in claim 1, wherein the first conductive bump and the second conductive bump are randomly disposed on the semiconductor die.
6. The semiconductor package as claimed in claim 1, wherein the first conductive bump is a circular shape from the top view.
7. The semiconductor package as claimed in claim 1, wherein the second conductive bump is an oblong shape from the top view.
8. The semiconductor package as claimed in claim 1, wherein the first conductive bump connects to a power pad or ground pad of the semiconductor die.
9. The semiconductor package as claimed in claim 1, wherein the second conductive bump connects to a signal pad of the semiconductor die.
10. The semiconductor package as claimed in claim 1, further comprising:
- a first under bump metallurgy layer pattern disposed between the semiconductor die and the first conductive bump; and
- a second under bump metallurgy layer pattern disposed between the semiconductor die and the second conductive bump.
11. The semiconductor package as claimed in claim 10, wherein the first under bump metallurgy layer pattern is a circular shape from the top view.
12. The semiconductor package as claimed in claim 10, wherein the second under bump metallurgy layer pattern is a rectangular shape from the top view.
13. The semiconductor package as claimed in claim 10, further comprising:
- a first conductive pillar connecting to and between the first under bump metallurgy layer pattern and the first conductive bump; and
- a second conductive pillar connecting to and between the second under bump metallurgy layer pattern and the second conductive bump.
14. The semiconductor package as claimed in claim 13, wherein the first conductive pillar is a circular shape.
15. The semiconductor package as claimed in claim 13, wherein the second conductive pillar is an oblong shape from the top view.
16. The semiconductor package as claimed in claim 13, wherein an area ratio the first conductive pillar to the second conductive pillar from a top view is larger than 1, and less than or equal to 3.
17. The semiconductor package as claimed in claim 1, further comprising a substrate having a plurality of conductive traces thereon, wherein the first conductive bump and the second conductive bump are bonded onto the conductive traces, respectively.
18. The semiconductor package as claimed in claim 1, further comprising:
- a solder resistance layer disposed on the substrate, away from an overlap region between the substrate and the semiconductor die; and
- an underfill material filling a gap between the substrate and the semiconductor
Type: Application
Filed: Mar 26, 2012
Publication Date: Oct 25, 2012
Applicant: MEDIATEK INC. (Hsin-Chu)
Inventors: Tzu-Hung LIN (Zhubei City), Wen-Sung HSU (Zhubei City), Tai-Yu CHEN (Taipei City)
Application Number: 13/430,439
International Classification: H01L 23/498 (20060101);