RELATED APPLICATIONS This application claims the benefit of provisional patent application 61/285,140 filed on Dec. 9, 2009, which is hereby incorporated by reference.
FIELD This disclosure relates in general to the field of photovoltaics and solar cells, and more particularly to back contact back junction thin solar cells and methods for manufacturing.
BACKGROUND Crystalline silicon currently has the largest market share in the photovoltaic (PV) industry, accounting for over 80% of the overall PV market share. Although going to thinner crystalline silicon solar cells is long understood to be one of the most potent knobs for PV cost reduction (because of the relatively high material cost of crystalline silicon wafers used in solar cells as a fraction of the total PV module cost), it is fraught with the problem of mechanical breakage due to the thin and large wafer sizes and to some extent that of light trapping in a thin structure. The requirement of high mechanical yield and reduced wafer breakage rate is further problematic with the realization that for cost-effectiveness, the yields in PV manufacturing factories must be very high. On a standalone crystalline silicon solar cell (without support), going even somewhat below the current thickness range of 140 μm-250 μm, starts to severely compromise mechanical yield during manufacturing. Thus, any solution to process very thin solar cell structures either should be fully or partially supported by a host carrier throughout the cell process or should be a novel self-supporting, standalone substrate with an accompanying structural innovation providing rigidity. High efficiency solar cells are classically manufactured using expensive patterning techniques such as lithography. The techniques described herein allow for substantial cost reduction both because of much less silicon and process simplification, while enabling a high performance high efficiency cell design.
Achieving high cell and module efficiency with low fabrication costs has always been an important task for solar cell development and manufacturing. Back junction/back contacted cell architecture is capable of very high efficiency primarily because there is no metal shading on the front side, no emitter on the front and the resulting high blue response, as well as due to potentially low metal resistance on the backside. Although, the aforementioned thin substrates and the carrier approach can, in general, be used with any cell architecture, it is specifically, conducive to the back junction/back contacted cell. It is known to those versed in the field that back junction/back contacted cell demands a very high diffusion length to substrate thickness ratio, typically ≧5. In conventional cells, because thickness cannot be reduced easily the emphasis is to get very high lifetime material—which results in a larger minority carrier diffusion length, but increases the wafer cost. With thin cells, the diffusion length does not have to be as high resulting in an ease in the material quality requirements, in addition to much less volume of silicon.
SUMMARY In accordance with the disclosed subject matter, innovative structures and methods for manufacturing back contact/back junction solar cells are provided.
In one embodiment, a back contact back junction solar cell using semiconductor wafers and methods for manufacturing is provided. The back contact back junction solar cell comprising a semiconductor wafer having a doped base region, a light capturing frontside surface, and a doped backside emitter region. A frontside and backside dielectric layer and passivation layer provide enhance light trapping and internal reflection. Backside base and emitter contacts are connected to metal interconnects forming a metallization pattern of interdigitated fingers and busbars on the backside of the solar cell.
The disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the claimed subject matter, but rather to provide a short overview of some of the subject matter's functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGURES and detailed description. It is intended that all such additional systems, methods, features and advantages included within this description, be within the scope of the accompanying claims.
BRIEF DESCRIPTIONS OF THE DRAWINGS For a more complete understanding of the disclosed subject matter and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:
FIG. 1 is a cross-sectional diagram of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 2 is a block diagram of a fabrication process flow for making a solar cell;
FIGS. 3(a-i) are cross-sectional schematic views of a solar cell fabricated according to FIG. 2 after key process steps;
FIGS. 4(a-b) illustrate backside views of two types of backside reinforcement plates with through plate openings or grid-shaped rib structures;
FIGS. 5(a-b) illustrate two exemplary metal busbar designs;
FIG. 6 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 7 is a block diagram of a fabrication process flow for making the solar cell of FIG. 6;
FIG. 8 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 9 is a block diagram of fabrication process flow of making the solar cell of FIG. 8;
FIG. 10 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 11 is a block diagram of the fabrication process flow for making the solar cell of FIG. 10;
FIG. 12 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 13 is a block diagram of the fabrication process flow for making the solar cell of FIG. 12;
FIGS. 14(a-k) are cross-sectional schematic views of the fabrication of the solar cell of FIG. 12 after key fabrication process steps;
FIG. 15 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 16 is a block diagram of fabrication process flow of making the solar cell of FIG. 15;
FIG. 17 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 18 is a block diagram of fabrication process flow of making the solar cell of FIG. 17;
FIG. 19 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 20 is a block diagram of fabrication process flow of making the solar cell of FIG. 19;
FIG. 21 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer;
FIG. 22 is a block diagram of the fabrication process flow for making the solar cell of FIG. 21; and
FIGS. 23(a-k) are cross-sectional schematic views of the fabrication of the solar cell of FIG. 21 after key fabrication process steps
DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENTS The following description is not to be taken in a limiting sense, but is made for the purpose of describing the general principles of the present disclosure. The scope of the present disclosure should be determined with reference to the claims. Exemplary embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings.
The following disclosure describes various back contacted cells (BLAC cell) on thin wafers made from bulk ingots. Specifically, the wafers may be made using wire saw or proton implantation and separation. And although, NBLAC cells are used for explanatory purposes (NBLAC defined by N-type base doping), the scope of the disclosed structures and methods are not intended to be limited to NBLAC cells as one skilled in the art could apply the disclosed subject matter PBLAC cells (PBLAC defined by p-type base doping, such as boron-based). There are two sub-sections in this disclosure: 1) In the first subsection, the process flows involve growth of the emitter using epitaxial deposition on the wafer as opposed to the entire substrate being grown using epitaxy. 2) In the second section, the emitter is formed on the surface region of the wafer using gas phase diffusion in a furnace or using atmospheric pressure chemical vapor deposition (APCVD). For NBLAC cells (having n-type base) the emitter is p-type, typically boron based, and is formed by boron doping in a furnace or the deposition of APCVD BSG on the wafer surface followed by annealing.
FIG. 1 is a cross-sectional diagram of a back contact solar cell that is made of a bulk silicon wafer. This solar cell embodiment is referred to as a Flow-1.1 cell. The back contact solar cell has lightly doped epitaxial emitter everywhere except under contacts (where it is doped heavily to form the selective emitter contacts), two-sided thermal oxide and LPCVD silicon nitride thin layers, laser ablated contact openings, inkjet printed dopants, electroless-plated metallization, and substrate reinforcement. The oxide layer provides passivation to both front and back surfaces while LPCVD silicon nitride acts as an anti-reflection coating for the front surface and as wet etch stop for processing on the back surface of the wafer. The substrate reinforcement plate is shown, as an example, attached with alignment to the backside of the cell. The backside reinforcement plate may be a continuous plate with through holes for accessing the emitter and base metal contacts on the backside of the solar cell. Alternatively, the backside reinforcement plate may have one or more larger openings that resemble a grid-shaped structure for lighter and easier substrate backside access at solar cell module level.
The starting silicon wafer may be either a CZ or FZ wafer. The thin silicon substrate may be formed by sawing a silicon ingot followed by an optional surface grinding and polishing, or by cleaving/releasing from a thick silicon wafer. The wafer is preferably thin enough for a given average minority carrier lifetime in order to obtain the diffusion length to wafer thickness ratio of ≧5. On the other hand, the wafer should be robust for surviving the handling and processing conditions. The thickness of the silicon wafer is preferably in the range of 50 μm to 250 μm. The shape of the silicon substrate may be square or pseudo-square with rounded corners. The edges of the thin wafer are preferable polished to eliminate the micro cracks at the edges in order to prevent the cracking of the wafer during subsequent processing steps.
FIG. 2 is a block diagram of a fabrication process flow for making the Flow-1.1 solar cell. FIGS. 3(a-i) are cross-sectional schematic views of the Flow-1.1 solar cell after key fabrication process steps. As shown in FIG. 2, the solar cell fabrication process starts with texturing. The front side surface of the solar cells is textured for reduction of the reflective optical losses. The surface texture is formed by etching in a diluted alkaline solution, such as KOH solution. In the low concentration of KOH etching, different crystal planes in silicon are etched at different rates. As a result, randomly distributed pyramids with various sizes are formed. The texture etching process may be conducted in a single side etching apparatus, in which only the front side of the silicon substrate is making contact with the etching solution or alternatively, both sides of the silicon substrate may be textured by submerging the substrates in the etching solution in a batch etching process. In yet another alternative texturing approach, the textures may be formed by laser surface ablation. As a laser beam with proper wavelength, power, and duty are scanned across the silicon front surface, micro surface cavities with random sizes and shapes are formed. After laser ablation, a short diluted KOH etching may be conducted to remove the silicon debris and further enhanced the surface texturing. After the texturing process, the wafer is cleaned using the standard RCA clean which consists of an organic clean (referred to as SC1) and metal contaminations clean (referred to as SC2 clean). FIG. 3(a) illustrates cross-sectional view of the silicon substrate after the front side texturing process.
In the next step, as shown in FIG. 3(b), a thin epitaxial silicon emitter layer is grown on top of the backside silicon surface. In the case of n-type silicon substrate, the epitaxial emitter layer is p-type in-situ doped, such as by boron doping within the epitaxial growth process. Compared with the diffusion based doping process, the in-situ epitaxial doping may provide doping profiles that can be tailored for the best possible open circuit voltage (Voc)and current density (Jsc). For example, the epitaxial doping can be constant or continuously varying (or graded) within the layer thickness, or use multi-step doping with each doping step resulting in different doping concentration. This in general, can facilitate a high open circuit voltage (Voc) of the solar cell, thus a higher efficiency. The epitaxial emitter layer is preferred to have a thickness in the range of 0.5 μm to 3 μm.
As shown in FIG. 2, the next step is surface passivation layer and anti-reflection coating (ARC) layer deposition. Since defects of the silicon crystal structure at the substrate surface are much more common than the defects in the bulk, reduction of the carrier recombination at the surface defects is an important requirement in achieving high-efficiencies for crystalline silicon solar cells—and it is even more critical for thin and large silicon wafers because of the larger surface to volume ratio. Surface passivation with dielectric layers is an effective method to reduce the carrier recombination rate at surfaces because good surface passivation layers provide reduction of the surface state density. In FIG. 2, a thermally grown silicon oxide thin layer with thickness in the range of 3 nm to 100 nm is used for both front and back side surface passivation. FIG. 3(c) illustrates the cross-sectional view of the wafer after the thin thermal oxidation layer growth showing the thin oxide layer on both sides of the silicon wafer.
On top of the thin thermal oxide layer, a thin LPCVD silicon nitride layer, with thickness preferably in the range of 60 nm to 100 nm, is deposited. Alternatively, the oxide/silicon nitride layers on the backside may be replaced by an aluminum oxide layer of similar thickness to provide surface passivation of p-type emitter. The LPCVD silicon nitride layers serve at least three purposes: (1) Optically, combined with the thin oxide layer, the silicon nitride layer surface as an anti-reflection coating (ARC) layer at front surface as well as an enhanced internal optical reflection layer for better light trapping at front surface. At the backside surface, the oxide and nitride (or aluminum oxide) layers, with proper thickness, provides an enhanced internal optical reflection to serve as part of the back mirror effects combined with the deposited metal layer on the backside surface. (2) Mechanically, the LPCVD silicon nitride layer (or the aluminum oxide layer at backside) protects the silicon surface and the thin silicon oxide surface from scratches that may be generated during cell processing. It also serves as a barrier layer to prevent impurity and metal diffusions into the silicon surface therefore avoiding or reducing electrical shunting. (3) Chemically, the silicon nitride and aluminum oxide layer, especially a LPCVD silicon nitride layer, provides a good chemical resistant layer during subsequent cell processing steps, such as removal of the doping glass in diluted HF-based etchants after the annealing the dispensed liquid dopants. In the embodiment shown in FIG. 2 of the Flow-1.1 solar cell, a thin layer of LPCVD silicon nitride is deposited on both sides of the substrates on top of the oxide layer. FIG. 3(d) illustrates the cross-sectional view of the substrate after the LPCVD silicon nitride deposition.
As shown in FIG. 2, the next step is to create interdigitated rows of contact openings in the aforementioned dielectric layer so the underlying silicon is exposed. In general, the pattern in which the dielectric will be opened is an inter-digitated fingers and bus bar—the base and the emitter lines are separated and continuous or a string of non-overlapping spots. The purpose of the base and emitter contact openings is for subsequent selective doping. In the NBLAC embodiment, base contact open will be doped heavily with n-type phosphorous material and emitter contact open will be doped with p-type Boron. Both base and emitter opening regions are opened at the same time in this step. A specific implementation of this step may be carried out using a direct laser ablation of the oxide layer. A pulsed picosecond laser in visible or UV wavelength is conducive to ablating an oxide layer. FIG. 3(e) illustrates the dielectric base and emitter openings in the cross-sectional drawing.
As shown in FIG. 2, the next step is to apply both n and p-type dopants selectively over the base and the emitter contact open areas following the previously defined inter-digitated pattern. The dopants will cover the openings and can have a slight overlap with the dielectric layer (on top of it). For the NBLAC specific embodiment, on the emitter area this dopant has to be p++ type (for instance boron based), and on the base contact area it has to be n++ type (phosphorous based). A specific method of implementation of the dopants is using the inkjet printing technique. In addition, specific examples of the inks that may be disposed are silicon nano-particle based phosphorous and boron inks. This step is followed by an optional step of using inkjet printer to print all cell areas (or areas excluding laser-ablated contacts) with undoped Si (or glass) nano-particle ink. This is followed by sintering of the ink as required by specific ink handling instructions. The purpose of the undoped ink is to use it to randomly texture the oxide surface which improves the Lambertian properties of the back mirror—thus enhancing efficiency. FIG. 3(f) illustrates the inkjet-printed (and optional sintered) base and emitter dopants and the inkjet-printed undoped silicon nano-particles that form a blanket textured surface layer.
As shown in FIG. 2, the next step is to anneal the inkjet-printed boron, phosphorous, and undoped ink to form n++ and P++ emitter contact regions. In addition, the annealing step may either be followed by or be integrated with another anneal in a low O2 environment which serves to oxidize the undoped silicon particles and create a randomly textured oxide surface. FIG. 3(g) illustrates the selectively doped base and emitter regions as well as the surface-textured silicon oxide layer.
As shown in FIG. 2, the next step is metallization. First, the backside of the substrate is cleaned to remove the dopant residue (phosphorous and boron glass) in a diluted HF solution. The LPCVD nitride serves as an etching stop to the dopant residue etching. Next, the contact areas are cleaned for good metal adhesion and electrical contacts. A mild selective silicon etch may be used to clean the area. Although there are several ways to perform metallization, a specific implementation with a few variations is described for explanatory purposes. As an example, a metal stack of nickel/copper/nickel (Ni/Cu/Ni) with Cu thickness in the range of 10 to 50 μm can be electroless plated. The thin Ni layer under the Cu serves as a Cu barrier to prevent Cu diffusion into silicon, while the Ni layer on top of the Cu layer serves as a passivation layer to prevent Cu surface oxidation and corrosion. In general the plating scheme may be electroplating, electroless or emulsions, or any other metal plating technique (the preferred scheme is electroless and the metal of choice is a Ni+Cu+Ni stack). However, it is not limited to this stack either for barrier (Ni) or for the main (Cu) metal. Another possibility is an Ni/Ag stack. FIG. 3(h) illustrates the cross-sectional schematic view of the fabricated solar cell after its backside metallization steps.
As shown in FIG. 2, the last step of the cell making process is applying a reinforcement plate on the backside of the solar cell. This step is necessary if the solar cell silicon substrate is thin, such as thinner than 150 μ. The material of the reinforcement plate is preferred to be a PV-grade material, such as PTFE. The PTFE plate/sheet may be pre-laminated through an adhesive layer, such as PV-grade EVA, Z68 or silicone. Before laminating the PTFE plate on to the solar cell, through-holes or openings have to be made so that the electrical metal contacts may be accessed from the backside. The opening or through-hole formation may be achieved by mechanical punching/stamping or by laser cutting. In the last step, as shown in FIG. 3(i), the patterned PTFE with adhesive layer is laminated on the backside of the solar cell with proper alignment.
FIGS. 4(a-b) illustrate backside views of two types of backside reinforcement plates with through plate openings or grid-shaped rib structures. As shown in FIG. 4(a), the PTFE reinforcement plate has regular through-hole openings for backside solar cell metal contact access. The thickness of the PTFE plate is preferably in the range of 0.1 mm to 0.5 mm. The through-hole diameter is preferably in the range of 1 mm to 5 mm and the pitch of the holes is preferably in the range of 5 mm to 50 mm—depending on the metal finger pattern and metal finger thickness on the back of the solar cell. As shown in FIG. 4(b), the grid-shaped backside reinforcement may also provide mechanical support for the thin solar wafer. The width of the grid line may be in the range of 0.3 mm to 1 mm, and the thickness of the grid line can be in the range of 50 μm to 300 μm. The opening shape may be square, rectangular, circular, or other shapes providing access to the cell backside. In the case of square shape openings as shown, the size of the squares may be in the range of 5 mm×5 mm to 50 mm×50 mm
FIGS. 5(a-b) illustrate two metal busbar designs. An important attribute of a thin, yet high efficiency cell design is the busbar design. The standard busbar design is a dual bus bar design with inter-digitated metal pattern, shown in FIG. 5(a). A consideration of is that it requires thick metal in the back because the current has to be carried by the fingers all the way from one edge of the substrate to the other. The line presents a large resistive loss of power. A thicker metal typically in the >30 μm range will work for standard a silicon cell ˜150 μm thick. However, thin silicon substrate (<150 μm) back contacted solar cells may not be able to withstand the stresses of >30 μm Cu metal lines. Hence, there is a need for alternatives in the busbar design to enable a very high efficiency, thin, back contacted cell.
FIG. 5(b) illustrates a distributed busbar design. Here, there are N bus bars for emitter and the same number for the base areas (FIG. 3 is an N=3 design). An advantage of this design is that the thinner fingers are responsible for carrying the current for a much shorter distance, hence dramatically mitigating the resistive losses. All the emitter busbars are connected together and the base busbars are connected together. Compared to the standard N=1 (dual busbar) for N pairs of busbars, the busbar current is reduced by a factor of N. This allows Cu thickness to be reduced by a factor of N without compromising the resistive losses, enabling Cu thickness between 5-10 μm for N=3-4. For thin silicon cells this is a major advantage. A potential consideration with the distributed bus bars is increased contact recombination and electrical shading because of a larger metal contact area. However, this may be mitigated by making a slotted busbar design in which the contact to underlying silicon is in slots, but the overhanging metal joins together to form a continuous line—this requires that the spacing between the slots is no more than twice the thickness of the metal. Note that the busbar design may be decoupled from the process flow discussed above as it only dictates the pattern in which the laser ablates the dielectric and the thin metal layer.
FIG. 6 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer—referred to hereinafter as a Flow-1.2 cell. The back junction/back contact solar cell has lightly doped epitaxial emitter everywhere except under contacts (where it is doped heavily to form the selective emitter contacts), front side and backside PECVD silicon nitride and thermal oxide thin layers for passivation and anti-reflection coating (ARC), optional backside PECVD aluminum oxide (replacing oxide/PECVD SiN on the backside), laser ablated contact openings, inkjet printed dopants, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, to be attached with alignment to the backside of the cell. A difference between the Flow-1.2 cell and Flow-1.1 cell is that Flow-1.2 cell uses two separated PECVD silicon nitride (or backside aluminum oxide) depositions to replace the single-step double-sided LPCVD silicon nitride deposition in the Flow-1.1 cell. There are several purposes for the change: (1) Electrically, it provides a built-in electric field by the isolated fixed charge within the PECVD silicon nitride film for repelling the minority carriers from the potential recombination sites at the silicon surfaces; (2) PECVD silicon nitride or aluminum oxide deposition is conducted at a much lower temperature, in the range of 300° C. to 400° C., than the LPCVD silicon nitride deposition temperature, in the range of 700° C. to 800° C. (lower deposition temperature not only has less influence to the substrate doping profile but also reduced the fabrication costs); (3) The separated frontside and backside PECVD deposition allows tuning of the front and back passivation layer thickness and properties independently for optimization of electrical and optical performance of the passivation, anti-reflection, and total internal reflection effects.
FIG. 7 is a block diagram of a fabrication process flow for making the Flow-1.2 solar cell of FIG. 6. As described, compared to the Flow-1.1 cell, a difference in the block diagram for Flow-1.2 cell is the fourth step, which is PECVD silicon nitride deposition on frontside and PECVD aluminum oxide or PECVD silicon nitride deposition on backside. The remaining process sequences and steps are identical to the Flow-1.1.
FIG. 8 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer. The solar cell is referred to as a Flow-2.1 cell. The back contact solar cell has epitaxial selective emitter (ESE) as described earlier, two-sided thermal oxide and LPCVD silicon nitride thin layers for passivation and anti-reflection coating (ARC), respectively, laser ablated contact openings, inkjet printed dopants, inkjet-deposited metal inks, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, to be attached with alignment to the backside of the cell. A difference between the Flow-2.1 cell and the described Flow 1.1 cell is that there is a metal inkjet printing and sintering step prior to the electroless plating metallization process. Metal inks, such as aluminum (Al) and silver (Ag) nano particle inks, are selectively deposited on top of both the base and the emitter contact areas. The Ink is deposited such that it follows the shape of the emitter and the base fingers and busbars. After the inkjet printing, the printed Al ink is sintered at elevated temperature, in the range of 500° C. to 575° C., that would also sinter the Ag ink. An advantage of the added inkjet printing and sintering step is to provide better electrical contact to the silicon.
FIG. 9 is a block diagram of fabrication process flow of making the Flow-2.1 solar cell. Compared to the Flow-1.1 cell, a difference in the block diagram for Flow-2.1 cell is the added step prior to electroless plating. The added step is inkjet printing AL/Ag or Ni nanoparticle ink on busbars and interdigitated fingers with optional thermal annealing/sintering. The rest process sequences and steps are identical to the Flow-1.1 cell as described.
FIG. 10 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer. The solar cell is referred to as a Flow-2.2 cell. The back contact solar cell has epitaxial selective emitter (ESE) as described earlier, front side and backside PECVD silicon nitride and thermal oxide thin layers for passivation and anti-reflection coating (ARC), optional backside PECVD aluminum oxide, laser ablated contact openings, inkjet printed dopants, inkjet-deposited metal inks, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, to be attached with alignment to the backside of the cell. A difference between the Flow-2.2 cell and Flow-2.1 cell is that Flow-2.2 cell use two separated PECVD silicon nitride (or backside aluminum oxide) depositions to replace the single-step double-sided LPCVD silicon nitride deposition in the Flow-2.1 cell.
FIG. 11 is a block diagram of the fabrication process flow for making the Flow-2.2 solar cell. As described, compared to the Flow-2.1 cell, a difference in the block diagram for Flow-2.2 cell is the fourth step, which is PECVD silicon nitride deposition on frontside and PECVD aluminum oxide or silicon nitride deposition on backside. The rest process sequences and steps are identical to the Flow-2.1 cell as described.
FIG. 12 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer. The solar cell is referred to as a Flow-3.1 cell. The back contact solar cell has epitaxial selective emitter (ESE) (the steps leading to the formation of selective emitter are described previously), two-sided thermal oxide and LPCVD silicon nitride thin layers for passivation and anti-reflection coating (ARC), respectively, laser ablated contact openings, spray coated dopants, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, to be attached with alignment to the backside of the cell. The final structure of the Flow-3.1 cell is identical to the Flow-1.1 as shown in FIG. 1. However the fabrication process is slightly different for the dopant deposition methods and the contact opening sequence. Specifically, the phosphorous and boron liquid dopants are spray coated in two separated steps and contact openings of each polarity are formed just prior to the separated liquid dopant coating step.
FIG. 13 is a block diagram of the fabrication process flow for making the Flow-3.1 solar cell. FIGS. 14(a-k) are cross-sectional schematic views of the Flow-3.1 solar cell after key fabrication process steps. The steps shown—including surface texturing, thin epitaxial emitter layer growth, thermal oxidation, and LPCVD silicon nitride deposition steps—are the same for the Flow-1.1 cell described and illustrated in FIG. 2 and FIGS. 3(a-d). In the next step, as shown in FIG. 14(e), only the base contacts are opened by pulsed laser ablation. Phosphorous liquid dopant is then spray coated—FIG. 14(f) shows the cured phosphorous dopant layer. Next, the emitter contacts are opened by pulsed laser ablation of the dielectric layer stacks on top of the silicon surface, as shown in FIG. 14(g). Then the emitter (boron) dopant liquid is spray coated and cured, as shown in FIG. 14(h). The rest of cell processing steps from FIGS. 14(i) to 14(k) are the same as described for Flow-1.1 cell.
FIG. 15 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer. The solar cell is referred to as a Flow-3.2 cell. The back contact solar cell has epitaxial selective emitter (ESE) (the steps leading to the formation of selective emitter are describes previously), front side and backside PECVD silicon nitride and thermal oxide thin layers for passivation and anti-reflection coating (ARC), optional backside PECVD aluminum oxide replacing oxide/silicon nitride sandwich, laser ablated contact openings, spray-coated dopants, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, attached with alignment to the backside of the cell. A difference between the Flow-3.2 cell and Flow-3.1 cell is that Flow-3.2 cell uses two separated PECVD silicon nitride (or backside aluminum oxide) depositions to replace the single-step double-sided LPCVD silicon nitride deposition in the Flow-3.1 cell.
FIG. 16 is a block diagram of fabrication process flow of making the Flow-3.2 solar cell. As described, compared to the Flow-3.1 cell, a difference in the block diagram for Flow-3.2 cell is the fourth step, which is PECVD silicon nitride deposition on front side and PECVD aluminum oxide or PECVD silicon nitride deposition on backside. The rest process sequences and steps are identical to the Flow-3.1 cell as described.
FIG. 17 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer. The solar cell is referred to as a Flow-4.1 cell. The back contact solar cell has epitaxial selective emitter (ESE) (where the steps leading to the formation of selective emitter are described previously), two-sided thermal oxide and LPCVD silicon nitride thin layers for passivation and anti-reflection coating (ARC),respectively, laser ablated contact openings, spray coated dopants, inkjet-deposited metal inks, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, attached with alignment to the backside of the cell. A difference between the Flow-4.1 cell and the described Flow 3.1 cell is that there is a metal inkjet printing and sintering step prior to the electroless plating metallization process. Metal inks, such as aluminum (Al) and silver (Ag) nano particle ink, are selectively deposited on top of both the base and the emitter contact areas. The inks are deposited such that they follow the shape of the emitter and the base fingers and busbars. After the inkjet printing, the printed inks are sintered at elevated temperature, in the range of 500° C. to 575° C., in the case of aluminum ink which would also sinter the Ag ink.
FIG. 18 is a block diagram of fabrication process flow of making the Flow-4.1 solar cell. Compared to the Flow-3.1 cell, a difference in the block diagram for Flow-4.1 cell is the added step prior to electroless plating. The added step is inkjet printing Al/Ag or Ni nanoparticle ink on busbars and interdigitated fingers with optional thermal annealing/sintering. The rest process sequences and steps are identical to the Flow-3.1 cell as described.
FIG. 19 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer. The solar cell is referred to as a Flow-4.2 cell. The back contact solar cell has epitaxial selective emitter (ESE) (where the steps leading to the formation of selective emitter are described previously), front side and backside PECVD silicon nitride and thermal oxide thin layers for passivation and anti-reflection coating (ARC), optional backside PECVD aluminum oxide, laser ablated contact openings, spray coated dopants, inkjet-deposited metal inks, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, attached with alignment to the backside of the cell. A difference between the Flow-4.2 cell and Flow-4.1 cell is that Flow-4.2 cell uses two separated PECVD silicon nitride (or backside aluminum oxide) depositions to replace the single-step double-sided LPCVD silicon nitride deposition in the Flow-4.1 cell.
FIG. 20 is a block diagram of fabrication process flow of making the Flow-4.2 solar cell. As described, compared to the Flow-4.1 cell, a difference in the block diagram for Flow-4.2 cell is the fourth step which is PECVD silicon nitride deposition on front side and PECVD aluminum oxide or silicon nitride deposition on backside. The rest process sequences and steps are identical to the Flow-4.1 cell as described.
The above described cell process variations have common epitaxial emitter layers. Alternatively, the emitter layer may be formed by a dopant diffusion process such as furnace annealing using boron containing precursors or the deposition of boron silicate glass (BSG) on the wafer surface followed by annealing. All eight flows along with their variations discussed for the epitaxial emitter in the aforementioned section are equally applicable here. The difference is that the epitaxial emitter step is substituted by the furnace annealing in boron containing gases or BSG deposition and annealing steps. This substitution is demonstrated for only one process (two sided LPCVD SiN, with inkjet dopants, with no metal inkjet) in FIGS. 21-23. However, it is equally applicable to all other seven embodiments. The epitaxial emitter deposition step is replaced by three steps of BSG deposition on the emitter side, furnace annealing to form p+ selective emitter on the backside, and BSG strip and clean.
FIG. 21 is a cross-sectional schematic view of a back contact solar cell that is made of a bulk silicon wafer. The solar cell is referred to as a Flow-5.1 cell. The back contact solar cell has a dopant-diffusion formed emitter layer, two-sided thermal oxide and LPCVD silicon nitride thin layers for passivation and anti-reflection coating (ARC), respectively, laser ablated contact openings, inkjet printed dopants, electroless-plated metallization, and substrate reinforcement.
FIG. 22 is a block diagram of the fabrication process flow for making the Flow-5.1 solar cell. FIGS. 23(a-k) are cross-sectional schematic views of the Flow-5.1 solar cell after key fabrication process steps. The first surface texturing step is same as describe for Flow 1.1 cell. As shown in FIG. 23(b), a thin layer of BSG is deposited on the substrate backside—preferably by the atmospheric pressure chemical vapor deposition (APCVD) process. Next, a furnace annealing process is conducted that forms the diffused p+ emitter layer on the backside, as shown in FIG. 23(c). FIG. 23(d) shows the removal of the remaining BSG layer followed by wafer cleaning The removal of the remaining BSG layer may be done by diluted HF solution etching and the substrate cleaning may be done by standard SC1 and SC2 etching. The rest of process steps as shown from FIG. 23(e) to FIG. 23(k) are same as described for the Flow-1.1 cell accordingly.
In operation, the disclosed subject matter provides both the structures and methods for manufacturing novel high-efficiency back junction/back contacted solar cells—preferably on thin crystalline semiconductor wafers (preferably monocrystalline silicon). More specifically, these solar cell wafers may be produced by techniques including slicing and cleaving thin crystalline substrates from thicker wafers or ingot pieces using techniques such as proton implantation and stress-induced cleaving/slicing. Generally, the particular concept of manufacturing methods as it pertains to all aspects of processing very thin solar cell wafers can be extended to other types of materials and to wafer-based approach. Key attributes of the detailed solar cell include reduced manufacturing cost per watt and relatively high conversion efficiencies, and thus performance. Specifically, this stems from the unique design, which entails manufacturing back junction/back contacted solar cells, yielding very high performance on very thin mono/multi-crystalline semiconductor wafers, yielding very low manufacturing cost. While the embodiments disclosed are described utilizing monocrystalline silicon wafers, these embodiments are also applicable to other elemental and compound semiconductor materials such as GaAs (gallium arsenide), as well as heterojunctions and multijunction solar cells utilizing silicon or other semiconductor materials.
Further, the disclosure provides designs and methods of manufacturing back contact/junction solar cell using planar silicon substrates. Other disclosed aspects include the use of sub-nanosecond pulsed laser processing (from femtosecond to hundreds of picoseconds) to support the fabrication of back junction back contact solar cells.
In one embodiment, the back contact solar cell has epitaxial selective emitter (ESE), two-sided thermal oxide and LPCVD silicon nitride thin layers for passivation and anti-reflection coating (ARC), laser ablated contact openings, inkjet printed dopants, electroless-plated metallization, and substrate reinforcement. The substrate reinforcement plate is shown, as an example, attached with alignment to the backside of the cell. The backside reinforcement plate may be a continuous plate with through-holes for accessing the emitter and base metal contacts on the backside of the solar cell. Alternatively, the backside reinforcement plate may have more or larger openings that are assembled to a grid-shaped structure for lighter and easier substrate backside access at solar cell module level.
In another embodiment, the double-sided LPCVD silicon nitride passivation layer is replaced by two separated front side and backside PECVD silicon nitride depositions. In another embodiment, the backside PECVD silicon nitride layer is replaced by a thin aluminum oxide layer.
In another embodiment, there is an inkjet printing of metal nanoparticle ink and its sintering process prior to the electroless metal plating process. Also disclosed is aerosol printed Al ink.
In one embodiment the inkjet dopant ink used is comprised of silicon nano-particles with p and n-type dopants. In another embodiment, the inkjet liquid dopant printing process is replaced by a dopant liquid spray coating process.
In another embodiment, the forming of the backside epitaxial emitter layer is replaced by forming the emitter layer by a dopant diffusion process. This includes, but is not limited to Atmospheric pressure Chemical vapor Deposition (APCVD) processes.
The foregoing description of the preferred embodiments is provided to enable any person skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the innovative faculty. Thus, the claimed subject matter is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
