SUBSTRATE DIODE FORMED BY ANGLED ION IMPLANTATION PROCESSES
A substrate diode device having an anode and a cathode includes a doped well positioned in a bulk layer of an SOI substrate. A first doped region is positioned in the doped well, the first doped region being for one of the anode or the cathode, the first doped region having a first long axis and a second doped region positioned in the doped well. The second doped region is separate from the first doped region, the second doped region being for the other of the anode or the cathode, the second doped region having a second long axis that is oriented at an orientation angle with respect to the first long axis.
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This is a divisional of co-pending application Ser. No. 13/218,589, filed Aug. 26, 2011.
BACKGROUND OF THE INVENTION1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. A typical semiconductor chip will include millions of transistors and multiple levels of conductive interconnections to form the desired electrical circuits on the chip such that the chip may perform its intended operations.
One important issue, particularly in high performance devices, such as microprocessors and the like, is efficient management of the internal temperature of the integrated circuit device during operation. Depending upon the frequency and duration of use of an integrated circuit device, the internal temperature can rise due to the heat generated by the operation of the circuits and the transistors on the device. If the internal temperature of the chip is not monitored and maintained within acceptable limits, the operating performance of the device may be impaired or, in a worst case scenario, the integrated circuit device may be destroyed. Heat management is even more problematic for integrated circuit devices that are formed on silicon-on-insulator (SOI) substrates. An SOI substrate includes a bulk silicon substrate, a buried insulation layer (BOX) and an active layer, wherein the BOX layer is positioned between the bulk substrate and the active layer. Semiconductor devices are formed in and above the active layer. The use of the SOI substrates is beneficial for the electrical performance characteristics of devices formed on such an SOI substrate because the combination of the BOX layer (which is typically made of silicon dioxide) and surrounding trench isolation structure completely isolates the semiconductor device formed within the trench isolation structure and above the BOX layer. However, the presence of the BOX layer does reduce the heat dissipation capability of SOI devices as compared to device formed on a bulk silicon substrate. Thus, monitoring and sensing the temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate substrate diode structure may be used wherein the electrical characteristics of the diode may be monitored to obtain regarding the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained from monitoring the substrate diode structure may depend significantly on the diode's characteristics, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. In SOI devices, a corresponding substrate diode structure, i.e., the respective PN junction, is typically formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements.
An illustrative trench isolation structure 14 is provided to electrically isolate the transistor 20. The substrate diode structure 101 also includes an N-doped well 28 formed in the bulk silicon layer 10C, and N+ doped region 32 and a P+ doped region 42 formed within the N-doped well 28. At the point of fabrication depicted in
A typical process flow for forming the substrate diode structure 101 will now be described. Typically, the N-doped well 28 is formed in the bulk silicon layer 10C prior to forming the trenches 31, 41 by performing a vertically-oriented ion implantation process with an N-type dopant through an implant mask (not shown), e.g., a photoresist mask, that locates the N-doped well 28 in the region of the device 100 where the cathode 30 and the anode 40 will be formed. Thereafter, the implant mask is stripped and a etch mask (not shown) is formed above the device 100 wherein the etch mask is patterned for the formation of the trenches 31, 41. One or more etching processes are then performed to form the trenched 31, 41. The etch mask is removed and first implant mask (not shown) is formed that covers the device 100 but exposes the trench 31. Then, a first vertically-oriented ion implantation process is performed with an N-type dopant to form the N+ doped region 32 within the N-doped well 28. The first implant mask is removed and a second implant mask (not shown) is formed that covers the device 100 but exposes the trench 41. Then, a second vertically-oriented ion implantation process is performed with a P-type dopant to form the P+ doped region 42 within the N-doped well 28. Thereafter, although not depicted in the drawings, metal silicide regions are formed on the N+ doped region 32 and the P+ doped region 42, and metal contacts are formed in the trenches 31, 41. In prior generation devices, the implantation processes performed to form the N+ doped region 32 and the P+ doped region 42 was part of the so-called deep source/drain implant processes performed to form the source/drain regions 22 on the transistor 20. However, in more recent generation devices, the desired dopant concentration of the N+ doped region 32 and the P+ doped region 42 is greater than can be obtained by combining such implant processes with the deep source/drain implant processes. Thus, separate ion implantation processes are typically now performed to form the N+ doped region 32 and the P+ doped region 42, as described above.
The present disclosure is directed to various novel methods of forming an anode and a cathode of a substrate diode.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various substrate diodes formed by angled ion implantation processes. In one illustrative example, a substrate diode device having an anode and a cathode is disclosed. In this example, the device includes a doped well positioned in a bulk layer of an SOI substrate, a first doped region positioned in the doped well, the first doped region being for one of the anode or the cathode, the first doped region having a first long axis and a second doped region positioned in the doped well, the second doped region being separate from the first doped region, the second doped region being for the other of the anode or the cathode, the second doped region having a second long axis that is oriented at an orientation angle with respect to the first long axis.
In another exemplary embodiment of the present disclosure, a substrate diode device includes, among other things, an N-doped well positioned in a bulk layer of an SOI substrate, and a substantially rectangularly shaped N+ doped region positioned in the N-doped well, wherein the substantially rectangularly shaped N+ doped region has a first long axis. The disclosed substrate diode device further includes a substantially rectangularly shaped P+ doped region positioned in the N-doped well, the substantially rectangularly shaped P+ doped region being separated from the N+ doped region and having a second long axis, wherein an orientation angle of the second long axis relative to the first long axis ranges from approximately 80-100 degrees.
In yet a further illustrative embodiment, a substrate diode device is disclosed herein that includes an N-doped well positioned in a bulk layer of an SOI substrate, the N-doped well having a substantially T-shaped configuration when viewed from above. The substrate diode device also includes, among other things, an N+ doped region positioned in the N-doped well, said N+ doped region having a first long axis and comprising a cathode of the substrate diode. Additionally, the substrate diode device further includes a P+ doped region positioned in the N-doped well, the P+ doped region having a second long axis and comprising an anode of the substrate diode, wherein an orientation angle of the second long axis relative to the first long axis is approximately 90 degrees, and wherein the P+ doped regions is separated from the N+ doped region by a portion of the N-doped well.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to
The trenches 231, 241 may or may not have the same dimensional characteristic or the same overall configuration. In the illustrative example depicted in
In contrast to the prior art substrate diode 101 described above with reference to
One illustrative method of forming the novel substrate diode 201 will now be described with reference to
Thereafter, the implant mask used to form the N-doped well 228 is stripped and a mask layer 260 is formed above the device 200 wherein the mask layer 260 is patterned for the formation of the trenches 231, 241. In one example, the mask layer 260 may be formed by depositing a layer of the masking material and thereafter forming a patterned photoresist mask above the layer of material. An etching process may then be performed through the photoresist mask to define the mask layer 260. The mask layer 260 may be comprised of a variety of materials such as carbon or an organic material, etc., and it may be formed by performing, for example, a chemical vapor deposition (CVD) process. In one example, the mask layer 260 may have a thickness ranging from 150-300 nm. One or more etching processes may then be performed through the mask layer 260 (functioning as an etch mask) to form the trenches 231, 241. The etching process performed to form the trenches 231, 241 may result in the tapering of the openings on the mask layer 260, as depicted in
The next steps will be discussed with reference to
The angle 257 (see
Next, as shown in
Of course, the trenches 231, 241 may have differing dimension and configurations, and the long axis 234, 244 of the trenches 231, 241 may be oriented at an angle 270 (see
Next, as shown in
Next, as shown in
The methods disclosed herein for forming the substrate diode 201 are much more efficient and cost effective than the illustrative prior art techniques described in the background section of this application for forming such structures. More specifically, by using the single mask layer 260 as an etch mask (to form the trenches 231, 241) and as an implant mask (for the implant processes 255N, 255P), the number of process operations is significantly reduced. Using the prior art techniques, separate implant masks was formed for each of the implant processes performed to form the doped regions 32, 42. As a result of using the mask layer 260, the formation and stripping of the additional implant mask used practicing the prior art techniques can be avoid, all of which reduces manufacturing time and reduces the overall cost of the resulting device.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1.-17. (canceled)
18. A substrate diode device having an anode and a cathode, the device comprising:
- a doped well positioned in a bulk layer of an SOI substrate;
- a first doped region positioned in said doped well, said first doped region being for one of said anode or said cathode, said first doped region having a first long axis; and
- a second doped region positioned in said doped well, said second doped region being separate from said first doped region, said second doped region being for the other of said anode or said cathode, second doped region having a second long axis that is oriented at an orientation angle ranging from 80-100 degrees with respect to said first long axis.
19. The device of claim 18, wherein said orientation angle is approximately 90 degrees.
20. The device of claim 18, wherein said doped well in an N-doped well, said first doped region is an N+ doped region and said second doped region is a P+ doped region.
21. The device of claim 18, wherein said doped well in an N-doped well, said first doped region is a P+ doped region and said second doped region is an N+ doped region.
22. The device of claim 18, wherein said first and second doped regions have the same configuration when viewed from above.
23. The device of claim 18, wherein said first and second doped regions have different configurations when viewed from above.
24. The device of claim 22, wherein said first and second doped regions both have rectangular configurations when viewed from above.
25. The device of claim 18, wherein said doped well has a T-shaped configuration when viewed from above.
26. A substrate diode device, comprising:
- an N-doped well positioned in a bulk layer of an SOI substrate;
- a substantially rectangularly shaped N+ doped region positioned in said N-doped well, said substantially rectangularly shaped N+ doped region having a first long axis; and
- a substantially rectangularly shaped P+ doped region positioned in said N-doped well, said substantially rectangularly shaped P+ doped region being separated from said N+ doped region and having a second long axis, wherein an orientation angle of said second long axis relative to said first long axis ranges from approximately 80-100 degrees.
27. The device of claim 26, wherein said orientation angle is approximately 90 degrees.
28. The device of claim 26, wherein N-doped well has a substantially T-shaped configuration when viewed from above.
29. The device of claim 26, wherein said N+ doped region is separated from said P+ doped region by a portion of said N-doped well.
30. The device of claim 26, wherein said N+ doped region comprises a cathode of said substrate diode and said P+ doped region comprises an anode of said substrate diode.
31. The device of claim 26, wherein said substrate diode is positioned adjacent to from a transistor, said transistor being electrically isolated from said substrate diode by a trench isolation structure.
32. The device of claim 26, wherein each of said N+ doped region and said P+ doped region comprise a metal silicide contact region.
33. A substrate diode device, comprising:
- an N-doped well positioned in a bulk layer of an SOI substrate, said N-doped well having a substantially T-shaped configuration when viewed from above;
- an N+ doped region positioned in said N-doped well, said N+ doped region having a first long axis and comprising a cathode of said substrate diode; and
- a P+ doped region positioned in said N-doped well, said P+ doped region having a second long axis and comprising an anode of said substrate diode, wherein an orientation angle of said second long axis relative to said first long axis is approximately 90 degrees, and wherein said P+ doped regions is separated from said N+ doped region by a portion of said N-doped well.
34. The device of claim 33, wherein each of said N+ doped region and said P+ doped region have a substantially rectangular configuration when viewed from above.
35. The device of claim 33, wherein a first end of said N+ doped region is positioned adjacent to a substantial mid-point of said P+ doped region, said first end of said N+ doped region being separated from said substantial mid-point of said P+ doped region by said portion of said N-doped well.
36. The device of claim 33, wherein a first end of said P+ doped region is positioned adjacent to a substantial mid-point of said N+ doped region, said first end of said P+ doped region being separated from said substantial mid-point of said N+ doped region by said portion of said N-doped well.
37. The device of claim 33, further comprising N+ doped halo regions positioned between said N+ doped region and said P+ doped region.
Type: Application
Filed: Jul 22, 2013
Publication Date: Nov 21, 2013
Applicant: GLOBALFOUNDRIES Inc. (Grand Cayman)
Inventors: Peter Baars (Dresden), Thilo Scheiper (Dresden)
Application Number: 13/947,793
International Classification: H01L 29/861 (20060101);