METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES
Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.
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The present invention generally relates to methods for fabricating FinFET integrated circuits, and more particularly relates to methods for fabricating and isolating FinFET integrated circuits on bulk semiconductor substrates.
BACKGROUNDAs integrated circuits (ICs) become larger and larger it becomes necessary to consider structures other than planar transistors to accommodate the ever increasing number of transistors that the circuits require. One such structure is the FinFET, a field effect transistor (FET), in which the channel of the transistor is formed along the vertical sidewalls of a thin semiconductor fin that extends upwardly from a semiconductor substrate. Because the channel is formed along a vertical fin sidewall rather than along the horizontal surface of the wafer, a wide channel (and hence high performance) can be achieved without increasing the horizontal surface area of the semiconductor substrate.
The fabrication of FinFET ICs, however, encounters some processing problems. Fin fabrication requires etching trenches into a semiconductor substrate to produce the vertical fins. The fins are usually formed in a wide array that extends across an entire IC chip. Among the problems encountered are the loading effects that arise when etching a plurality of fins. Larger open areas have a tendency to produce wide fins and deep trenches while more closely spaced fins are thin with much shallower trenches. Such variance in fin width and trench depth makes reliable processing difficult because the etch results become layout and thus product dependent. A common solution to the etch pattern loading problem is to include dummy fins to achieve a regular array in which all fins can be etched equally. If the FinFET is fabricated on a semiconductor-on-insulator (SOI) substrate, the removal of the dummy fins to achieve the necessary fin-fin electrical isolation is relatively easy. On bulk semiconductor wafers, however, such dummy fin removal and electrical isolation is not easy.
Accordingly, it is desirable to provide methods for fabricating FinFET integrated circuits on bulk semiconductor substrates. In addition, it is desirable to provide methods for fabricating FinFET integrated circuits having the necessary electrical isolation between fins. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
BRIEF SUMMARYMethods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.
In accordance with a further embodiment, a semiconductor substrate is provided and a patterned hard mask is formed overlying the semiconductor substrate, the patterned hard mask defining locations of a plurality of parallel fins extending in a first direction. A first etch mask exposing a first portion of the patterned hard mask is formed overlying a logic portion of the integrated circuit and a second portion of the patterned hard mask is formed overlying a memory portion of the integrated circuit, the first mask extending in a second direction including a portion substantially perpendicular to the first direction. Portions of the patterned hard mask are etched using the first etch mask to remove the first portion and the second portion. The semiconductor substrate is etched using remaining portions of the patterned hard mask as an etch mask to form a plurality of semiconductor fins separated by etched trenches. A second etch mask is formed overlying the plurality of semiconductor fins and portions of the plurality of semiconductor fins exposed through the second etch mask are etched to at least partially remove portions of the plurality of semiconductor fins. An insulator material is deposited to fill the trenches and to cover the etched portions of the plurality of semiconductor fins.
In accordance with yet another embodiment, a semiconductor substrate is provided and a first mask is formed overlying the semiconductor substrate and defining a plurality of parallel fin locations extending in a first direction and selectively cut in a second direction. The semiconductor substrate is etched using the first mask as an etch mask to form a plurality of parallel fins extending in a first direction and separated by etched trenches, at least selected ones of the parallel fins being terminated in the second direction. A second mask is formed overlying the fins and exposing dummy ones of the plurality of parallel fins. At least a portion of the dummy ones of the plurality of parallel fins are etched to reduce the height thereof, and the trenches are filled and the etched dummy fins are covered with an insulating material.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
Methods are provided for the fabrication of FinFET integrated circuits (ICs) in accordance with various embodiments. The embodiments described and illustrated below will find application in ICs of all sizes, but are particularly useful in the fabrication of large ICs such as those that incorporate both logic circuits (which will likely vary greatly from design to design and across a design) and memory circuits such as static random access memory (SRAM) circuits (that will likely be very uniform across a design and from design to design). The memory circuit portion of an IC is fabricated in an array of fins and is somewhat tolerant of etch pattern loading because the memory circuit portion is usually a highly regular array of memory cells that may be repeated many thousands of times across the IC. Because the array of memory cells is so regular, both on a particular circuit design and from design to design, any variations that result from etch pattern loading can be at least partially compensated for in the design of the memory cell. The logic portion of a FinFET IC is fabricated in an array of closely spaced fins (usually more closely spaced than in the memory portion) in which etch pattern loading must be minimized. Etch pattern loading can cause variances in the width of fins and in the depth of the trenches between fins. The effects of etch pattern loading is illustrated in
The method for fabricating FinFET IC 70 continues, in accordance with one embodiment, as illustrated in
As illustrated in
When semiconductor fins are formed everywhere in order to minimize etch pattern loading and to maintain fin etch uniformity, selected fins and portions of fins (both collectively referred to as “dummy fins”) must be cut away where the fins are not electrically necessary. Dummy fins are reduced in height so as to effectively be removed and active fins remain. In the direction parallel to the fins (the X-direction as indicated in subsequent FIGURES) dummy fins must be removed to provide isolation between transistors of opposite polarity (NFET and PFET). In the direction perpendicular to the fins (the Y-direction) dummy fins must be removed to provide isolation between transistors of the same polarity. It would be difficult to entirely remove the necessary dummy fins in both the X- and Y-directions and to still maintain the necessary dimensional controls. An etchant would be required that can non-selectively etch a planarizing layer, oxide, nitride, and semiconductor material to a depth of 300-400 nm while maintaining critical dimensions and overlay tolerances within a line-space pitch of only 40-50 nm.
The method for fabricating a FinFET IC in accordance with one embodiment continues by using the modified hard mask as an etch mask to etch deep trenches 110 into semiconductor substrate 72 to form a plurality of semiconductor fins 112 extending upwardly from the substrate and separated by the trenches 110 as illustrated in cross section in
After etching trenches 110 to define fins 112, the trenches are filled with a fill material such as an organic planarizing layer (OPL) 118 as illustrated in
As illustrated in
After removing the selected dummy fins using lithographic patterning layer 122, the method for fabricating a FinFET IC continues, in accordance with an embodiment, as illustrated in cross section in
The method for fabricating a FinFET IC continues as illustrated in
As illustrated in
After formation of the electrically active fin portions 140 and the insulating oxide (130 plus 132) between the fins, a gate structure is formed overlying the electrically active fins as illustrated in cross section in
In accordance with an alternate embodiment, a hard mask such as that illustrated in
In accordance with this alternate embodiment, an organic planarizing layer is deposited to fill the trenches between the fins. A masking layer, such as a patterned layer of photoresist is formed overlying the OPL. The masking layer is patterned with pattern that is the composite of the masks 106 and 122 (illustrated in
The composite mask is used as an etch mask to etch through the OPL layer and to etch selected portions of the selected fins exposed through the mask. As noted above, a process for completely removing the selected fins and portions of fins would be complex and difficult carry out with high yield. In accordance with this embodiment, however, the fins are only partially removed. The top portion of the selected fins is etched to reduce the height of the fins to a height such as indicated by arrow 128 in
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. For example, the foregoing description specifically details method steps for the fabrication of a FinFET IC that includes both a logic portion and a memory portion, specifically an SRAM portion. The invention is also applicable to IC that include only a logic portion or only a memory portion and to ICs in which the memory portion is of some other configuration than an SRAM. Additionally, the foregoing description details steps by which the patterned hard mask is formed by a SIT process, but those of skill in the art will understand that there are other methods to form the hard mask. It should also be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof.
Claims
1. A method for fabricating a FinFET integrated circuit comprising:
- providing a semiconductor substrate;
- forming a patterned hard mask overlying the semiconductor substrate, the patterned hard mask defining locations of a regular array of a plurality of fins;
- removing portions of the patterned hard mask using a cut mask to form a modified hard mask;
- etching the substrate using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches;
- at least partially removing selected ones of the plurality of fins to form isolation regions; and
- depositing an insulating material to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins,
- wherein at least partially removing selected ones of the plurality of fins comprises: etching dummy fins positioned between regions of the integrated circuit comprising transistors of opposite polarity; etching portions of ones of the plurality of fins to provide isolation between transistors of the integrated circuit of the same polarity; depositing an organic planarizing layer to fill the trenches; forming a photolithographic mask layer overlying the organic planarizing layer and exposing a portion of the organic planarizing layer overlying dummy fins and a portion of the organic planarizing layer overlying the portions of ones of the plurality of fins; etching the organic planarizing layer and a top portion of the dummy fins and a top portion of the portions of ones of the plurality of fins; removing the organic planarizing layer; partially filling the trenches with a flowable chemical vapor deposited oxide; depositing a high density plasma oxide overlying the flowable chemical vapor deposited oxide; and planarizing the high density plasma oxide and removing a top portion of the fins.
2. The method of claim 1 wherein forming a patterned hard mask comprises:
- depositing a layer of hard mask material overlying the semiconductor substrate;
- depositing a layer of mandrel-forming material overlying the layer of hard mask material;
- patterning the layer of mandrel-forming material to form a plurality of mandrels;
- forming sidewall spacers on the mandrels;
- removing the mandrels; and
- etching the layer of hard mask material using the sidewall spacers as etch masks.
3. The method of claim 1 wherein forming a patterned hard mask comprises forming a plurality of elongated, substantially parallel hard masks extending in a first direction.
4. The method of claim 3 wherein removing portions of the patterned hard mask comprises removing portions of the patterned hard mask with a cut mask aligned substantially along a second direction perpendicular to the first direction to define regions of isolation between transistors of like polarity.
5. (canceled)
6. The method of claim 1 forming a patterned hard mask comprises forming a first plurality of elongate, substantially parallel lines having a first line-space pitch and a second plurality of elongate, substantially parallel lines having a second line-space pitch different than the first line-space pitch.
7. The method of claim 6 wherein removing portions of the patterned hard mask comprises using a first cut mask in the first plurality of elongate, substantially parallel lines and a second cut mask in the second plurality of elongate, substantially parallel lines.
8. (canceled)
9. The method of claim 1 wherein depositing an insulating material comprises:
- depositing an oxide to fill the trenches between fins;
- planarizing the oxide;
- removing any patterned hard mask remaining on the fins; and
- recessing the oxide to expose a top portion of the fins.
10. A method for fabricating a FinFET integrated circuit comprising:
- providing a semiconductor substrate;
- etching trenches into the semiconductor substrate to form a plurality of fins having a first height;
- etching selected ones of the plurality of fins to reduce the height thereof to a second height less than the first height;
- depositing an insulator material to form an insulator layer having a thickness greater than the first height and covering the selected ones of the plurality of fins,
- wherein etching selected ones of the plurality of fins comprises: etching dummy fins positioned between regions of the integrated circuit comprising transistors of opposite polarity; etching portions of ones of the plurality of fins to provide isolation between transistors of the integrated circuit of the same polarity; depositing an organic planarizing layer to fill the trenches; forming a photolithographic mask layer overlying the organic planarizing layer and exposing a portion of the organic planarizing layer overlying dummy fins and a portion of the organic planarizing layer overlying the portions of ones of the plurality of fins; etching the organic planarizing layer and a top portion of the dummy fins and a top portion of the portions of ones of the plurality of fins; removing the organic planarizing layer; partially filling the trenches with a flowable chemical vapor deposited oxide; depositing a high density plasma oxide overlying the flowable chemical vapor deposited oxide; and planarizing the high density plasma oxide and removing a top portion of the fins.
11. The method of claim 10 wherein etching trenches comprises:
- forming a silicon nitride hard mask comprising a first plurality of parallel lines having a first line-space pitch for forming a logic portion of the integrated circuit and a second plurality of parallel lines having a second line-space pitch different than the first line-space pitch for forming a memory portion of the integrated circuit; and
- etching the semiconductor substrate using the silicon nitride hard mask as an etch mask.
12. The method of claim 10 wherein depositing an insulator material comprises:
- filling the trenches with an oxide;
- planarizing the oxide; and
- removing a top portion of the oxide to expose a top portion of the plurality of fins other than the selected ones.
13.-15. (canceled)
16. The method of claim 10 further comprising removing a top portion of the planarized high density plasma oxide to expose a top portion of the semiconductor fins.
17. A method for fabricating a FinFET integrated circuit comprising:
- providing a semiconductor substrate;
- forming a first mask overlying the semiconductor substrate and defining a plurality of parallel fin locations extending in a first direction and selectively cut in a second direction;
- etching the semiconductor substrate using the first mask as an etch mask to form a plurality of parallel fins extending in a first direction and separated by etched trenches, at least selected ones of the parallel fins being terminated in the second direction;
- forming a second mask overlying the fins and exposing dummy ones of the plurality of parallel fins;
- etching at least a portion of the dummy ones of the plurality of parallel fins to reduce the height thereof; and
- filling the trenches and covering the etched dummy ones with an insulating material,
- wherein etching at least a portion of the dummy ones of the plurality of fins comprises: etching portions of the dummy ones of the plurality of fins to provide isolation between transistors of the integrated circuit of the same polarity; depositing an organic planarizing layer to fill the trenches; forming a photolithographic mask layer overlying the organic planarizing layer and exposing a portion of the organic planarizing layer overlying the dummy ones; etching the organic planarizing layer and a top portion of the dummy ones; removing the organic planarizing layer; partially filling the trenches with a flowable chemical vapor deposited oxide; depositing a high density plasma oxide overlying the flowable chemical vapor deposited oxide; and planarizing the high density plasma oxide and removing a top portion of the fins.
18. The method of claim 17 further comprising etching the insulating material to expose a top portion of the plurality of parallel fins but leaving the insulating material overlying the etched dummy ones.
19. The method of claim 17 wherein forming a first mask comprises forming a first mask defining a first group of fin locations having a first line-space pitch and a second group of fin locations having a second line-space pitch different than the first line-space pitch.
20. The method of claim 17 wherein forming a first mask comprises depositing a layer of silicon nitride overlying the semiconductor substrate and patterning the layer of silicon nitride by a sidewall image transfer technique.
Type: Application
Filed: May 17, 2012
Publication Date: Nov 21, 2013
Applicant: (Grand Cayman)
Inventors: Andy C. Wei (Queensbury, NY), Francis C. Tambwe (Malta, NY), Frank Scott Johnson (Wappingers Falls, NY)
Application Number: 13/474,443
International Classification: H01L 21/762 (20060101);