METHODS OF PERFORMING HIGHLY TILTED HALO IMPLANTATION PROCESSES ON SEMICONDUCTOR DEVICES
One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
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1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of performing highly tilted halo implantation processes on semiconductor devices such as transistors.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors are typically either NFET devices or PFET devices. During the fabrication of complex integrated circuits, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions. The channel length of a MOS transistor is generally considered to be the lateral distance between the source/drain regions.
Ion implantation is a technique that is employed in many technical fields to implant dopant ions into a substrate so as to alter the characteristics of the substrate or of a specified portion thereof. The rapid development of advanced devices in the semiconductor industry is based on, among other things, the ability to generate highly complex dopant profiles within tiny regions of a semiconducting substrate by performing advanced implantation techniques through a masking layer. In the case of an illustrative transistor, ion implantation may be used to form various doped regions, such as halo implant regions, extension implant regions and deep source/drain implant regions, etc.
An illustrative ion implantation sequence for forming various implant regions for an illustrative prior art transistor 100 will now be discussed with reference to
The masking layers that would be used during the implantation sequence shown in
Next, as shown in
Then, as shown in
Thereafter, as shown in
As shown in
Such a two-step halo implantation process to form halo implant regions where the transistors are oriented at an angle of about 90 degrees relative to one another limits what can be done to improve device performance. For example, the implantation parameters for the second halo implant process 50H may need to be varied as compared to such parameters used during the first halo implant process 40H so as to change various performance characteristics of the transistor 50, e.g., the implantation dose during the second halo implant process 50H may need to be increased to increase the threshold voltage of the transistor 50 and to reduce its drive current until such time as the transistor 50 meets pre-established performance criteria. However, increasing the dopant dose employed during the halo implant process 50H may adversely affect the performance characteristics of other devices formed above the substrate that are exposed to the halo implant process 50H. For example, an increase in the dopant dose employed in the halo implant process 50H may, undesirably, increase the capacitance of, for example, a large area diode (not shown). The inventors have discovered that desirable changes to drive current of the transistor 50 may be accomplished by performing the halo implant process 50H at a higher implant angle without adversely affecting the capacitance of the illustrative large area diode. Unfortunately, as noted above with respect to
Many integrated circuit products require the formation of PFET and NFET devices on a common substrate. As is well known to those skilled in the art, manufacturing each of the devices involves the use of techniques that may be common to both types of devices and some techniques that are unique to each type of device. In the end, a process flow must be established that permits the most effective and efficient manufacturing of such devices as possible, typically in as few process steps as possible. For example, in a situation that involves both standard and horizontally oriented PFET transistors and standard NFET transistors, an illustrative process flow may include the following: Initially, isolation structures, such as trench isolation structures are formed in a substrate to define active regions for the various devices. Thereafter, the NFET device regions are masked and a first tilted halo implant process is performed for the standard PFET transistor. Thereafter, a vertically oriented extension implant processes is performed to form extension implant regions for both the standard and horizontal PFET transistors. Next, the substrate is rotated about 90 degrees and a second tilted halo implant process is performed to form halo implant regions in the horizontal PFET transistor. Of course, the first angled halo implant process could have been performed on the horizontal PFET transistor if desired. The halo implantation processes performed on the PFET transistors may be performed at an angle of about 30 degrees (relative to the vertical). After this implant sequence, embedded silicon/germanium (SiGe) source/drain regions are form for both the standard and horizontal PFET transistors using etching and epitaxial deposition processes known to those skilled in the art. The SiGe source/drain regions are typically doped in situ, although dopants may be introduced into the SiGe source/drain regions via ion implantation if desired. Thereafter, the masking layer used to mask the NFET device regions is removed and the gate cap layers, like the gate cap layer 14C depicted in
The present disclosure is directed to various methods of performing highly tilted halo implantation processes on semiconductor devices, such as transistors, that may avoid, or at least reduce, the effects of one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of performing highly tilted halo implantation processes on semiconductor devices such as transistors. One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
Another illustrative method disclosed herein involves forming first, second and third gate structures, a first PFET transistor, a second PFET transistor device and an NFET transistor, wherein each of the gate structures includes a cap layer and wherein the first and second PFET transistors are oriented transverse to one another, performing a first halo ion implant process at a first tilt angle to form first halo implant regions for the first PFET transistor with the cap layer in position in the first gate structure, removing the cap layer from the first, second and third gate structures, forming halo implant regions, extension implant regions and source/drain implant regions for the NFET transistor, and, after forming the doped regions for the NFET transistor, performing a second halo ion implant process at a second tilt angle to form second halo implant regions for the second PFET transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate, and wherein the second tilt angle is greater than the first tilt angle.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of performing highly tilted halo implantation processes on semiconductor devices such as transistors. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices and technologies, e.g., NFET, PFET, CMOS, etc., and is readily applicable to a variety of integrated circuit products, including, but not limited to, ASIC's, logic devices, memory devices, etc. With reference to the attached drawings, various illustrative embodiments of the methods disclosed herein will now be described in more detail.
As shown in
The gate structures 114P, 114N depicted herein are intended to be schematic and representative in nature, as the materials of construction used in the gate structures 114P in the first and second PFET transistors 100P1, 100P2 may be different than the gate structure 114N in the NFET transistor 100N, e.g., the PFET transistors 100P1, 100P2 may have multiple layers of conductive metal, etc. However, in some applications, the gate structures 114P, 114N may be comprised of the same basic materials, e.g., both gate structures 114P and 114N may comprise a silicon dioxide gate insulation layer and a polysilicon gate electrode. In general, the gate insulation layer 114A may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, a high-k (k value greater than 10) insulating material. The gate electrode 114B may be comprised of one or more layers of conductive materials, such as polysilicon, a metal, etc. The gate structures 114P, 114N depicted in
In one illustrative embodiment, the next process operation involves the formation of extension implant regions on both of the first and second PFET transistors 100P1, 100P2 and the formation of halo implant regions on one of the first and second PFET transistors 100P1, 100P2. In the depicted example, the halo implant regions are first formed on the first PFET transistor 100P1. However, as will be understood by those skilled in that art after a complete reading of the present application, the halo implant regions could have been formed first on the second PFET transistor 100P2. Moreover, the implant process to form the halo regions on one of the first and second PFET transistors 100P1, 100P2 and the implant process performed to form extension implant regions on both of the first and second PFET transistors 100P1, 100P2 may be performed in any order. In the illustrative example described herein, the halo implantation process is performed prior to the extension implant process, although such an order of implantation steps should not be considered to be a limitation of the presently disclosed inventions.
As shown in
Next, as shown in
Next, as shown in
Thereafter, as shown in
Then, as shown in
Next, as shown in
In one illustrative process flow, the next series of process operations performed on the device 100 involves forming halo implant regions, extension implant regions and source/drain implant regions for the NFET transistor 100N while masking both of the first and second PFET transistors 100P1, 100P2. Accordingly, as shown in
Next, as shown in
Next, as shown in
Thus, at this point in the fabrication process: (1) extension implant regions 140A have been formed for both the first and second PFET transistors 100P1, 100P2, while halo implant regions 130 have only been formed on the first PFET transistor 100P1; and (2) halo implant regions 150A, extension implant regions 160A and source/drain implant regions 170A have been formed on the NFET transistor 100N. Of course, the first and second PFET transistors 100P1, 100P2 were masked during the various implant processes that were performed on the NFET transistor 100N, as described above.
As shown in
Thereafter, the ion implant masking layer 172 is removed and a heating or anneal process is performed to form the final source/drain regions (not shown) for the transistors 100P1, 100P2, 100N. This heating process repairs the damage to the lattice structure of the substrate 110 as a result of the various ion implantation processes described above and it activates the implanted dopant materials, i.e., the implanted dopant materials are incorporated into the silicon lattice. The various implantation processes described above may be performed using well-known ion implantation systems.
Another illustrative aspect of forming doped regions on transistor devices will now be further described with reference to
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A method, comprising:
- forming a first gate structure for a first transistor device and a second gate structure for a second transistor device above a semiconducting substrate, wherein said first and second gate structures comprise a cap layer and wherein said first and second transistors are oriented transverse to one another;
- performing a first halo ion implant process to form first halo implant regions in said substrate for said first transistor with said cap layer in position in said first gate structure of said first transistor;
- removing said cap layer from both of said first and second gate structures; and
- after removing said cap layer from both of said first and second gate structures, performing a second halo ion implant process to form second halo implant regions in said substrate for said second transistor, wherein said first and second halo implant processes are performed at transverse angles relative to said substrate and wherein both of said first and second transistor devices are unmasked during said second halo ion implant process and fully exposed to said second halo ion implantation process.
2. The method of claim 1, wherein said first and second transistors are PFET transistors.
3. The method of claim 1, wherein said first and second transistors are NFET transistors.
4. The method of claim 1, wherein said first and second gate structures comprise a gate electrode and a gate insulation layer that are sacrificial structures.
5. The method of claim 1, wherein said first and second gate structures comprise a gate electrode and a gate insulation layer that are a final gate electrode and a gate insulation layer of a final integrated circuit product.
6. The method of claim 1, wherein said first and second gate structures are comprised of the same materials.
7. The method of claim 1, wherein said first and second gate structures are comprised of different materials.
8. (canceled)
9. The method of claim 1, further comprising, after removing said cap layer, performing an etching process to reduce an original size of a gate electrode of said second gate structure and thereafter performing said second halo implant process.
10. The method of claim 1, wherein said first halo implant process is performed at a first tilt angle and said second halo implant process is performed at a second tilt angle, wherein said second tilt angle is greater than said first tilt angle.
11. The method of claim 10, wherein said second tilt angle is at least 5 degrees greater than said first tilt angle.
12. The method of claim 10, wherein said first tilt angle is an angle within the range of about 20-30 degrees and said second tilt angle is an angle within the range of about 35-45 degrees.
13. A method, comprising:
- forming a first gate structure for a first PFET transistor device and a second gate structure for a second PFET transistor device above a semiconducting substrate, wherein said first and second gate structures comprise a cap layer and wherein said first and second PFET transistors are oriented transverse to one another;
- forming a third gate structure for an NFET transistor above said semiconducting substrate, wherein said third gate structure comprises a cap layer;
- performing a first halo ion implant process at a first tilt angle to form first halo implant regions in said substrate for said first PFET transistor with said cap layer in position in said first gate structure of said first PFET transistor;
- removing said cap layer from said first gate structure of said first PFET transistor and from said second gate structure of said second PFET transistor; and
- after removing said cap layer from said first gate structure of said first PFET transistor and from said second gate structure of said second PFET transistor, performing a second halo ion implant process at a second tilt angle to form second halo implant regions in said substrate for said second PFET transistor, wherein said first and second halo implant processes are performed at transverse angles relative to said substrate, wherein said second tilt angle is greater than said first tilt angle and wherein and wherein both of said first and second PFET transistor devices are unmasked during said second halo ion implant process and fully exposed to said second halo ion implantation process.
14. The method of claim 13, wherein said second tilt angle is at least 5 degrees greater than said first tilt angle.
15. The method of claim 13, wherein said first tilt angle is an angle within the range of about 20-30 degrees and said second tilt angle is an angle within the range of about 35-45 degrees.
16. The method of claim 13 further comprising:
- after removing said cap layer from said second gate structure, masking said first and second PFET transistors; and
- performing a plurality of ion implantation processes to form halo implant regions, extension implant regions and source/drain implant regions in said substrate for said NFET transistor.
17. The method of claim 16, wherein said step of performing said second halo implant process is performed after said halo implant regions, extension implant regions and source/drain implant regions are formed in said substrate for said NFET transistor.
18. The method of claim 13, further comprising, after removing said cap layer from said second gate structure, performing an etching process to reduce an original size of a gate electrode of said second gate structure and thereafter performing said second halo implant process.
19. A method, comprising:
- forming a first gate structure for a first PFET transistor device and a second gate structure for a second PFET transistor device above a semiconducting substrate, wherein said first and second gate structures comprise a cap layer and wherein said first and second PFET transistors are oriented transverse to one another;
- forming a third gate structure for an NFET transistor above said semiconducting substrate, wherein said third gate structure comprises a cap layer;
- performing a first halo ion implant process at a first tilt angle to form first halo implant regions in said substrate for said first PFET transistor with said cap layer in position in said first gate structure of said first PFET transistor;
- removing said cap layer from said first, second and third gate structures;
- performing a plurality of ion implantation processes to form halo implant regions, extension implant regions and source/drain implant regions in said substrate for said NFET transistor, and
- after forming said halo implant regions, extension implant regions and source/drain implant regions for said NFET transistor, performing a second halo ion implant process at a second tilt angle to form second halo implant regions in said substrate for said second PFET transistor, wherein said first and second halo implant processes are performed at transverse angles relative to said substrate, and wherein said second tilt angle is greater than said first tilt angle.
20. The method of claim 19, further comprising, after removing said cap layer from said first, second and third gate structures, performing an etching process to reduce an original size of a gate electrode of at least said second gate structure and thereafter performing said second halo implant process.
21. The method of claim 19, wherein said second tilt angle is at least 5 degrees greater than said first tilt angle.
22. The method of claim 19, wherein said first tilt angle is an angle within the range of about 20-30 degrees and said second tilt angle is an angle within the range of about 35-45 degrees.
23. A method, comprising:
- forming a first gate structure for a first transistor device and a second gate structure for a second transistor device above a semiconducting substrate, wherein said first and second gate structures comprise a cap layer and wherein said first and second transistors are oriented transverse to one another;
- performing a first halo ion implant process to form first halo implant regions in said substrate for said first transistor with said cap layer in position in said first gate structure of said first transistor;
- removing said cap layer from at least said second gate structure of said second transistor;
- after removing said cap layer, performing an etching process to reduce an original size of a gate electrode of said second gate structure; and
- after performing said etching process, performing a second halo ion implant process to form second halo implant regions in said substrate for said second transistor, wherein said first and second halo implant processes are performed at transverse angles relative to said substrate.
24. A method, comprising:
- forming a first gate structure for a first PFET transistor device and a second gate structure for a second PFET transistor device above a semiconducting substrate, wherein said first and second gate structures comprise a cap layer and wherein said first and second PFET transistors are oriented transverse to one another;
- forming a third gate structure for an NFET transistor above said semiconducting substrate, wherein said third gate structure comprises a cap layer;
- performing a first halo ion implant process at a first tilt angle to form first halo implant regions in said substrate for said first PFET transistor with said cap layer in position in said first gate structure of said first PFET transistor;
- removing said cap layer from said second gate structure of said second PFET transistor;
- after removing said cap layer from said second gate structure of said second PFET transistor, performing an etching process to reduce an original size of a gate electrode of said second gate structure;
- after performing said etching process, performing a second halo ion implant process at a second tilt angle to form second halo implant regions in said substrate for said second PFET transistor, wherein said first and second halo implant processes are performed at transverse angles relative to said substrate, and wherein said second tilt angle is greater than said first tilt angle.
Type: Application
Filed: Jun 4, 2012
Publication Date: Dec 5, 2013
Applicant: GLOBALFOUNDRIES INC. (Grand Cayman)
Inventors: Stefan Flachowsky (Dresden), Jan Hoentschel (Dresden), Thilo Scheiper (Dresden)
Application Number: 13/487,351
International Classification: H01L 21/8238 (20060101); H01L 21/8234 (20060101);