METHOD FOR FORMING TRENCH ISOLATION
A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench.
Latest Anpec Electronics Corporation Patents:
This application is a continuation of U.S. application Ser. No. 13/628,051 filed Sep. 27, 2012, which is incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates generally to the field of semiconductor process. More particularly, the present invention relates to a trench isolation process that utilizes spacer process and/or thermal oxidation to achieve void-free trench fill.
2. Description of the Prior Art
In the application of the integrated circuit, the different functional elements are often built on a single chip. In order to ensure that each individual component does not interfere with other components around, the electrical isolation between circuit components is particularly important.
Local oxidation of silicon (LOCOS) is a well known and common isolation method. The LOCOS process is not complex, and has the advantage of low cost. However, with the progress of process capability as well as scaling of elements, the problems such as bird's beak and field oxide thinning have become worse. Therefore, shallow trench isolation (STI) process has been developed.
The STI process includes first etching trench around the active area and then filling the trench with insulating material to isolate the active area. Although the shortcomings of LOCOS can be overcome by the STI process, but it also has the problems of dishing effect and sub-threshold kink effect. Further, with the components miniature, void-free trench fill has become more difficult to achieve.
SUMMARY OF THE INVENTIONTherefore, it is one objective of the present invention to provide an improved trench isolation process, in combination with spacer process and/or thermal oxidation to achieve void-free trench fill, without increasing the process complexity.
According to one embodiment, a trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench.
According to another embodiment, a method for forming trench isolation is disclosed. A substrate having thereon a pad layer and a hard mask layer is provided. At least one opening is then formed in the hard mask layer. A spacer is then formed on a sidewall of the opening. The substrate is etched through the opening to thereby form a trench. A thermal oxidation process is performed, using the spacer as a protection layer, to oxidize the substrate within the trench until the trench is completely filled up with an oxide layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
As shown in
As shown in
As shown in
As shown in
As shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A method for forming trench isolation, comprising:
- providing a substrate having thereon a pad layer and a hard mask layer;
- forming at least one opening in the hard mask layer;
- forming a spacer on a sidewall of the opening;
- after forming the spacer, etching the substrate through the opening to thereby form a trench; and
- performing a thermal oxidation process, using the spacer as a protection layer, to oxidize the substrate within the trench until the trench is completely filled up with an oxide layer.
2. The method for forming trench isolation according to claim 1 wherein the pad layer is a silicon oxide pad layer.
3. The method for forming trench isolation according to claim 1 wherein the spacer is a silicon nitride spacer.
4. The method for forming trench isolation according to claim 1 wherein the thermal oxidation process is performed at a temperature between 800-1200° C., using steam, oxygen, or steam or oxygen containing hydrogen chloride or nitrogen, under process pressure ranging 600-760 torr.
5. The method for forming trench isolation according to claim 1 wherein the spacer has a thickness that is smaller than a quarter of a width of the opening.
6. The method for forming trench isolation according to claim 1 wherein the oxide layer has a wedge-shaped recess structure on its surface.
7. The method for forming trench isolation according to claim 1 wherein a recess region is formed in the substrate through the opening after forming the opening in the hard mask and before forming the spacer.
Type: Application
Filed: Dec 9, 2013
Publication Date: Mar 27, 2014
Applicant: Anpec Electronics Corporation (Hsin-Chu)
Inventors: Yung-Fa Lin (Hsinchu City), Chia-Hao Chang (Hsinchu City)
Application Number: 14/100,023
International Classification: H01L 21/762 (20060101);