METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS
A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.
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This Application is a division of U.S. patent application Ser. No. 12,983,477 filed on Jan. 3, 2011 which is a division of U.S. patent application Ser. No. 11/690,258 filed on Mar. 23, 2007, now U.S. Pat. No. 7,892,928 issued Feb. 22, 2011.
FIELD OF THE INVENTIONThe present invention relates to the field of method of forming asymmetric spacers; more specifically, it relates to forming spacers of different widths on opposite sides of a raised line, methods of fabricating semiconductor devices using asymmetric spacers and semiconductor having asymmetrical source/drain structures.
BACKGROUND OF THE INVENTIONAsymmetric devices have drawn increasing attention as a method to suppress short channel effects in metal-oxide-silicon field effect transistors (MOSFETS). However, current technology forms asymmetrical devices by adding additional photolithographic process steps to existing methods. Additional photolithographic processes require additional photomasks and exposure tools and add additional time to the fabrication process, making such processes more costly and adversely effecting yield. Therefore, there is a need for a method of fabricating asymmetrical structures, including MOSFETs that do not require photolithographic steps to generate asymmetrical spacers.
SUMMARY OF THE INVENTIONA first aspect of the present invention is a method, comprising: (a) forming on a top surface of a substrate, a structure comprising a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls and to the top surface of the substrate; after (a), (b) forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; after (b), (c) tilting the substrate about an axis parallel to the longitudinal axis relative to a flux of reactive ions directed toward the top surface of the substrate, the flux of reactive ions striking the conformal layer at an angle less than 90° and greater than zero degrees relative to the top surface of the substrate; and after (c), (d) exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate by the flux of reactive ions except in regions of the top surface of the substrate immediately adjacent to the sidewalls of the structure, the exposing leaving a first spacer on the first sidewall and a second spacer on the second sidewall.
A second aspect of the present invention is a structure, comprising: a silicon layer having a top surface; a gate stack comprising a gate dielectric layer on the top surface of the silicon layer and an electrically conductive gate electrode on a top surface of the gate electrode or comprises the gate electrode on the gate dielectric layer, the gate dielectric layer extending along the top surface of the silicon layer on either side of the gate stack; a first spacer on a first sidewall of the gate stack and a second spacer on a second and opposite sidewall of the gate stack, a first width of the first spacer measured from the first sidewall in a first direction perpendicular to the first sidewall is less than a second width of the second spacer measured from the second sidewall in a second direction perpendicular to the second sidewall, the first and second spacers decreasing in width from a bottom surface of the gate stack to a top surface of the gate stack; a first source/drain extension in the silicon layer under the first spacer and a second source/drain extension in the silicon layer under the second spacer, the first and second source/drain extensions separated by a channel region in the layer under the gate stack; a first source/drain in the silicon layer abutting the first source/drain extension and extending away from the channel region and a second source/drain in the silicon layer abutting the second source/drain extension and extending away from the channel region, the first source/drain and the second source/drain both comprising silicon germanium or both comprising carbon-doped silicon.
A third aspect of the present invention is a structure, comprising: a silicon layer having a top surface; a gate stack comprising a gate dielectric layer on the top surface of the silicon layer and an electrically conductive gate electrode on a top surface of the gate electrode or comprises the gate electrode on the gate dielectric layer, the gate dielectric layer extending along the top surface of the silicon layer on either side of the gate stack; a first spacer on a first sidewall of the gate stack and a second spacer on a second and opposite sidewall of the gate stack, a first width of the first spacer measured from the first sidewall in a first direction perpendicular to the first sidewall equal to a second width of the second spacer measured from the second sidewall in a second direction perpendicular to the second sidewall, the first and second spacers decreasing in width from a bottom surface of the gate stack to a top surface of the gate stack; a first source/drain extension in the silicon layer under the first spacer and a second source/drain extension in the silicon layer under the second spacer, the first and second source/drain extensions separated by a channel region in the layer under the gate stack; a first diffused-source/drain in the silicon layer abutting the first source/drain extension and extending away from the channel region and a second diffused-source/drain in the silicon layer abutting the second source/drain extension and extending away from the channel region; and a first hetero-source/drain in the silicon layer, abutting the first source/drain extension and extending away from the channel region and a second hetero-source/drain in the silicon layer separated from the second source/drain extension by the second diffused-source/drain and extending away from the channel region, the first hetero-source/drain and the second hetero-source/drain both comprising silicon germanium or both comprising carbon-doped silicon.
A fourth aspect of the present invention is a structure, comprising: a silicon layer having a top surface; a gate stack comprising a gate dielectric layer on the top surface of the silicon layer and an electrically conductive gate electrode on a top surface of the gate electrode or comprises the gate electrode on the gate dielectric layer, the gate dielectric layer extending along the top surface of the silicon layer on either side of the gate stack; a first spacer on a first sidewall of the gate stack, a second spacer on a second and opposite sidewall of the gate stack and a third spacer on the second spacer, a first width of the first spacer measured from the first sidewall in a first direction perpendicular to the first sidewall equal to a second width of the second spacer measured from the second sidewall in a second direction perpendicular to the second sidewall, the first, second and third spacers decreasing in width from a bottom surface of the gate stack to a top surface of the gate stack; a first source/drain extension in the silicon layer under the first spacer and a second source/drain extension in the silicon layer under the second and third spacers, the first and second source/drain extensions separated by a channel region in the layer under the gate stack; a first source/drain in the silicon layer abutting the first source/drain extension and extending away from the channel region and a second source/drain in the silicon layer abutting the second source/drain extension and extending away from the channel region, a first distance between the first source/drain and the channel region measured through the first source/drain extension region less than a second distance between the second source/drain and the channel region measured through the second source/drain extension region.
A fifth aspect of the present invention is an apparatus, comprising: a chamber having a gas inlet and an exhaust port connected to a vacuum pump; a magnetic filter positioned between means for generating an electron/reactive gas ion plasma from a gas supplied through the gas inlet and means for holding a substrate at a pre-selected angle between 0° and 90° relative to a plane defined by the magnetic filter; and means for applying a bias voltage to the means for holding the substrate.
The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
SOI substrate.
In
In one example, substrate 100 is a single-crystal bulk silicon wafer or an SOI wafer (wafers are generally flat circular disks.) In one example, gate dielectric layer 115 comprises silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (Si:C), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), organosilicate glass (Si:COH), plasma-enhanced silicon nitride (PSiNx) or NBLok (Si:C(N,H)). In one example gate dielectric layer 115 is a high K (dielectric constant) material, examples of which include but are not limited to metal oxides such as Ta2O5, BaTiO3, HfO2, ZrO2, Al2O3, or metal silicates such as HfSixOy or HfSixOyNz or combinations of layers thereof. A high K dielectric material has a relative permittivity above about 10. In one example, gate dielectric layer 115 is about 0.5 nm to about 20 nm thick. In one example, gate electrode 120 comprises polysilicon, doped polysilicon, metal, metal silicide or combinations thereof. In one example, capping layer 125 comprises SiO2, Si3N4, Si:C, SiON, SiOC, Si:COH, PSiNx or Si:C(N,H). In one example, capping layer 125 is about 5 nm to about 200 nm thick. In one example, spacers 135A and 135B comprise SiO2 or Si3N4.
While gate dielectric layer 115 is illustrated in
It should be understood that the present invention is not limited to forming asymmetrical spacers on a gate stack, but can be applied to forming asymmetrical spacers on any mesa-like structure having a top surface and two opposing sidewalls.
where:
- m is the mass of the charged particle,
- ν ⊥ is the velocity component perpendicular to the direction of the magnetic field,
- q is the charge on the particle, and
- B is the constant magnetic field.
For a typical electron at less than 20 eV, its gyroradius under a 50 G applied magnetic field is approximately 0.5 cm. By setting S1 to less than 1 cm, all electrons with electron temperature less than 20 eV will be excluded from the region below magnetic filter cores 170 (seeFIG. 2A ), whereas less mobile ions (positive or negative) will not. This results in a flux of charged ions only through the magnetic filter region, and a consequent build-up of ion-ion plasma between the magnetic filter and the substrate. Since the formation of a sheath just above the surface of a substrate in a plasma environment requires a differential mobility between charged species in gaseous plasma (e.g. electrons and ions), there is no sheath formed above substrate 100 in the inventive method because electrons have been excluded from the region just above the substrate by magnetic filter cores 170 and a self-bias is generated in the direction normal to the wafer surface. Reactive neutral species are still present above the wafer. With appropriate chemistry selection etching will proceed preferentially on the spacer sidewall titled toward the incident ion flux.
In one example, trench isolation is formed prior to formation of gate stack 110. Trench isolation 185 extends from top surface 105 of substrate 100 into the substrate. Trench isolation 185 may be formed by etching a trench into substrate 100, depositing a dielectric layer over substrate 100 to completely fill the trenches and then performing a chemical-mechanical polish to coplanarize top surface 105 of substrate 100 and a top surface of trench isolation 185. In one example, trench isolation comprises high-density plasma (HDP) silicon oxide or chemical-vapor-deposition (CVD) tetraethoxysilane (TEOS) oxide. In one example, trench isolation 185 comprises a dielectric liner, such as SiO2 and a polysilicon core.
In
In
In
In
Because of the SiGe or Si:C source/drains, a channel region 200 between the first source/drain extensions 180A and the second source/drain extensions 180B under gate 120 is under compressive or tensile stress, so FET 205A is a strained FET. Further, because L1 is not equal to L2, FET is also an asymmetrical FET. First and second hetero-source/drains 195A and 195B may be doped in-situ during epitaxial growth (to form a self-aligned source/drains) or doped afterwards by ion implantation other suitable techniques such as plasma doping.
In
In
In
In
In order to fabricate a fourth MOSFET device according to the present invention, it is necessary to return to
Thus the present invention provides a method of fabricating asymmetrical spacers and asymmetrical MOSFETs without defining the asymmetrical elements with photolithographic steps.
The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims
1. An apparatus, comprising:
- a chamber having a gas inlet and an exhaust port connected to a vacuum pump;
- a magnetic filter positioned between means for generating an electron/reactive ion plasma from a gas supplied through said gas inlet and means for holding a surface of a substrate at a pre-selected angle between 0° and 90° relative to a plane defined by said magnetic filter; and
- means for applying a bias voltage to said means for holding said substrate.
2. The apparatus of claim 1, wherein said means for holding said substrate is a tiltable stage.
3. The apparatus of claim 1, wherein said means for holding said substrate is a stage fixed at said pre-selected angle.
4. The apparatus of claim 1, wherein said magnetic filter includes a row of magnetic cores spaced apart less than half a gyroradius of an electron at the magnetic field strength generated by said magnetic filter cores.
5. The apparatus of claim 1, wherein said means for generating an electron/reactive gas ion plasma is inductively coupled to a plasma power supply.
6. The apparatus of claim 1, wherein said means for generating an electron/reactive gas ion plasma is capacitively coupled to a plasma power supply.
7. The apparatus of claim 1, wherein said means for generating an electron/reactive gas generates a plasmas density of between about 1012 and 1013 ions per cm3.
8. The apparatus of claim 1, said magnetic filter has a field strength between about 5 G and about 500 G.
9. The apparatus of claim 1, wherein said magnetic filter has a field strength between about 5 G and about 500 G and includes cores spaced apart less than half a gyroradius of an electron at said field strength.
10. The apparatus of claim 1, wherein said magnetic filter is positioned between said means for holding a substrate and said high density plasma.
11. The apparatus of claim 1, wherein said magnetic filter includes a row of magnetic filter cores spaced apart a distance that is less than half a gyroradius of an electron at the magnetic field strength generated by said magnetic filter cores, said distance allowing a flux of charged ions to pass from said electron/reactive ion plasma through said magnetic filter to said substrate and not allowing electrons from said electron/reactive ion plasma to pass through said magnetic filter to said substrate.
12. The apparatus of claim 1, wherein said magnetic filter prevents formation of a sheath around a plasma generated between said magnetic filter and said substrate.
13. The apparatus of claim 1, wherein said magnetic filter allows formation of an ion-ion plasma between said magnetic filter and said substrate.
14. The apparatus of claim 1, wherein only reactive ions and neutral species strike said surface of said substrate.
15. The apparatus of claim 1, wherein said magnetic filter includes a row of magnetic cores spaced apart less than 1 cm.
16. The apparatus of claim 1, wherein said electron/reactive ion plasma is a non-equilibrium plasma.
17. The apparatus of claim 1, wherein said gas comprises CHxF4-x where x is 1, 2 or 3.
18. The apparatus of claim 1, wherein said substrate comprise a semiconductor material having a dielectric layer thereupon.
19. The apparatus of claim 1, wherein said substrate is a silicon-on-insulator substrate comprising a single-crystal silicon layer separated from a semiconductor substrate by a buried insulating layer.
20. The apparatus of claim 1, wherein said substrate is a circular disk of silicon having a dielectric layer thereupon.
Type: Application
Filed: Jun 3, 2014
Publication Date: Sep 18, 2014
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Kangguo Cheng (Beacon, NY), Xi Li (Somers, NY), Richard S. Wise (Newburgh, NY)
Application Number: 14/294,557
International Classification: H01L 21/67 (20060101);