BIPOLAR TRANSISTORS WITH CONTROL OF ELECTRIC FIELD

Abstract

The invention provides a bipolar transistor circuit and a method of controlling a bipolar transistor, in which the bipolar transistor has a gate terminal for controlling the electric field in a collector region of the transistor. The bias voltage applied to the gate terminal is controlled to achieve different transistor characteristics.

Description

This invention relates to bipolar transistors, and in particular bipolar transistor designs which make use of a control terminal (additional to the base, collector and emitter terminals), for controlling the electric field distribution within a portion of the device.

In the field of data communications, there is an on-going need for power amplifiers that are able to operate at high speed. Systems of this kind typically use power amplifiers at the transmitter side to enable them to transfer the data from the circuit to the open field by electro-magnetic radiation. These high-frequency power amplifiers are designed to work at high currents and/or high voltages in order to transmit sufficient power.

Although CMOS based technologies can be used to produce high output power amplifiers, bipolar technologies remain important for providing high-efficiency, high power amplifiers at (ultra-) high frequencies. There is often a trade-off in bipolar devices between high power performance, high frequency performance and cost.

For bipolar technologies, high currents can be obtained with large-area transistors, while the breakdown voltage of the device largely determines the maximum voltage swing during operation.

When the technical requirements for medium RF power amplifiers become more stringent in terms of output power, power gain and linearity, new designs of cost-effective bipolar or heterojunction bipolar transistors (HBT) are required to meet these criteria. The aim would be to enable Si or SiGe HBT's with characteristics comparable to expensive GaAs transistors.

It has been proposed to use control of the electric field distribution in a bipolar transistor to enhance the trade-off between breakdown voltage and other device characteristics, for example as disclosed in U.S. Pat. No. 6,777,780.

The structure described has a drift region, and one or more gate contacts, which enable to shape the electric field in the collector region proximal to the base region. This enables a uniform electric field to be shaped enables the range over which the field is constant to be varied. As such the setting point for the trade-off between various bipolar transistor characteristics can be set.

According to the invention, there is provided a transistor circuit, comprising:

a bipolar transistor comprising a base, collector and emitter, and one or more gate terminals for controlling the electric field in a collector region of the transistor;

a control circuit for controlling the bias voltage or voltages applied to the gate terminal or terminals, with different control voltages used for different transistor characteristics.

The ability to provide different transistor characteristics by setting a control voltage enables different identical transistors to have different Is characteristics. The control voltage can be static so that the circuit is configured in a certain way to achieve the desired performance.

A system can then have multiple identical transistors but with different static bias applied. Different bias settings can be used in a system comprising many transistors. Depending on the configuration, the requirement of breakdown voltages (BV) and speed (cut-off frequency fT) for these transistors might be different. By setting different gate biases for identical transistors, they can have different characteristics. For example, with two identical transistors, one can have BV1 and fT1 with control voltage VG1; and another have BV2 and fT2 with control voltage VG2.

An example of multiple transistors is a cascaded configuration where one transistor needs a high breakdown (but does not need an extremely high fT) while the other transistor needs a high speed (high fT) and not necessarily a high breakdown. In such configuration, the same transistors can be used but with different static biasing on the gate to make them operate in the regime as needed in the cascade circuit.

Alternatively, the control voltage can be dynamic. The gate terminal associated with the collector can be considered to be a field plate, and this can be used to further advance the power capability of such a device. By biasing the gate terminal dynamically, the power capability of the device can be extended by pushing the load line outwards so that both V_CE,MAX and I_C,MAX can be increased. The circuit can be tuned to a particular application by selecting the bias voltage.

The circuit can further comprise:

a feedback circuit for dynamically controlling a bias voltage applied to the gate terminal in dependence on a collector-emitter or base-emitter voltage of the bipolar transistor.

This enables the circuit to respond dynamically to the circuit conditions.

The feedback circuit preferably comprises a signal processing unit for generating a bias voltage which related to the collector-emitter voltage. In this way, by an appropriate field shaping, the high breakdown (for high voltage operation) or high current (for smaller collector emitter voltage) can be is achieved.

The feedback circuit can comprise an inverter connected between the collector and gate terminal.

The dynamic control is preferably at the frequency of operation of the bipolar transistor so that it can respond dynamically to the load conditions.

The circuit can be used in an RF power amplifier.

The invention also provides a method of controlling a bipolar transistor comprising a base, collector and emitter, and one or more gate terminals for controlling the electric field in a collector region of the transistor, wherein the method comprises:

controlling the bias voltage or bias voltages applied to the gate terminal or terminals to achieve different transistor characteristics.

Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

FIG. 1 shows the trade-off between breakdown voltage and frequency of different high-voltage SiGe heterojunction bipolar transistors (HBTs);

FIG. 2 shows an example of bipolar transistor structure to which the invention can be applied;

FIG. 3 shows how the accumulation layer under a collector field plate changes with various gate voltages at the ON state;

FIG. 4 shows the value of the collector-base breakdown voltage at various values of the field plate voltage;

FIG. 5 shows an adjustable relationship between frequency and breakdown voltage with varied field-plate voltages;

FIG. 6 shows how dynamic switching of the field-plate allows to use a different load line which is more in favour for better power operation; and

FIG. 7 shows an example of how to implement dynamic field plate voltage control in a power amplifier.

The invention provides a bipolar transistor circuit in which the bipolar transistor has one or more gate terminals for controlling the electric field in a collector region of the transistor. The bias voltage or voltages applied to the gate terminal or terminals are controlled to achieve different transistor characteristics.

In example the control is static, so that different identical transistors in a circuit can have different (fixed) characteristics. In another example, a feedback circuit dynamically controls a bias voltage applied to the gate terminal in dependence on a collector-emitter or base-emitter voltage of the bipolar transistor. This enables the transistor performance to be tuned in real time to the dynamically varying load requirements.

Bipolar (or heterojunction bipolar) transistors are currently used for RF power amplifiers at high frequencies thanks to their good RF characteristics. For such applications, a high-breakdown device is usually preferred allowing high voltage swing at the output (for high output power). However, high voltage devices usually have their limitations, which include:

(i) A low speed. There is always a trade-off between breakdown voltage and speed: a high-breakdown voltage device has a low f_T (the frequency at which the current gain is unity) and vice versa. FIG. 1 shows a general example of such a trade-off and shows different devices of different collector emitter breakdown voltage (BVceo).

(ii) Current limitations. As can be seen FIG. 1, there is a relation between speed (fT) and maximum current (i.e. current at peak fT). This current is shown as J_MAX, it means that the high-voltage device suffers also from a lower J_MAX, which makes the power capability of the device also lower.

In practice, different breakdown voltages and fT values for different application requirements are obtained by changing the process for the collector profile (i.e. implantation dose, implementation energy, diffusion time and io temperature). This complicates the process or increases its cost and limits the flexibility of the designer in implementing ICs.

As mentioned above, it has been proposed to use one or more gate biases to increase the flexibility and power capability for power bipolar devices.

This invention will be described in connection with a particular bipolar Is transistor design which will now be described. The invention is however not limited to the particular transistor shown.

FIG. 2 shows one example of bipolar transistor structure to which the invention can be applied. The method of the invention of using an extra terminal (for example to dynamically extend the power capability of the device) can be applied to any bipolar device as long as that device has a contact close to the collector drift region. The structure of FIG. 2 is one example.

The transistor has an emitter E, a base B and a collector C. The emitter E is formed in the bulk of the substrate of the device. The emitter E could also be formed as a layer above the surface of the substrate.

The base B is provided as a layer of semiconductor material over the emitter E. The layer forming the base B can be deposited and patterned using standard lithographic techniques, to provide the desired dimensions and alignment with respect to the emitter E. The collector C can also be provided as a patterned layer of semiconductor material, dimensioned and aligned with respect to the base as desired.

In the example structure of FIG. 2, the collector C extends laterally in a plane substantially parallel to the major surface of the substrate. The collector C overlaps the base B (thereby to make contact therewith), but also extends past an edge of the base B and away from the overlapping region. To prevent a short circuit of the base B a dielectric 10 is provided beneath the overhang portion of the collector C to ensure that this portion of the collector C does not make contact with the emitter E. The collector C is formed at the “top” of the device (i.e. above the emitter E and the base B). The emitter E, base B and collector C are each provided with corresponding emitter contact(s) 12, base contact(s) 14 and collector contact(s) 16 The collector C is provided with a collector gate 18. The purpose of the collector gate 18 is to shape the electric field within the collector C. The collector gate is thus a gate terminal of the device, in addition to the conventional base, emitter and collector terminals. It functions as a field plate. In this way, the peak electric field within the collector C can be suppressed, thereby improving still further the breakdown voltage of the device. This field shaping in this device thus makes use of a collector gate in a bottom-up bipolar transistor having a lateral collector.

Although a small gate is shown schematically in FIG. 2, in principle the gate can also be extended laterally over the entire collector region. This can give improved field shaping.

This invention relates to biasing of the gate, and it can be applied to different transistor designs, such as vertical transistors. It can be applied to any structure which implements a gate which enables field shaping in the drift region.

In high-power devices, it is known that a field plate can be used to reshape the field distribution. With a suitable bias, an accumulation layer can be formed under the field plate, which can be used for enhancing f_T and current.

In order to understand the behaviour of the accumulation layer under different field plate bias (V_G) for the field plated-collector of FIG. 2 a CAD model has been used.

The impact of field plate voltage has then been investigated at ON and OFF states:

In the ON state (for example: V_CE=1V, VBE=0.7V): when V_G increases from 1V to 10V, the accumulation layer under the field plate starts to increase and extend under the whole field plate (to a saturation level). FIG. 3 shows how the accumulation layer under the field plate (at X=−0.5 μm) changes with various gate voltages at the ON state. This accumulation layer can be considered as a thin collector (i.e., virtually moving the collector closer to the base), which helps delay the onset of the Kirk effect and increase f_T. In brief, high f_T and low BVceo are obtained at high V_G.

In the OFF state (V_CE=1V, VBE=low voltage for example 0V): when V_G increases from 1V to 10V, the breakdown BVcbo is reduced, which can be explained as follows. At a low V_G and high V_CE, the field is pushed away from the base-collector junction (or lines of equi-potential are pushed further to the end of collector), which is beneficial for a high breakdown. When V_G is increased, that effect is reduced (e.g. the collector is depleted slower) which makes the breakdown voltage lower. FIG. 4 shows the value of BVcbo at various values of the field plate voltage V_G. (V_G=1, 4, 7, 10 V).

The transistor has two main important figures of merit: breakdown voltages (BVcbo) and cut-off frequency (fT). While BVcbo is determined at the OFF-state condition, fT is determined at ON-state condition. In a method which dynamically changes breakdown voltages (BV) and fT, an analysis of the effect of bias at these ON and OFF states is relevant. The bias conditions mentioned above for ON and OFF states (e.g., VCE=1V, VBE=0.7V; VCE=1V, VBE=0V) are of course simply a typical example of biasing for a silicon-based bipolar transistor. Other bias conditions are possible.

There are various applications of this control of the accumulation layer.

A first application is to create a single design of device with various values of f_T and breakdown voltage. This can be considered to be a static implementation of the invention, in which different transistors in a multiple-transistor circuit are biased to provide different transistor characteristics.

By making use of the effect described above relating to the accumulation layer, one device can be made with an f_T and breakdown (BVceo and BVcbo), which can be adjusted by varying only the field-plate bias.

FIG. 5 shows an adjustable f_T/BVceo with varied field-plate voltages.

As shown in FIG. 5, by increasing V_G from 1V to 7V, BVceo is reduced from 9.5V to 5V; and then increases from 20 to 32 GHz.

This shows that depending on the gate biasing it is possible to trade-off fT with BV (most clearly, seen in FIG. 5b).

By adapting the gate voltage, the breakdown voltage and f_T and f_MAX can be adapted (with fT and f_MAX going up when BV is going down). As such, the same design of device can be used either as a lower-frequency-higher-voltage device or as a high-frequency-lower-voltage device.

In the static implementation, a DC bias is applied to the gate which can be a single gate or a gate which is by split into parts. One or more gates can be used for optimal field shaping. A gate part closer to the base-collector junction can be used to shape the field for control of the breakdown. Different gates can be provided with different static bias levels.

A designer can have more flexibility to apply a given transistor type to the desired application. If it is a wireless infrastructure application, the supply voltages can be as high as 5V or 9V, while frequency bands are 900 MHz, 2.1 GHz, 2.4 GHz, 3.5 GHz and 5.8 GHz.

In this way, separate technologies are no longer needed for different frequency bands—for example, one for frequencies below 2.7 GHz and another for frequencies above 2.7 GHz.

In summary, the technology using gated HBTs can cover:

(i) High gain at different frequency bands (wide band design) at a fixed breakdown.

(ii) High linearity over frequency and wide band (because of high f_T) by using negative feedback designs with high loop gain.

(iii) The field-plated HBT can be universal for different applications. Depending on application requirements, it can be used with high supply voltages to obtain high linearity, power levels or efficiency.

(iv) More design flexibility is provided, as the field-plated HBTs can be used with different V_G, which is dependent on the design topology.

This application provides static control of the bias voltage, in dependence on the intended use of the transistor. Different bias voltages can be used to create different transistor characteristics to suit the intended circuit application.

A second application is to enable selection of a particular load line for power amplifiers in a dynamic way.

The power capability (and also linearity) of power amplifiers is determined by the maximum voltage (e.g. BVceo or BVcbo) and maximum current.

FIG. 6 shows how the load line can be shifted by biasing the field-plate in real-time (at the same speed as collector).

The desired load line can be selected by the dynamic switching approach. With a better load line, better linearity can be obtained as well.

This means that in a first region (shown as Region I), where a high breakdown is needed, a small V_G is applied and a high BVceo (and also BVcbo) can be obtained. In a second region (shown as Region II), where a high current is needed, a large V_G is applied (breakdown is not important here).

FIG. 6 shows two load lines 30,32. The original load line is shown as 30 and the improved load line under dynamic switching is shown as 32.

The biasing does not change the load line, instead the load line is a choice made by the designer.

Starting with a given transistor, the designer chooses a load which fits the requirements and generates enough power and linearity. This means that the loadline is fixed and determined by the load impedance, e.g. loadline 30. However, to have improved performance (e.g. more power) the designer would like to use a different load impedance to end up with the loadline 32, but the loadline 32 crosses the breakdown voltage limit (VCE,MAX on x axis) and the maximum current (JMAX on y axis).

The dynamic control of the invention enables the designer not to be contrained by the maximum voltage and maximum current, so that a load impedance can be used that gives loadline 32, even if the breakdown voltage or maximum current of the transistor is lower than the corresponding VCE,MAX and MAX. The transistor can be tuned to allow more current or voltage if the transistor is kept in the correct position on the loadline.

In a standard transistor, the designer can only use load line 30 because of the maximum VCE,max and Jmax values.

The dynamic biasing approach enables the designer to use load line 32 because with the circuit operated with the correct dynamic biasing, both VCE,max and Jmax will shift, and the transistor will adapt its point of operation in real time to remain at a suitable point on the selected loadline.

The power and linearity performance of power amplifiers is limited by Jmax and VCE,max (of the transistor). The invention enables both Jmax and VCE,max to be increased. The power and linearity performance of the power amplifier by enabling the user of load line 32 will be better than when there is only the choice of load line 30

This way of biasing the field plate means the power capability of the device can be extended by pushing the load line further to the right hand side, i.e. both V_CE,MAX and I_C,MAX can be increased. This enhancement is a large advantage to the current status of power (high-voltage) devices, where I_C,MAX is often traded off versus V_CE,MAX

This approach can be applied in mobile phone power amplifiers. Since these amplifiers are adaptively biased to get more effective current consumption and high power efficiency, V_G can be regulated so that whenever the power amplifier transistor experiences a high V_out (peak-to-peak), the high output voltage can be detected and V_G can be reduced in order to increase the breakdown voltage.

Power amplifiers tend to work sometimes with a mismatch at the output, i.e. the real or imaginary parts of the load can vary. Thus the output voltage swings can increase substantially and some part of the power is reflected back to the power amplifier. Only a certain part of the power is still transmitted to the load. In this case a fast detection could set up a low V_G, extend the breakdown and the transmission would be supported without any breakdown. In a power amplifier, a very high BV_CBO is needed, for example 3 times larger than the operating voltage, to withstand very high output voltages in some unexpected cases of mismatch. However, using a high breakdown voltage transistor just these cases, there is a consequent sacrifice of other features (e.g. high fT or Jmax). The dynamic switching method can be used with detection of the mismatch case, and immediately the gate voltage can be lowered. In this way, a higher By can be tolerated, whereas in normal situations, we can a higher VG is used.

An example of implementing dynamic switching operation in a power amplifier is shown schematically in FIG. 7.

FIG. 7 shows the power transistor 40 with the field plate gate G. There are thus four device terminals: base (B), emitter (E), collector (C) and gate (G). A substrate contact is also possible, but not essential. The (complex) load 42 is connected to the collector via a DC blocking capacitor 44. The transistor base is DC biased by a bias circuit 47 and the RF input is supplied through a decoupling capacitor 48.

A choke inductor 49 is connected between the power supply line and the transistor 40. The choke 49 is used for decoupling DC and AC signals.

This is just one way of operating a power transistor, many other configurations are possible and the dynamic switching of the invention can again be applied.

The gate biasing is implemented by a high-speed inverter 46 which probes the collector-emitter voltage of the power transistor in real-time and sends this inverted signal to the gate of transistor 40. In this way, the gate biasing is low in the case of a high V_CE (region I in FIG. 6) while it is high for low V_CE (region II in FIG. 6). The base-collector voltage can also be used as the feedback parameter.

There are other ways of sensing a voltage on the transistor and feeding it to the gate. For example, the base current can be probed or the voltage swing. Since there is a relation between base and collector current and voltages, probing the base could also be used to bias the gate.

Sensing the output signal in a real-time mode for power amplifiers at high frequencies (GHz range) has been demonstrated for example in Young-Sang Jean et al., “High-Efficiency Power Amplifier Using Novel Dynamic Bias Switching”, IEEE Transactions of Microwave Theory and Techniques, vol. 55. No. 4, April 2007 for class-E type operation.

Other power amplifiers configurations are possible as well but have a similar way of dynamic gate-biasing as shown schematically in FIG. 7.

For example, as mentioned above, the gate can be physically split in one or more sections (i.e. more gates next to each other on the same collector region) with every section individually biased depending on the application requirements or device operation.

The invention in this second application thus provides an approach for dynamically biasing the field plate of bipolar devices to enable a dynamic change (i.e. adjustability) of device characteristics and their trade-off such as breakdown voltage (BVcbo/BVceo) vs. frequency (f_T/f_MAX). This extends the power capability and linearity of the device by varying V_G in real time, for example at the same speed as the collector-emitter voltage swing.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A transistor circuit, comprising:

a bipolar transistor comprising a base, collector and emitter, and at least one gate terminal for controlling the electric field in a collector region of the transistor;

a control circuit for controlling a bias voltage or bias voltages applied to the gate terminal or gate terminals, with different control voltages used for different transistor characteristics.

2. A circuit comprising:

at least first and second first transistor circuits as claimed in claim 1, wherein the transistors of the first and second first transistor circuits are identical and have different bias voltages applied to them to achieve different transistor characteristics.

3. A circuit as claimed in claim 1, further comprising:

a feedback circuit for dynamically controlling a bias voltage applied to the gate terminal in dependence on a collector emitter or base-emitter voltage of the bipolar transistor.

4. A circuit as claimed in claim 3, wherein the feedback circuit comprises an inverter connected between the collector and gate terminal.

5. A circuit as claimed in claim 2, wherein the dynamic control is at the frequency of operation of the bipolar transistor.

6. An RF power amplifier comprising a circuit as claimed in claim 1.

7. A method of controlling a bipolar transistor comprising a base, collector and emitter, and at least one gate terminal for controlling the electric field in a collector region of the transistor, wherein the method comprises:

controlling a bias voltage or bias voltages applied to the gate terminal or terminals to achieve different transistor characteristics.

8. A method as claimed in claim 7, comprising controlling first and second first transistor circuits, wherein the transistors of the first and second first transistor circuits are identical, and the method comprises applying different bias voltages to the transistor of the first and second first transistor circuits to achieve different transistor characteristics.

9. A method as claimed in claim 7, further comprising dynamically controlling a bias voltage applied to the gate terminal in dependence on a collector emitter voltage of the bipolar transistor.

10. A method as claimed in claim 9, comprising generating a bias voltage from an inverted version of the collector voltage.

11. A method as claimed in claim 9, wherein the dynamic control is at the frequency of operation of the bipolar transistor.