Digital Phase Locked Loop with Hybrid Delta-Sigma Phase/Frequency Detector
A PLL includes independent frequency-locking and phase-locking operational modes. In addition, the PLL includes a hybrid (e.g., mixed-analog/digital signal) 2nd-order delta-sigma (DS) phase/frequency detector. The detector may be implemented based on a continuous-time 1st-order DS Analog to Digital (ADC) converter. The ADC may be enhanced to 2nd-order by using, e.g., closed loop frequency detection. The PLL includes a fine resolution encoder for encoding the DS ADC output. The fine resolution encoding facilitates true multi-bit phase/frequency error digitization with drastically reduced DS quantization noise.
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This application claims the benefit of priority to U.S. Provisional Application No. 61/828,108, filed 28 May 2013 and to U.S. Provisional Application No. 61/856,278, filed 19 Jul. 2013.
TECHNICAL FIELDThis disclosure relates to phase locked loops (PLLs).
BACKGROUNDRapid advances in electronics and communication technologies, driven by immense customer demand, have resulted in the widespread adoption of an extensive variety of electronic devices. These devices often rely for proper operation on sophisticated frequency synthesizers, clock recovery circuits, jitter and noise reduction circuits and other types of circuits that are sometimes implemented with phase locked loops (PLLs). Improvements in PLLs will further enhance the performance of electronic devices.
The PLL 100 and its component parts may be implemented in other ways and may vary in performance characteristics from implementation to implementation. For example,
The PLL 100 includes a fine resolution (FineRes) encoder 106 for encoding the DS ADC output. The fine resolution encoding facilitates true multi-bit phase/frequency error digitization with drastically reduced DS quantization noise. A phase/frequency detector (PFD) charge pump (CP) 108 drives the ADC 104, and a multi-modulus divider (MMD) 110 is present in the feedback path from the digital loop filter.
The PLL 100 also includes coarse and fine resolution detection modes that facilitate fast acquisition and spur-free tracking operation. A fully digital loop filter 112 may be implemented in the PLL 100 and may control the digitally control oscillator (DCO) 114. Note that the PLL 100 has a bandwidth determined by the loop filter coefficients independent of the DS phase/frequency detector parameters (e.g., CP current Icp and the 1st-order DS ADC integrating capacitor Cint).
The PLL 100 operates on the differential phase/frequency error of its output clock signal Fout with respect to the input reference clock signal 122, Fref. The output frequency of the PLL output clock 124, Fout, reflects the targeted channel frequency upon phase/frequency lock. The detector 102 provides a digital estimate of the PLL output frequency the PLL 100 may compare to a digital word (e.g., a channel indicator 116) that specifies the targeted channel frequency for the PLL 100 to produce. The digital frequency error information (Dfe) 118 is accumulated (e.g., integrated) to provide the digital phase error information (Dphie) 120. The PLL 100 controls the phase/frequency of the DCO 114 responsive to the digital phase error information, e.g., to try to eliminate the error. A phase lock enable signal 126 may be provided to selectively enable or disable the operation of the accumulation and filter operations of the PLL 100.
Note that the loop filter configuration is independent of the fine resolution encoder 106. Without the fine resolution encoder 106, the loop filter may instead be characterized by a low bandwidth and high rejection (that may result in less stable output) so that distortion due to the coarse resolution quantization is adequately filtered. The fine resolution encoder 106 thus allows for more flexible PLL dynamic control.
The flash ADC 204 and current-mode DAC 206 of the ADC 104 is digitally reconfigurable to support single-bit or multi-bit resolution via dynamic control of the number of active quantization levels, allowing for fast frequency acquisition and spur-free tracking operation. In that regard, the PLL 100 may include a resolution control input 208 that specifies, e.g., the number of quantization levels that the ADC 104 will generate. As a specific example, the resolution control input 208 may be provided to both the flash ADC 204 and the current-mode DAC 206 to configure them for the number of quantization levels desired. A controller may use the resolution control input 208 to place the PLL 100 into single-bit or three level quantization mode for coarse resolution operation of the PLL 100, while the controller may cause multi-bit quantization for fine resolution operation of the PLL 100. The controller may switch to fine resolution operation on an application specific basis, and as one example the switch to fine resolution may depend upon the time for the frequency error to settle to within a predefined margin. To the extent that there are mismatches in the flash ADC 204 and current-mode DAC 206 characteristics, those mismatches may be randomized via the closed-loop noise shaping functionality of the detector 200, thereby alleviating any need for dynamic element matching (DEM). However, as noted below with respect to
Nint+{ . . . ,−1,0,1, . . . }
and thereby achieves a long-term average fractional N value, where:
N=Nint+Nfrac=FLO/Fref and Nfracε[0,1) or [−½,½).
The mean value of the detector output Bout 302 is preferably Nfrac in order to minimize the frequency error between Fref and Fmmd=FLO/(Nint+Nfrac). The fractional division control results in Nfrac cycle-to-cycle period variations of Fmmd, which entail a Nfrac LO cycles normalized differential frequency Delta fin input 304 to the DS detector.
Delta fin (Nfrac) 304 and the induced 1st-order DS ADC quantization noise Qn 306 are transferred to the detector output 302 as:
Bout=Nfrac+(1−z1)2Qn
Note that the induced quantization noise undergoes 2nd-order noise shaping.
In
Fine resolution encoding may generally refer to a quantization step D less than 1. The PLL 100 uses quantization steps less than one (D<1) together with the fine resolution encoder 106 to interface the fractional valued DS ADC output with the MMD 110. The quantization step may be set according to a targeted PLL performance. Accordingly, even low-level fractional quantization may be sufficient for a target performance level, and finer grained fractional quantization may be implemented to reach higher target performance levels.
Various implementations of the PLL 100 have been specifically described. However, many other implementations are also possible.
Claims
1. A phase locked loop (PLL) comprising:
- a reference frequency input;
- a detector in communication with the reference frequency input, the detector comprising a fine resolution encoder configured to output a multiple bit resolution phase/frequency error encoding;
- a loop filter following the detector and configured to accept the multiple bit resolution error encoding; and
- a reference frequency output following the loop filter.
2. The PLL of claim 1, where the detector comprises a phase and frequency detector including an analog to digital converter (ADC).
3. The PLL of claim 2, where the ADC is configured to selectively operate in:
- a fine resolution mode providing a fine mode number of quantization levels; and
- a coarse resolution mode providing fewer quantization levels than the fine mode number of quantization levels.
4. The PLL of claim 3, where the coarse resolution mode provides at least two quantization levels.
5. The PLL of claim 3, where the fine resolution mode provides at least eight quantization levels.
6. The PLL of claim 2, where the ADC comprises a delta-sigma ADC.
7. The PLL of claim 6, where the detector further comprises a charge pump configured to drive the delta-sigma ADC.
8. The PLL of claim 1, further comprising a digitally controller oscillator (DCO) driven by the loop filter, the DCO configured to generate a target output frequency signal on the target frequency output.
9. The PLL of claim 8, further comprising:
- a feedback path from the DCO to the detector, the feedback path configured to provide the target frequency output to the detector.
10. The PLL of claim 9, where the feedback path comprises a multi-modulus divider (MMD) configured to receive the target frequency output.
11. The PLL of claim 10, further comprising a dither circuit configured to interface the fine resolution encoder to the MMD.
12. The PLL of claim 11, where the multi-modulus divider comprises a divider output that provides feedback to a phase and frequency detector (PFD) charge pump.
13. The PLL of claim 12, where the PFD charge pump drives a delta-sigma ADC in communication with the fine resolution encoder.
14. A method comprising:
- performing phase/frequency detection with respect to a reference frequency and a feedback signal;
- generating, with a fine resolution encoder, a multiple bit error encoding of phase/frequency error responsive to the detection;
- receiving the multiple bit error encoding at a loop filter; and
- controlling a digitally controller oscillator (DCO) with the loop filter to generate a reference frequency output.
15. The method of claim 14, further comprising:
- generating the feedback signal by applying a multimodulus divider (MMD) to the reference frequency output.
16. The method of claim 15, further comprising:
- dithering the multiple bit error encoding to interface the fine resolution encoder to the MMD.
17. The method of claim 14, further comprising configuring an analog to digital converter (ADC) to act in a fine resolution mode to provide the fine resolution encoder that generates the multiple bit error encoding.
18. The method of claim 17, further comprising configuring the ADC to act in a coarse resolution mode for acquisition of frequency lock.
19. A phase locked loop (PLL) comprising:
- a reference frequency input;
- a phase and frequency detector charge pump in communication with the reference frequency input;
- a delta signal analog to digital converter (ADC) driven by the charge pump, the ADC comprising a resolution mode input configured to selectively change the ADC between: a fine resolution mode providing a fine mode number of quantization levels for phase and frequency error; and a coarse resolution mode providing fewer quantization levels for the phase and frequency error than the fine mode number of quantization levels;
- a loop filter following the ADC and configured to accept the phase and frequency error and responsively drive a digitally controlled oscillator (DCO) that generates a reference frequency output; and
- a feedback path from the DCO to the charge pump, the feedback path comprising a multimodulus divider (MMD).
20. The PLL of claim 19, further comprising a dither circuit configured to interface the fine mode number of quantization levels to a lower-resolution MMD control grid of the MMD.
Type: Application
Filed: Aug 14, 2013
Publication Date: Dec 4, 2014
Applicant: Broadcom Corporation (Irvine, CA)
Inventors: Ioannis Loukas Syllaios (Costa Mesa, CA), Henrik Tholstrup Jensen (Long Beach, CA)
Application Number: 13/966,515