Method of forming and structure of a non-volatile memory cell
A structure of a memory cell includes a substrate, a well, three source/drain doped regions, two bottom dielectric layers, two charge trapping layers, a blocking layer and two gates to form a storage transistor and a select transistor of the memory cell. A bottom dielectric layer and a charge trapping layer may be used to provide the dielectric of the gate of the select transistor with enough thickness but without any additional fabrication process.
This non-provisional application claims priority of U.S. provisional application U.S. 61/883,205 filed on Sep. 27, 2013.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a non-volatile memory cell, and more specifically, to a non-volatile memory cell having two transistors and a method of fabricating the non-volatile memory cell.
2. Description of the Prior Art
Non-volatile memory can store data in the absence of a power supply; therefore it is preferred to be used by various portable electronic products such as personal digital assistants (PDAs), mobile phones, and memory cards. In order to respond to the requirements of the market, non-volatile memory technology must have compatibility with CMOS processing, low power consumption, high writing efficiency, low cost, and high density. However, as non-volatile memory becomes smaller in size, the gate oxide layer becomes accordingly thinner making stored data dissipate easily and causes a problem in the data storing ability of non-volatile memory.
However, the conventional memory cell 10 has disadvantages. First, the conventional memory cell 10 comprises the PMOS transistor 30 and the NMOS transistor 28 which occupy a large amount of chip area since there is a minimum spacing rule between different types of transistors set by the fabrication technology used. Second, the conventional memory cell 10 requires the floating gate metal line 36 for connecting the first floating gate 32 and the second floating gate 34. Third, the field oxide layer 24 is required to separate the PMOS transistor 30 from the NMOS transistor 28. Therefore, the conventional memory cell 10 occupies considerable chip area and is structurally complicated. All of which increase the cost and difficulties in the manufacturing process.
SUMMARY OF THE INVENTIONA non-volatile memory cell comprises a well formed on a substrate, a plurality of source/drain doped regions formed on the well, a first bottom dielectric layer formed between a first source/drain doped region and a second source/drain doped region of the plurality of source/drain doped regions on the well, a second bottom dielectric layer formed between the second source/drain doped region and a third source/drain doped region of the plurality of source/drain doped regions on the well, a first charge trapping layer formed on the first bottom dielectric layer, a second charge trapping layer formed on the second bottom dielectric layer, a blocking layer formed on the first charge trapping layer, a memory gate formed on the blocking layer, and a select gate formed on the second charge trapping layer.
A method of forming a non-volatile memory cell comprises defining an active region which comprises a select transistor region and a storage transistor region, forming a well on a substrate, forming a stacked layer comprising a bottom dielectric layer, a charge trapping layer and a top dielectric layer, etching the top dielectric layer in the select transistor region, forming a select gate on the select transistor region and a memory gate on the storage transistor region, and forming a plurality of source/drain doped regions.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In addition, the non-volatile memory cell 200 may further comprise of at least four lightly doped regions 241, 242, 243, and 244. Each of the at least four lightly doped regions 241, 242, 243, and 244 may be a P-doped region and formed on the well 220. The first lightly doped region 241 may be in contact with the first source/drain doped region 231 and formed between the first source/drain doped region 231 and the first bottom dielectric layer 251. The second lightly doped region 242 may be in contact with the second source/drain doped region 232 and formed between the second source/drain doped region 232 and the first bottom dielectric layer 251. The third lightly doped region 243 may be in contact with the second source/drain doped region 232 and formed between the second source/drain doped region 232 and the second bottom dielectric layer 252. The fourth lightly doped region 244 may be in contact with the third source/drain doped region 233 and formed between the third source/drain doped region 233 and the second bottom dielectric layer 252.
To protect the at least four lightly doped regions 241, 242, 243, and 244 from being overlapped by forming of three source/drain doped regions 231, 232, and 233, at least four spacers 291, 292, 293, and 294 are formed. Each spacer shall be formed above a lightly doped region.
The first source/drain doped region 231, the second source/drain doped region 232, the first bottom dielectric layer 251, the first charge trapping layer 261, the blocking layer 271 and the memory gate 281 may form a storage transistor 201 of the non-volatile memory cell 200. The second source/drain doped region 232, the third source/drain doped region 233, the second bottom dielectric layer 252, the second charge trapping layer 262, and the select gate 282 may form a select transistor 202 of the non-volatile memory cell 200. The storage transistor 201 may be formed in a storage transistor region 101 of the substrate 210 and the select transistor 202 may be formed in a select transistor region 102 of the substrate 210. The channel length of the storage transistor 201 may be greater than or equal to the base length of the fabrication technology. The channel length of the select transistor 202 may be greater than or equal to the channel length of the storage transistor 201. A select line and a bit line may be used to provide voltages needed during operations of the non-volatile memory cell 200. The second source/drain doped region 232 is a floating region and is used to electrically connect the storage transistor 201 and the select transistor 202.
To perform write operation on the non-volatile memory cell 200, electrons are injected into the first charge trapping layer 261 through hot-electron injection mechanism induced by channel-hot-hole. Before writing data onto the non-volatile memory cell 200, the select transistor 202 is turned on to have a conducting channel between the third source/drain doped region 233 and the second source/drain doped region 232. The conducting channel between the third source/drain doped region 233 and the second source/drain doped region 232 would allow the third source/drain doped region 233 and the second source/drain doped region 232 to have the same voltage level. Holes in the channel between the second source/drain doped region 232 and the first source/drain doped region 231 are accelerated to obtain high energy. As a result of high energy impacting the well 220, electron hole pairs are generated. The electrons generated are attracted by a voltage applied to the memory gate 281 and the electrons are then injected into the first charge trapping layer 261 of the storage transistor 201.
To perform an erase operation on the non-volatile memory cell 200, electrons injected into the first charge trapping layer 261 may be ejected through Fowler Nordheim tunneling. Fowler Nordheim tunneling may also be performed by the memory cell when performing read operation. And controlling the voltage on the select line and the bit line allows the program inhibit operation to be performed.
In another embodiment of the present invention, a memory cell may further comprise a deep well.
In addition, the non-volatile memory cell 300 may further comprise of the at least four lightly doped regions 241, 242, 243, and 244. Each of the at least four lightly doped regions 241, 242, 243, and 244 may be a P-doped region and formed on the well 220. The first lightly doped region 241 may be in contact with the first source/drain doped region 231 and formed between the first source/drain doped region 231 and the first bottom dielectric layer 251. The second lightly doped region 242 may be in contact with the second source/drain doped region 232 and formed between the second source/drain doped region 232 and the first bottom dielectric layer 251. The third lightly doped region 243 may be in contact with the second source/drain doped region 232 and formed between the second source/drain doped region 232 and the second bottom dielectric layer 252. The fourth lightly doped region 244 may be in contact with the third source/drain doped region 233 and formed between the third source/drain doped region 233 and the second bottom dielectric layer 252.
The storage transistor 201 and the select transistor 202 of the non-volatile memory cell 300 comprise of similar components as that in the non-volatile memory cell 200. The difference of the non-volatile memory cell 300 and the non-volatile memory cell 200 is that the non-volatile memory cell 300 has a deep well 310 formed on the substrate 210 while the other does not. The function and operation of the two non-volatile memory cells 200 and 300 are the same. Therefore, the operation of the non-volatile memory cell 300 is not discussed further for brevity.
Step 401: Form isolations STI on the substrate 210;
Step 402: Form the well 220 on the substrate 210;
Step 403: Grow/deposit a bottom dielectric layer 250, a charge trapping layer 260, and a top dielectric layer 270 on the substrate 210;
Step 404: Etch the bottom dielectric layer 250, the charge trapping layer 260, and the top dielectric layer 270 from areas out of the areas of the non-volatile memory cell 200;
Step 405: Etch the top dielectric layer 270 formed in the select transistor region 102;
Step 406: Deposit a layer of gate compound 280 on the substrate 210;
Step 407: Form the memory gate 281 and the select gate 282;
Step 408: Etch the bottom dielectric layer 250, the charge trapping layer 260, and the top dielectric layer 270 from areas out of the areas of the memory gate 281 and the select gate 282;
Step 409: Form the at least four lightly doped regions 241, 242, 243, and 244; and
Step 410: Form source/drain doped regions 231, 232, and 233 of the non-volatile memory cell 200.
In step 401, isolations STI are formed on the substrate 210 to define the active region where the non-volatile memory cell 200 is to be formed.
Note that the etching of the gate dielectric layer of input/output (I/O) devices may be performed separately or at the same time as the etching in step 405. The gate dielectric layer of input/output (I/O) devices and the gate dielectric layer of logic devices may be formed separately for reasons that the thickness of the gate dielectric layer of input/output (I/O) devices may be thicker than the gate dielectric layer of logic devices.
In step 408, the reverse Oxide-Nitride-Oxide (ONO) etching process may be performed. After the etching process of the layer of gate compound 280 is finished, a first stacked layer which comprises the blocking layer 271 and the first charge trapping layer 261 and the first bottom dielectric layer 251 is formed. Moreover, a second stacked layer which comprises the second charge trapping layer 262 and the second bottom dielectric layer 252 is also formed. The first stacked layer and the second stacked layer may be defined by etching areas of the bottom dielectric layer 250, the charge trapping layer 260, and the top dielectric layer 270 outside the area of the select gate 282 and the area of the memory gate 281.
Two masks may be adopted for the gate compound etching process and the reverse ONO etching process. Moreover, to perform the etching process, a layer of photoresist may be deposited over the entire surface of a top layer of layers of compounds to be etched. For example, to form a poly silicon gate, a layer of oxide and a layer of poly silicon compound are formed on the entire surface of the substrate. The top layer for instance may be the layer of poly silicon gate compound. The layer of photoresist is formed above the layer of poly silicon gate compound to be etched. The photoresist may be developed using a mask that specifies the selected areas of the layer of poly silicon gate compound to be etched. The photoresist is etched, removing photoresist above the selected areas of the layer of poly silicon gate compound to be etched. The process is then followed by the removal of parts of the layer of oxide and the layer of poly silicon compound from the selected areas, leaving remaining parts of the layer of oxide and the layer of poly silicon compound protected by the remaining photoresist to form the gate components of the non-volatile memory cell 200 intact. The photoresist acts as a protection layer to the layers of compounds that need not be etched during the etching process. The remaining photoresist may be removed after an etching process. The etching process may be used for forming components that are above the surface of the substrate 210.
The non-volatile memory cell 200 may further comprise of the at least four lightly doped regions 241, 242, 243, and 244. In step 409, the at least four lightly doped regions 241, 242, 243, and 244 may be formed by implanting ions to the selected areas of the well 220. The at least four lightly doped regions 241, 242, 243, and 244 may be formed before forming the source/drain doped regions 231, 232, and 233.
After step 409, the lightly doped regions of the input/output (I/O) devices and the logic devices may be formed by implanting ions to the selected areas of the substrate 210. The lightly doped regions of the input/output (I/O) devices and the logic devices are formed separate from the lightly doped regions of the non-volatile memory cells 200 since the lightly doped regions of the input/output (I/O) devices and the logic devices and the lightly doped regions of the non-volatile memory cells 200 may require different concentrations of the implanted ions that are defined according to the specific need of the devices.
A protection layer, such as the spacers 291, 292, 293, and 294, may be placed above the at least four lightly doped regions 241, 242, 243, and 244 to protect the at least four lightly doped regions 241, 242, 243, and 244 from being overlapped by other implanted components such as the three source/drain doped regions 231, 232, and 233. The present invention is not limited to the use of protection layers to prevent lightly doped regions from being overlapped by source/drain doped region.
In step 410, selected areas of the well 220 are implanted with ions to form the three source/drain doped regions 231, 232, and 233. The structure of the non-volatile memory cell 200 is illustrated in
Note that the non-volatile memory cell 300 in
The present invention discloses a non-volatile memory cell comprising of two transistors, a storage transistor and a select transistor, coupled in series. The charge trapping layer of the storage transistor may store electrons according to the data stored on the non-volatile memory cell. The select transistor may be used to select the non-volatile memory cell to be used during an operation. The use of lightly doped regions reduces the short channel effect on the non-volatile memory cell. A second charge trapping layer and a second bottom dielectric layer may serve as a dielectric of the gate of the select transistor. As compared to prior art, the method of fabrication of the present invention is more efficient since there is no need for additional etching step to reduce the thickness of the dielectric, which is the same dielectric as that of IO devices, of the gate of the select transistor. The non-volatile memory cell of the present invention may perform write operation, erase operation, read operation, and program inhibit operation. In some embodiments of the present invention, a deep well may be added to prevent damage to the non-volatile memory cell when operating under high supply voltage.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A non-volatile memory cell comprising:
- a well formed on a substrate;
- a plurality of source/drain doped regions formed on the well;
- a first bottom dielectric layer formed between a first source/drain doped region and a second source/drain doped region of the plurality of source/drain doped regions on the well;
- a second bottom dielectric layer formed between the second source/drain doped region and a third source/drain doped region of the plurality of source/drain doped regions on the well;
- a first charge trapping layer formed on the first bottom dielectric layer;
- a second charge trapping layer formed on the second bottom dielectric layer;
- a blocking layer formed on the first charge trapping layer;
- a memory gate formed on the blocking layer; and
- a select gate formed on the second charge trapping layer.
2. The non-volatile memory cell in claim 1, further comprising:
- a plurality of isolations formed on the substrate to define an active region.
3. The non-volatile memory cell in claim 1, further comprising:
- a plurality of lightly doped regions formed on the well and each formed between a corresponding bottom dielectric layer and a corresponding source/drain doped region.
4. The non-volatile memory cell in claim 1, further comprising:
- a deep well formed between the substrate and the well.
5. The non-volatile memory cell in claim 4, wherein the deep well is a deep N-well.
6. The non-volatile memory cell in claim 1, further comprising:
- a barrier layer formed between the substrate and the well.
7. The non-volatile memory cell in claim 6, wherein the barrier layer is an N-barrier layer.
8. The non-volatile memory cell in claim 1, wherein a length of the select gate is greater than or equal to a length of the memory gate.
9. The non-volatile memory cell in claim 1, wherein the first charge trapping layer and the second charge trapping layer are composed of silicon nitride.
10. The non-volatile memory cell in claim 1, wherein the first charge trapping layer and the second charge trapping layer are composed of silicon oxynitride.
11. The non-volatile memory cell in claim 1, wherein the substrate is a P-substrate, the well is an N-well, and the plurality of source/drain doped regions are P+ doped regions.
12-24. (canceled)
Type: Application
Filed: Jul 8, 2014
Publication Date: Apr 2, 2015
Inventors: Wein-Town Sun (Taoyuan County), Cheng-Yen Shen (Taoyuan County)
Application Number: 14/325,383
International Classification: H01L 27/115 (20060101); H01L 29/423 (20060101); H01L 29/06 (20060101);