OVERLOAD PROTECTION OF A TRANSFORMER LOADED LINE DRIVER

Abstract

A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of pending U.S. patent application Ser. No. 13/087,027, filed Apr. 14, 2011, which is a divisional of U.S. application Ser. No. 12/012,725, filed Feb. 1, 2008, now abandoned, which claims priority to provisional application No. 60/900,180, filed Feb. 7, 2007. These prior applications are incorporated herein by reference, in their entirety, for any purpose.

FIELD OF THE INVENTION

The invention relates generally to electronic communication systems. More particularly, the invention relates to a training pattern to enable recognition of proper wire-pair orientation and correction in electronic communication systems.

BACKGROUND

In Ethernet 10GBase-T cabling, the data is sent over four pairs of wires. Between the transmitter and receiver, the pairs can be swapped with each other, and the wires in a pair can be swapped. These reconfigurations can result in an inverted signal or the latency of the four pairs can differ. 10GBASE-T, or IEEE 802.3an-2006, is a standard to provide 10 gigabit/second connections over conventional unshielded or shielded twisted pair cables, over distances up to 100 m. This standard mandates specific training patterns to enable recognition of the proper correction, but does not provide a means to find the proper corrections from all the possibilities. Accordingly, there is a need to develop an algorithm to efficiently search the possible corrections and identify the correct one.

SUMMARY OF THE INVENTION

The current invention is a method of recognizing inverted signals and latency difference in wire pairs between a transmitter and receiver in 10GBase-T Ethernet cabling due to wire pair mismatch, and correcting the inversion and latency by swapping the cable orders. The method includes providing four pairs of wires, wherein the wires transmit data between the transmitter and the receiver. The wire pairs include pairs A, B, C, and D, whereas the pairs are arranged in a quadrille pattern having two top pairs and two bottom pairs. The method includes providing a pair swapping state machine, where the swapping state machine selects one pair from the top pairs, whereas the selected pair is designated as pair A. A polarity swapping and scrambler lock state machine is provided, where the lock state machine determines if the designated pair A is a correct choice for position A. The lock state machine then determines if the selected pair is inverted. If the selection for A is not correct a next pair of the wires is designated as pair A and the determination is repeated until the requirements for pair A are met and the pair is not inverted. A slave tap state machine is provided, where the tap state machine establishes a rule for a correct B, C, and D pattern based on the determined pair A. The lock state machine is used to designate a second top pair as pair B. The lock state machine is further used to designate a first bottom pair as pair C and to designate a first bottom pair as pair D. A deskew state machine is provided, where the deskew state machine compares all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, the cable swap state machine reverses the designated pair C with designated pair D. The deskew state machine is used to re-compare all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

DETAILED DESCRIPTION

Details of various embodiments of the present invention are disclosed in the following appendices:

Appendix A.

Appendix B.

Appendix C.

As one of ordinary skill in the art will appreciate, various changes, substitutions, and alterations could be made or otherwise implemented without departing from the principles of the present invention. Accordingly, the examples and drawings disclosed herein including the appendix are for purposes of illustrating the preferred embodiments of the present invention and are not to be construed as limiting the invention.

Claims

1. A line driver circuit comprising:

an output transistor on an integrated circuit chip, wherein the output transistor is configured to provide an output signal to a transformer coupled to a load; and

an overload detector circuit on the integrated circuit chip, wherein the overload detector circuit is configured to: receive the output signal; compare the output signal to a threshold value range; and responsive to the output signal having a value that is outside the threshold value range, providing a control signal to the transistor to reduce an amplitude of the output signal.

2. An rate adaptation system comprising:

a first first in, first out (FIFO) buffer configured to serially receive a first plurality data blocks via a first data bus at a rate based on a first clock, the first FIFO buffer further configured to output the first plurality of data blocks in an order received responsive to valid read requests of a plurality of read requests, at a rate based on a second clock;

a rate adaptation transmit register configured to serially provide a second plurality of data blocks from a second FIFO buffer to a second data bus at a rate based on the second clock, wherein a frequency of the first clock is greater than a frequency of the second clock; and

a barrel shift slot register configured to, responsive to the first clock, provide the first plurality of data blocks from the first FIFO buffer to the second FIFO buffer at a rate based on the second clock.