SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In order to improve the reliability of a semiconductor device, dummy wiring includes: a first dummy part provided to be spaced apart from and to be parallel to, of a plurality of sides that form a pad, a first side nearest to a corner; and a second dummy part provided to be spaced apart from and to be parallel to, of the sides that form the pad, a second side nearest to an edge side of a semiconductor chip. That is, the dummy wiring is formed by: a first dummy part extending along the first side of the pad; and a second dummy part extending along the second side of the pad.
The disclosure of Japanese Patent Application No. 2014-045679 filed on Mar. 7, 2014 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
BACKGROUNDThe present invention relates to a semiconductor device and a manufacturing technique thereof, and for example, to a technology effective in applying to a semiconductor device having pads and a manufacturing technique thereof.
Japanese Unexamined Patent Application Publication No. 2003-45876 describes a technique for forming dummy wiring around a pad.
Japanese Unexamined Patent Application Publication No. Hei 5 (1993)-235085 describes a technique for providing a dummy pad exposed from a cover film so as to surround a bonding pad.
Japanese Unexamined Patent Application Publication No. 2010-10197 describes a technique for providing, in a corner of a semiconductor chip, a small pad to be used exclusively for a probe.
SUMMARYFor example, in a pad formed in a semiconductor chip, an end portion of the pad is covered with a surface protective film, while most of the surface of the pad is exposed from an opening provided in the surface protective film. That is, in the end portion of the pad, the surface protective film is formed to cover a level difference resulting from the thickness of the pad.
Herein, a crack may occur in the surface protective film, covering a level difference formed in the end portion of the pad, by the stress applied when dicing for cutting semiconductor chips into pieces is performed, or the stress applied from a sealing body for sealing a semiconductor chip, etc. In particular, for a pad arranged near a corner of a semiconductor chip having a rectangular shape, there is the tendency that a crack is likely to occur in a surface protective film covering a level difference formed in an end portion of the pad. That is, because stress is likely to be applied in a corner of a semiconductor chip, occurrence of a crack is likely to become obvious in a surface protective film covering a level difference formed in an end portion of a pad. From the fact described above, there is room for improvement in the current semiconductor devices, from the viewpoint of improving the reliability of a semiconductor device by suppressing occurrence of a crack in a surface protective film covering a level difference formed in an end portion of a pad.
Other problems and new characteristics will become clear from the description and accompanying drawings of the present specification.
A semiconductor device according to one embodiment has dummy wiring provided around a first pad arranged at a position nearest to a corner of a semiconductor chip. In this case, the dummy wiring includes: a first dummy part provided to be spaced apart from and to be parallel to, of a plurality of sides that form the first pad, a first side nearest to the corner of the semiconductor chip; and a second dummy part provided to be spaced apart from and to be parallel to a second side nearest to an edge side of the semiconductor chip.
A method of manufacturing a semiconductor device according to one embodiment includes the steps of: forming a plurality of pads each having a rectangular shape along a boundary line between a chip region and a scribe region and within the chip region; and forming dummy wiring around, of the pads, a first pad nearest to a corner of the chip region. In this case, the dummy wiring includes: a first dummy part provided to be spaced apart from and to be parallel to, of a plurality of sides that form the first pad, a first side nearest to a corner of a semiconductor chip; and a second dummy part provided to be spaced apart from and to be parallel to a second side nearest to an edge side of the semiconductor chip.
According to one embodiment, the reliability of a semiconductor device can be improved.
When necessary for convenience in the following embodiment, description is given by dividing the embodiment into a plurality of sections or embodiments, however, unless stated explicitly, they are not independent of one another, but one is related with the other part or the whole as a modification example, a detail, supplementary description, etc.
When referring to the number of elements, etc. (including number of pieces, numerical value, quantity, range, etc.) in the following embodiment, unless stated explicitly or except when the number is obviously limited to specific numbers in principle, the number is not limited to the specific ones but may be more or less than the specific numbers.
Further, in the following embodiment, it is needless to say that components (also including constituent steps, etc.) are not necessarily requisite unless stated explicitly or except when they are obviously requisite in principle.
Similarly, when referring to the shapes and positional relations, etc., of components, etc., in the following embodiment, unless stated explicitly or except when they can be thought otherwise in principle, those substantially the same or similar to the shapes, etc., are to be included. This also applies to the aforementioned numerical values and ranges.
In addition, like components are denoted with like reference numerals in principle in each of the views for explaining embodiments, and duplicated descriptions are omitted. For easy understanding of drawings, hatching lines are sometimes drawn even in a plan view.
Embodiment Example of Configuration of Semiconductor Device (QFP Package)There are various types of package structures of semiconductor devices, such as, for example, a BGA (Ball Grid Array) package and a QFP (Quad Flat Package) package. The technical ideas of the present embodiments can be applied to these packages, and hereinafter a configuration of a semiconductor device including a QFP package will be described as an example.
Subsequently, the internal structure of the semiconductor device SA1 will be described.
The chip mounting part TAB, the inner lead IL1, and the outer lead OL are formed, for example, of a copper material, 42 Alloy (alloy of iron and nickel), or the like, while the wire W is formed, for example, of a gold wire. The semiconductor chip CHP is formed, for example, of silicon or a compound semiconductor (GaAs, etc.), and a plurality of semiconductor elements, such as MOSFETs, are formed in this semiconductor chip CHP. Multilayer wiring is formed above the semiconductor elements via an interlayer insulating film, and a pad PD to be coupled to the multilayer wiring is formed in the uppermost layer of the multilayer wiring. Accordingly, the semiconductor elements formed in the semiconductor chip CHP are electrically coupled to the pad PD via the multilayer wiring. That is, an integrated circuit is formed by the semiconductor elements, formed in the semiconductor chip CHP, and the multilayer wiring, and the pad PD functions as a terminal for coupling the integrated circuit and the outside of the semiconductor chip CHP together. The pad PD is coupled to the inner lead IL1 by the wire W, and is also coupled to the outer lead OL formed integrally with the inner lead IL1. From this, it is known that the integrated circuit, formed in the semiconductor chip CHP, can be electrically coupled to the outside of the semiconductor device SA1 by a pathway including the pad PD, the wire W, the inner lead IL1, the outer lead OL, and an external coupling device in this order. That is, it is known that the integrated circuit, formed in the semiconductor chip CHP, can be controlled by inputting an electrical signal from the outer lead OL formed in the semiconductor device SA1. It is also known that an output signal from the integrated circuit can be taken out from the outer lead OL to the outside.
Subsequently,
Herein, a crack may occur in the surface protective film, covering the end portion of the pad PD, by stress applied when dicing, for cutting the semiconductor chips CHP into pieces, is performed, or stress applied from the resin (sealing body) for sealing the semiconductor chip CHP, etc. In particular, there is the tendency that a crack is likely to occur in the surface protective film in a peripheral region R1 of a pad PD1 arranged to be nearest to a corner CNR of the semiconductor chip CHP, as illustrated, of
<Room for Improvement>
When attention is focused on a region B1 illustrated in
Moreover, semiconductor elements represented by a field-effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) and the wiring to be coupled to the semiconductor elements are recently being miniaturized. With such miniaturization of the semiconductor elements and the wiring being developed, there is the tendency that the thickness of the pad PD becomes large. It is because the development of the generations of the miniaturization of the semiconductor elements and the wiring actually means that an integrated circuit formed in the semiconductor chip CHP is highly integrated, and thereby an amount of the current to be used in the semiconductor chip CHP is increased, although it is superficially thought that, with the aforementioned development, the thickness of the pad PD is also made small. That is, an increase in the amount of current to be used in the semiconductor chip CHP means that a large current flows through the pad PD coupled to a highly integrated circuit, which requires the thickness of the pad PD to be made large, because the resistance of the pad PD needs to be made as low as possible. From this, there is the tendency that the thickness of the pad PD becomes large, with the development of the generations of miniaturization. This means that a level difference, resulting from the thickness of the pad PD, becomes large in a product manufactured in a developed generation of miniaturization. Thereby, it can be considered that precipituousness of the covering shape of the surface protective film PAS and thinning of the thickness of the surface protective film PAS may become remarkable in the region B1 illustrated, for example, in
From the facts described above, it can be considered that: the stress applied from the resin MR to the region B1 of the surface protective film PAS, covering the end portion of the pad PD arranged to be nearest to the corner CNR of the semiconductor chip CHP, becomes large in a product manufactured in a developed generation of miniaturization; and as a result thereof, occurrence of a crack CLK in the surface protective film PAS becomes more obvious. That is, it can be considered that, in a product manufactured in a more developed generation of miniaturization and in the pad PD arranged to be nearest to the corner CNR of the semiconductor chip CHP, the crack CLK is more likely to occur in the surface protective film PAS, due to a level difference resulting from the thickness of the pad PD, and hence it becomes more necessary to suppress occurrence of a crack CLK in the surface protective film PAS.
When the crack CLK occurs in the surface protective film PAS as illustrated in
Accordingly, a device is incorporated in the present embodiment, in which occurrence of the crack CLK in the surface protective film PAS, resulting from a level difference occurring due to the thickness of the pad PD, is suppressed. Hereinafter, the technical ideas of the present embodiment incorporating this device will be described.
<Configuration of Semiconductor Chip>
As used herein, the “major component” means, of constituent materials that form members (layers and films), a material component that is included in the largest amount, and for example, the “pad PD including aluminum as a major component” means that the material for the pad PD includes aluminum (Al) in the largest amount. In the present specification, the term “major component” is intended to express that, for example, the pad PD is basically formed by aluminum but the case where impurities are also included is not excluded.
For example, when attention is focused on the pad PD generally used in a semiconductor device, this pad PD has a configuration in which an aluminum film is usually sandwiched by barrier conductor films including a titanium/titanium nitride film. That is, the pad PD including a first barrier conductor film, an aluminum film formed over the first barrier conductor film, and a second barrier conductor film formed over the aluminum film. In this case, when the pad PD is formed by a laminated film including the first barrier conductor film, the aluminum film, and the second barrier conductor film, this pad PD is referred to as the “pad PD including aluminum as a major component”, because the pad PD is mostly occupied by the aluminum film.
Additionally, the aluminum film as used herein is used to have a wide concept including: an aluminum film having pure aluminum; an aluminum alloy film (AlSi film) having silicon added to aluminum; and an aluminum alloy film (AlSiCu film) having silicon and copper added to aluminum. The pads PD including these aluminum alloy films are also included in the “pad PD including aluminum as a major component.” That is, the “pad PD including aluminum as a major component” as used herein is applied to the pad PD including an aluminum film and a barrier conductor film, and also applied to the pad PD in which an aluminum film itself is an aluminum alloy film.
Characteristics in EmbodimentSubsequently, characteristic points in the present embodiment will be described.
For simple description, the dummy region DMR is described as part of the semiconductor chip CHP in the present embodiment. However, the dummy region DMR is a region integrated with the scribe region SCR in a wafer state before dicing is performed. Accordingly, the dummy region DMR may be expressed as part of the scribe region SCR in the later description.
The pads PD are arranged in a region inside the seal ring region SRR. Of the pads PD, the pad arranged at a position nearest to the corner CNR of the semiconductor chip CHP is referred to as a pad PD 1 in the present specification.
As illustrated in
Subsequently,
Herein, the pad PD1 is electrically coupled to the field-effect transistor Q formed over the semiconductor substrate 1S via the global layer GL and the fine layer FL, as illustrated in
Subsequently, the surface protective film PAS is formed to cover the pad PD1 and the dummy wiring DML, which are formed in the same layer. The surface protective film PAS is formed of a laminated film including, for example, the silicon oxide film OXF and the silicon nitride film SNF. The opening OP is formed in the surface protective film PAS, and part of the surface of the pad PD is exposed from the bottom of the opening OP. On the other hand, an opening is not formed over the dummy wiring DML, and the dummy wiring DML is covered with the surface protective film PAS.
The wire W including, for example, a gold wire is coupled to the surface of the pad PD exposed from the opening OP, and the surface protective film PAS, including the surface of the pad PD1 to which the wire W is coupled, is covered, for example, with the resin MR.
Subsequently,
The seal ring SRG disclosed in the present embodiment is formed by coupling a multilayer wiring layer, and is coupled to the semiconductor substrate 1S. Although not illustrated in detail, the seal ring SRG is coupled to a well formed in the semiconductor substrate 1S to have a fixed potential, such as a ground potential, etc. On the other hand, the dummy pattern DP is formed by a multilayer wiring layer, similarly to the seal ring SRG, and respective wiring layers may be coupled together or separated from each other. Unlike the seal ring SRG, the dummy pattern DP is not coupled to a fixed potential and is in a floating state.
As illustrated in
Herein, a wiring structure and a device structure, which are formed in layers lower than the pad PD1 and the dummy wiring DML formed in the integrated circuit region ICR, are basically the same as those in
As described above, the present embodiment is characterized by the fact that the dummy wiring DML is provided around the pad PD1 arranged at a position nearest to the corner CNR of the semiconductor chip CHP, as illustrated, for example, in
Herein, when attention is first focused on the region B1 in
On the other hand, when attention is focused on the region D1 in
According to the present embodiment, by thus providing the dummy wiring DML in a near-field region of the end portion of the pad PD1, the precipitousness of the curving shape of the surface protective film PAS, covering the end portion of the pad PD1, can be made gentle and the thickness of the surface protective film PAS can be made large in the region D1 of the surface protective film PAS, even if a level difference resulting from the thickness of the pad PD1 is present in the region D1. That is, by providing the dummy wiring DML in a near-field region of the end portion of the pad PD1, stress resistance can be improved in the region D1 to which the stress from the resin MR that seals the surface protective film PAS is likely to be applied, according to the present embodiment. As a result thereof, occurrence of a crack in the surface protective film PAS can be suppressed in the region D1, according to the present embodiment, and thereby “aluminum slide”, which is likely to occur when a heat cycle test is performed in a state where a crack occurs in the surface protective film PAS, can be effectively suppressed. The fact that the “aluminum slide” can be suppressed means that an appearance defect of the pad PD1 can be reduced, and thereby the reliability of a semiconductor device can be improved according to the present embodiment.
There is the tendency that, with the generations of miniaturization of both semiconductor elements represented by a field-effect transistor and wiring being developed, the thickness of the pad PD1 becomes larger. This means that, in a product manufactured in a developed generation of miniaturization, a level difference resulting from the thickness of the pad PD1 becomes large. Accordingly, it can be considered that, when miniaturization of semiconductor elements and wiring is developed, the precipitousness of the covering shape of the surface protective film PAS, covering the end portion of the pad PD1, and the thinning of the thickness of the surface protective film PAS are likely to become obvious as problems. That is, with a product manufactured in a more developed generation of miniaturization, a crack is more likely to occur in the surface protective film PAS, due to a level difference resulting from the thickness of the pad PD1. Accordingly, it can be considered that, in a product manufactured in a developed generation of miniaturization, it becomes further important to suppress occurrence of a crack in the surface protective film PAS.
Regarding this point, the dummy wiring DML is formed in a near-field region of the pad PD1 in the present embodiment, and as a result thereof, even if a level difference resulting from the thickness of the pad PD1 is generated, the precipitousness of the covering shape of the surface protective film PAS, covering the end portion of the pad PD1, is made gentle and the thickness of the surface protective film PAS becomes large. This phenomenon will be similarly generated, even if the thickness of the pad PD1 becomes large and a level difference resulting from the thickness of the pad PD1 becomes large, with the generations of miniaturization of semiconductor elements and wiring being developed. From this, by forming the dummy wiring DML in a near-field region of the pad PD1, occurrence of a crack in the surface protective film PAS, covering the end portion of the pad PD1, can be effectively prevented according to the present embodiment, even if the generations of miniaturization of semiconductor elements and wiring are developed and a level difference resulting from the thickness of the pad PD1 becomes large. When the generations of miniaturization are developed and a level difference resulting from the thickness of the pad PD1 becomes large, namely, when occurrence of a crack is likely to become obvious, the availability of applying the technical ideas of the present embodiment is increased. However, it is needless to say that the remarkable effect that occurrence of a crack in the surface protective film PAS, covering the end portion of the pad PD1, is suppressed can be acquired by the technical ideas of the present embodiment, regardless of how large a level difference resulting from the thickness of the pad PD1 is.
In the present embodiment, the dummy wiring DML is provided around the pad PD1 nearest to the corner CNR of the semiconductor chip CHP, as illustrated in
On the other hand, the dummy wiring DML is not provided around the pads PD other than the pad PD1 nearest to the corner CNR of the semiconductor chip CHP in the present embodiment, as illustrated, for example, in
In the present embodiment, the dummy wiring DML is thus provided only around the pad PD1 where occurrence of a crack becomes obvious, while it is not provided around the pads PD other than the pad PD1. That is, in the present embodiment, the dummy wiring DML is provided around the pad PD1 of minimum necessity where occurrence of a crack in the surface protective film becomes obvious, while it is not provided around the pads PD other than the pad PD1, because occurrence of a crack in the surface protective film hardly becomes obvious. Thereby, occurrence of a crack in the surface protective film can be suppressed without significant design modification of the pads PD, according to present embodiment. When expressed in another way, the distance between the respective pads PD becomes large if the dummy wiring DML is provided for each of the pads PD, which may cause an increase in the size of the semiconductor chip CHP. On the other hand, the dummy wiring DML is provided only around the pad PD1 of minimum necessity where occurrence of a crack in the surface protective film becomes obvious, in the present embodiment, and hence occurrence of a crack in the surface protective film can be suppressed without an increase in the size of the semiconductor chip CHP. That is, the remarkable effect that the reliability of a semiconductor device can be improved can be acquired, while the miniaturization of the semiconductor device is being kept, according to the present embodiment.
Additionally, in the present embodiment, the level of the surface of the pad PD1 and that of the surface of the dummy wiring DML are the same as each other, as illustrated in
From the facts described above, it is desirable to form the pad PD1 and the dummy wiring DML such that the levels of the surfaces thereof are the same as each other, from the viewpoint that the crack resistance of the surface protective film PAS, covering the end portion of the pad PD1, is increased by making the covering shape of the surface protective film PAS gentle and making the thickness of the surface protective film PAS in the region D1 large. However, when the dummy wiring DML is provided according to the technical ideas of the present embodiment, occurrence of a crack in the surface protective film PAS, covering the end portion of the pad PD1, can be suppressed, even in both of the cases where the levels of the surfaces of the pad PD1 and the dummy wiring DML are different from each other, and where the levels of the surfaces thereof are the same as each other.
Further, it is desirable to make the distance between the pad PD1 and the dummy wiring DML as small as possible, from the viewpoint that the crack resistance of the surface protective film PAS is improved. It is because, as the distance between the two becomes smaller, a level difference, resulting from the thickness of the pad PD1, is more hardly reflected in the covering shape of the surface protective film PAS. That is, as the distance between the two becomes smaller, the covering shape of the surface protective film PAS becomes duller to a level difference resulting from the thickness of the pad PD1. That is, by making the distance between the two small, the covering shape of the surface protective film PAS, covering the end portion of the pad PD1, can be made gentle and the thickness of the surface protective film PAS can be made large, in the region D1 illustrated in
Accordingly, it is desirable to make the levels of the surfaces of the pad PD1 and the dummy wiring DML the same as each other and to make the distance between the two small, from the viewpoint of increasing the crack resistance of the surface protective film PAS by making the covering shape of the surface protective film PAS, covering the end portion of the pad PD1, gentle and making the thickness of the surface protective film PAS in the region D1 large.
In the present embodiment, the covering shape of the surface protective film PAS in the region D1 can be made gentle and the thickness of the surface protective film PAS in the region D1 can be made large, but the covering shape of the surface protective film PAS covering the outside of the dummy wiring DML becomes one in which a level difference resulting from the thickness of the dummy wiring DML is reflected, as illustrated in
From the facts described above, it is desirable to make the distance between the pad PD1 and the dummy wiring DML small, from the viewpoint of increasing the crack resistance of the surface protective film PAS, covering the end portion of the pad PD1, by making the covering shape of the surface protective film PAS gentle and making the thickness of the surface protective film PAS in the region D1 large. On the other hand, if the distance between the pad PD1 and the dummy wiring DML becomes too small, there is the possibility that the pad D1 may undergo “aluminum slide” resulting from the “aluminum slide” of the dummy wiring DML. Accordingly, there is an optimal range of the distance between the pad PD1 and the dummy wiring DML, the range which is from a certain distance while the distance is preferably made small, from the viewpoint of avoiding an appearance defect of the pad PD1 by surely preventing the “aluminum slide” of the pad PD1. The distance between the pad PD1 and the dummy wiring DML can be set, for example, by collecting data on amounts of movement by “aluminum slide”.
<Method of Manufacturing Semiconductor Device> A semiconductor device according to the present embodiment is configured as described above, and hereinafter a manufacturing method thereof will be described with reference to the drawings.
As illustrated in
Subsequently, patterning is performed on the laminated film, including the barrier conductor film BCF1, the aluminum film AF, and the barrier conductor film BCF2, by using a photolithography technique and an etching technology, as illustrated in
In this step, the pads PD each having a rectangular shape are formed in the chip region CR and along a boundary line between the chip region CR and the scribe region SCR (see
Subsequently, a silicon oxide film OXF covering the pad PD1 and the dummy wiring DML is formed over the interlayer insulating film IL, as illustrated in
In this case, the dummy wiring DML is formed in a near-field region of the pad PD1 in the present embodiment, and hence, even if a level difference resulting from the thickness of the pad PD1 is generated, the precipitousness of the covering shape of the surface protective film PAS, covering the end portion of the pad PD1, is made gentle and the thickness of the surface protective film PAS in the end portion of the pad PD1 can be made large.
Subsequently, the opening OP for exposing part of the surface of the pad PD1 is formed in the surface protective film PAS by using a photolithography technique and an etching technology, as illustrated in
Thus, the pad PD1 can be formed in the uppermost layer of the multilayer wiring layer.
Herein, the dummy region DMR is a region integrated with the scribe region SCR. When the semiconductor wafer is cut into the respective semiconductor chips in the later-performed dicing step, part of the scribe region SCR remains inside the edge side ES of the semiconductor chip. In the present embodiment, the remaining region is described as the dummy region DMR. That is, the region near to the chip edge side ES from the seal ring region SRR is referred to as the scribe region SCR (dummy region DMR), while the region away from the seal ring region SRR is referred to as the integrated circuit region ICR, in the present embodiment.
The dummy pattern DP is formed in the dummy region DMR, and the seal ring SRG is formed in the seal ring region SRR. The dummy pattern DP and the seal ring SRG are formed in the same step as that of forming the multilayer wiring (not illustrated in
Subsequently, the following steps will be described with reference to a flowchart.
After an integrated circuit is first formed in each of the chip regions over the semiconductor wafer, the semiconductor wafer is diced along the scribe region (FIG. 21/S101). Thereby, the chip regions are cut into pieces and a semiconductor chip, in which an integrated circuit is formed, can be acquired. After the semiconductor chip is mounted over the chip mounting part formed in the lead frame (FIG. 21/S102), the pad formed in the semiconductor chip and the inner lead are coupled together by a wire (FIG. 21/S103). Then, the chip mounting part, the semiconductor chip, the wire, and the inner lead are sealed with a resin (FIG. 21/S104). After a dam formed in the lead frame is cut (FIG. 21/S105), a metal-plated film is formed over the surface of the outer lead exposed from the resin (FIG. 21/S106). Subsequently, a mark is formed over the surface of the resin (FIG. 21/S107), and the outer lead exposed from the resin is shaped (FIG. 21/S108). After a semiconductor device is thus manufactured, an electrical property inspection is performed (FIG. 21/S109). A heat cycle test is then performed on the semiconductor device (FIG. 21/S110), and a product determined to be a good product is shipped as a product.
Herein, in the present embodiment, by providing the dummy wiring DML in a near-field region of the end portion of the pad PD1, as illustrated, for example, in
Typical effects acquired by the technical ideas of the present embodiment will be summarized as follows:
(1) In the pad nearest to the corner of a semiconductor chip, the precipitousness of the surface protective film, covering the end portion of the pad, is made gentle and the thickness of the surface protective film, covering the end portion of the pad, becomes large, and as a result thereof, the stress from a resin (sealing body) can be suppressed. Thereby, occurrence of a crack in the surface protective film, covering the end portion of the pad nearest to a corner of the semiconductor chip, can be suppressed according to the present embodiment.
(2) Because occurrence of a crack in the surface protective film, covering the end portion of the pad nearest to a corner of the semiconductor chip, can be suppressed according to the present embodiment, “aluminum slide”, which is likely to occur when a heat cycle test is performed in a state where a crack occurs in the surface protective film, can be effectively suppressed.
(3) Because “aluminum slide” can be suppressed according to the present embodiment, an appearance defect of the pad can be reduced, and thereby the reliability of a semiconductor device can be improved.
(4) In the present embodiment, occurrence of a crack in the surface protective film, covering the end portion of a pad, can be effectively prevented, even if the generations of miniaturization of semiconductor elements and wiring are developed and a level difference resulting from the thickness of a pad becomes large. Accordingly, when a generation of miniaturization is developed and a level difference resulting from the thickness of the pad particularly becomes large, namely, when occurrence of a crack is likely to become obvious, the availability of the technical ideas of the present embodiment is increased.
(5) Further, by making the levels of the surfaces of a pad and dummy wiring the same as each other and by making the distance between the pad and the dummy wiring within a certain range, the covering shape of the surface protective film, covering the end portion of the pad, becomes gentle and the thickness of the surface protective film, covering the end portion of the pad, becomes large, and thereby crack resistance can be further improved in the present embodiment.
<First Variation>
<Second Variation>
<Third Variation>
<Fourth Variation>
<Fifth Variation>
As a result, the precipitousness of the covering shape of the surface protective film PAS, covering the end portion of the pad PD1, is made gentle and the thickness of the surface protective film PAS, covering the end portion of the pad PD1, becomes large, also in the present Fifth Variation, as illustrated in
The present Fifth Variation further has a peculiar advantage that: not only the precipitousness of the covering shape is made gentle and the thickness of the surface protective film PAS becomes large in the surface protective film PAS covering the end portion of the pad PD1, but also the precipitousness of the covering shape of the surface protective film PAS, covering the end portion of the dummy wiring DML, is made gentle and the thickness thereof becomes large.
Hereinafter, the reason will be described. For example, in the embodiment illustrated in
Regarding this point, the thickness of the surface protective film PAS formed over the dummy wiring DML becomes smaller than that of the surface protective film PAS formed over the pad PD1, in the present Fifth Variation illustrated, for example, in
The invention made by the present inventors has been specifically described above based on its preferred embodiments, but it is needless to say that the invention should not be limited to the embodiments and may be modified variously within a range not departing from the gist thereof.
Claims
1. A semiconductor device comprising:
- a semiconductor chip having a rectangular shape,
- wherein the semiconductor chip includes:
- (a) a plurality of pads arranged along an edge side of the semiconductor chip; and
- (b) dummy wiring provided around, of the pads, a first pad that is arranged at a position nearest to a corner of the semiconductor chip and has a rectangular shape, and
- wherein the dummy wiring includes:
- (b1) a first dummy part provided to be spaced apart from and to be parallel to a first side nearest to the corner, of a plurality of sides that form the first pad; and
- (b2) a second dummy part provided to be spaced apart from and to be parallel to a second side nearest to the edge side of the semiconductor chip of the sides that form the first pad.
2. The semiconductor device according to claim 1,
- wherein a semiconductor element is formed in the semiconductor chip, and
- wherein the dummy wiring is not electrically coupled to the semiconductor element, so that the dummy wiring does not function as wiring.
3. The semiconductor device according to claim 2,
- wherein a potential of the dummy wiring is in a floating state.
4. The semiconductor device according to claim 1,
- wherein the dummy wiring is formed in the same layer as that of the first pad.
5. The semiconductor device according to claim 4,
- wherein a level of a surface of the dummy wiring is the same as that of a surface of the first pad.
6. The semiconductor device according to claim 1,
- wherein a seal ring, for suppressing a foreign substance from entering inside of the semiconductor chip, is formed between the second dummy part and the edge side of the semiconductor chip.
7. The semiconductor device according to claim 6,
- wherein a semiconductor element is formed in the semiconductor chip, and
- wherein wiring to be electrically coupled to the semiconductor element is not provided between the first pad and the seal ring.
8. The semiconductor device according to claim 1,
- wherein the first dummy part and the second dummy part are formed integrally with each other.
9. The semiconductor device according to claim 8,
- wherein the first dummy part and the second dummy part are coupled together by a slant part.
10. The semiconductor device according to claim 8,
- wherein, while located between the pads and the edge side of the semiconductor chip, the second dummy part extends along the edge side of the semiconductor chip.
11. The semiconductor device according to claim 1,
- wherein the first dummy part is formed by a plurality of dot patterns, and
- wherein the second dummy part is formed by a plurality of dot patterns.
12. The semiconductor device according to claim 11,
- wherein, while located between the pads and the edge side of the semiconductor chip, the second dummy part extends along the edge side of the semiconductor chip.
13. The semiconductor device according to claim 1,
- wherein a surface protective film is formed to cover the pads and the dummy wiring, and
- wherein an opening, for exposing part of a surface of each of the pads, is formed in the surface protective film.
14. The semiconductor device according to claim 13,
- wherein a level of the surface protective film covering the dummy wiring is lower than that of the surface protective film covering the first pad, while a level of a surface of the first pad is the same as that of a surface of the dummy wiring.
15. The semiconductor device according to claim 13,
- wherein the semiconductor chip is sealed by a sealing body including a resin.
16. A method of manufacturing a semiconductor device comprising the steps of:
- (a) providing a semiconductor substrate including a chip region having a rectangular shape and a scribe region partitioning the chip region; and
- (b) forming a plurality of pads each having a rectangular shape along a boundary line between the chip region and the scribe region, and forming dummy wiring around, of the pads, a first pad nearest to a corner of the chip region,
- wherein the dummy wiring formed in the step (b) includes:
- a first dummy part provided to be spaced apart from and to be parallel to a first side nearest to a corner of the chip region, of a plurality of sides that form the first pad; and
- a second dummy part provided to be spaced apart from and to be parallel to a second side nearest to the boundary line, of the sides that form the first pad.
17. The method of manufacturing a semiconductor device according to claim 16, comprising the steps of:
- (c) forming a surface protective film covering the pads and the dummy wiring;
- (d) forming an opening for exposing part of a surface of each of the pads in the surface protective film;
- (e) after the step (d), acquiring a semiconductor chip by dicing the semiconductor substrate along the scribe region;
- (f) after the step (e), coupling a wire to the surface of each of the pads exposed from the opening; and
- (g) after the step (f), sealing the semiconductor chip.
18. The method of manufacturing a semiconductor device according to claim 17, comprising the step of:
- after the step (g), performing a heat cycle test.
19. The method of manufacturing a semiconductor device according to claim 17,
- wherein the step (c) includes the steps of:
- (c1) forming a silicon oxide film so as to cover the pads and the dummy wiring; and
- (c2) forming a silicon nitride film over the silicon oxide film.
20. The method of manufacturing a semiconductor device according to claim 19,
- wherein the step (c1) is performed by using a high-density plasma CVD process.
Type: Application
Filed: Mar 4, 2015
Publication Date: Sep 10, 2015
Inventor: Kentaro Saito (Kawasaki-shi)
Application Number: 14/639,062