METHOD FOR PARSING NETWORK PACKETS HAVING FUTURE DEFINED TAGS
Methods and systems are provided for enabling existing or legacy network devices to handle packets defined in accordance with future-defined standards, without having to be re-configured to be compatible with these standards. A transmitting network device may generate packets, and may set in the packets indication fields (e.g., tag header type fields) to indicate when particular fields (e.g., tag header fields) are inserted into the packets, including unknown or newly-defined fields. The indication fields may enable a receiving device to handle the packets by skipping, when necessary, over these fields (e.g., including the unknown or newly-defined fields). The indication fields may, for example, identify for each packet a remaining portion to jump to without reading the inserted fields.
This relates to data transfer and processing in computer networks such as the Ethernet, and more particularly, to parsing network packets in which additional information such as a tag header is inserted according to future-defined standards and protocols.
BACKGROUND OF THE INVENTIONOne way of transmitting a packet defined in accordance with an existing network protocol (e.g., a Fibre Channel packet) over the Ethernet network is to encapsulate such a packet in the payload portion of an Ethernet frame. As a result, the Ethernet frame with the packet encapsulated therein typically contains an EtherType field that indicates the type of the protocol of the encapsulated packet. For example, FIG. lA illustrates an exemplary packet frame 100 in which an Internet Protocol (IP) packet is encapsulated or embedded. As can be seen, this frame 100 includes different fields, such as the Media Access Control (MAC) destination address 102 and the MAC source address 104, which identify the destination of the packet and the source of the packet, respectively, in the network. Usually following the MAC source address 104 is the EtherType field, i.e., EtherType 106, as shown in
When a network packet, such as the one illustrated in
An existing packet frame as shown in
This relates to allowing an existing or legacy network device to recognize and parse packets defined in accordance with future-defined standards without having to be re-configured to be compatible with such standards. In particular, the device can skip past unknown or newly-inserted fields, such as tag headers in a tagged packet, to parse and process the remainder of the packet. In one embodiment, when parsing a tagged packet, a parser in the device can skip a tag header based on the tag header type, which usually indicates a fixed or pre-defined length of the tag header, and continue to read an EtherType field past the tag header. Based on the EtherType, the device can recognize the encapsulated protocol and offload further processing of the packet to appropriate dedicated hardware for efficiency. By skipping those added fields such as a tag header, the device can accommodate various future-defined standards without incurring additional engineering or design costs or compromising packet processing efficiency.
In the following description of preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which it is shown by way of illustration specific embodiments in which the invention can be practiced. It is to be understood that other embodiments can be used and structural changes can be made without departing from the scope of the embodiments of this invention.
Embodiments of the invention allow an existing or legacy network device to recognize and parse packets defined in accordance with future-defined standards without having to be re-configured to be compatible with such standards. In particular, the device can skip past unknown or newly-inserted fields, such as tag headers in a tagged packet, to parse and process the remainder of the packet. In one embodiment, when parsing a tagged packet, a parser in the device can skip a tag header based on the tag header type, which usually indicates a fixed or pre-defined length of the tag header, and continue to read an EtherType field past the tag header. Based on the EtherType, the device can recognize the encapsulated protocol and offload further processing of the packet to appropriate dedicated hardware for efficiency. By skipping those added fields such as a tag header, the device can accommodate various future-defined standards without incurring additional engineering or design costs or compromising packet processing efficiency.
Although embodiments of the invention may be described and illustrated herein using tag headers under 802.1Q as examples, it should be understood that embodiments of this invention are not so limited, but are applicable to many future-developed or defined standards and protocols. Additionally, embodiments of the invention are not limited to Ethernet networks and are compatible with any networking protocol that uses an enumerated field to indicate what type of content follows within a packet or byte stream. Also, embodiments of the invention can be implemented in a host bus adapter (HBA), a converged network adapter (CNA), a network interface card (NIC), target channel adapter (TCA), or any other similar device that enables hardware offloading of packet processing.
Referring now to
At step 302, the device determines whether the first portion of the packet contains a known EtherType. If so, the device can proceed with offloading the processing of the packet to dedicated hardware at step 304. For example, the parser of the network device may recognize the EtherType as indicating an IP packet being encapsulated in the received packet, as illustrated in
In one embodiment, if the first portion is not a known EtherType, the device further determines at step 306 whether the first portion contains a known tag header type. For example, the first portion may contain a tag header type indicating the inserted tag header is an 802.1Q header, as shown in
If the first portion is a known tag header type, the device proceeds to step 310 to determine a tag header length associated with the tag header type so that the parser in the device can bypass the inserted tag header to read the remainder of the packet. In one configuration, the device may include one or more programmable registers (as shown in
Once the tag header length is determined from the associated tag header type, the parser in the device can determine the remainder of the packet at step 312. Using the example in
According to some embodiments, the processing of the packet can depend on the tag header type. For example, a network device can drop all packets of a certain tag header type, hardware offload can be disallowed for packets of a certain tag header type, or packets of a certain tag header type can be sent to a programmable receive client. According to some embodiments, network devices can process a packet in this way only based on the tag header type with no capability to interpret or process the tag header. For example, a network device with no capability to interpret an 802.1Q tag header can nonetheless recognize an 802.1Q tag header type. Such a device can recognize and then drop all packets with an 802.1Q tag header type, even though it has no capability to interpret or process an 802.1Q tag header. In this way, devices that lack hardware to interpret or process future-defined tag headers can still process packets containing such tag headers based only on the tag header type.
The algorithm in
In one embodiment, the various lengths 410, 412 and 414 in the programmable registers 408 can be pre-defined tag lengths according to respective network protocols. Alternatively, these lengths stored in the programmable registers 408 can be updated dynamically each time a new tag header type is added. For instance, the tables in
Processor(s) 704 may be implemented using any applicable processing-capable technology. Processor(s) 704 may be one or more processors such as central processing units (CPUs), microprocessors, controllers, dedicated processing circuits, digital signal processors (DSPs), processing portion(s) of an ASIC, some combination thereof, and so forth. Generally, processors 704 are capable of executing, performing, and/or otherwise effectuating processor-executable instructions, such as processor-executable instructions 708 in the memory 706.
The memory 706 comprises portions of computer-readable storage media, which may include volatile and non-volatile media, removable and non-removable media, storage and transmission media, and so forth. The memory 706 is tangible media when it is embodied as a manufacture and/or a composition of matter. By way of example only, storage media may include an array of disks or flash memory for longer-term mass storage of processor-executable instructions, random access memory (RAM) for shorter-term storing of instructions that are currently being executed and/or otherwise processed, hard-coded logic media (e.g., an application-specific integrated circuit (ASIC), a field programmable gate-array (FPGA), etc.), some combination thereof, and so forth. Transmission media may include link(s) on networks for transmitting communications and so forth.
In one embodiment, the memory 706 is comprised of one or more processor-accessible media, such as the processor-executable instructions 708 that are executable by the processor 702 to enable the network device 700 to perform the various functions and operations described herein, including (by way of example only) any of those that are associated with the illustrated features, aspects, components, and flow diagrams of
A network switch can be configured in a way similar to the above-described exemplary network device 700, except that the processor-executable instructions implemented therein enable the network switch to perform additional functions and operations described herein, such as acceptance or rejection of network device registration, traffic forwarding between different Network devices, etc. The network switch may include various components as defined by the Network and FC standards and customized by different vendors.
In practice, the methods, processes or steps described herein may constitute one or more programs made up of machine-executable or computer-executable instructions. The above description, particularly with reference to the steps and flow chart in
Although embodiments of this invention have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of embodiments of this invention as defined by the appended claims.
Claims
1-17. (canceled)
18. A method, comprising:
- generating a packet;
- inserting a tag header in the packet;
- setting a tag header type in a first portion of the packet to: indicate that the tag header is inserted; and identify a remaining portion of the packet, such that to enable reading the remaining portion of the packet without reading the tag header inserted in the packet.
19. The method of claim 18, comprising, when an additional tag header is inserted in the packet, setting an additional tag header type in a second portion of the packet to indicate that the additional tag header is inserted;
- wherein the additional tag header type is set to identify a second remaining portion of the packet, such that to enable reading the second remaining portion of the packet without reading the additional tag header inserted in the packet.
20. The method of claim 18, comprising setting the tag header type based on one or more tag header lengths, associated with corresponding one or more tag header types.
21. The method of claim 18, comprising generating the packet such that to enable controlling processing of the packet at a receiving device.
22. The method of claim 21, comprising setting a field in the remaining portion of the packet to enable controlling the processing of the packet at the receiving device.
23. The method of claim 22, wherein the field comprises an indication of which type of network frame is encapsulated in the packet.
24. The method of claim 21, wherein controlling the processing of the packet comprises offloading processing of the packet to a particular component of the receiving device, the particular component comprising hardware or software client.
25. A system, comprising:
- one or more circuits for use in a device, the one or more circuits are operable to: generate a packet; insert a tag header in the packet; and set a tag header type in a first portion of the packet to: indicate that the tag header is inserted; and identify a remaining portion of the packet, such that to enable reading the remaining portion of the packet without reading the tag header inserted in the packet.
26. The system of claim 25, wherein the one or more circuits are operable to, when an additional tag header is inserted in the packet set an additional tag header type in a second portion of the packet to indicate that the additional tag header is inserted;
- wherein the additional tag header type is set to identify a second remaining portion of the packet, such that to enable reading the second remaining portion of the packet without reading the additional tag header inserted in the packet.
27. The system of claim 25, wherein the one or more circuits are operable to set the tag header type based on one or more tag header lengths, associated with corresponding one or more tag header types.
28. The system of claim 25, wherein the identified remaining portion of the packet includes an indication of which type of network frame is encapsulated in the packet.
29. The system of claim 25, wherein the device is incorporated into a host bus adapter (HBA).
30. The system of claim 25, wherein the device is incorporated into a converged network adapter (CNA).
31. The system of claim 25, wherein the device is incorporated into a target channel adapter (TCA).
32. The system of claim 25, wherein the device is a network interface card (NIC).
33. A non-transitory computer-readable storage medium comprising processor-executable instructions, said instructions, while executed, causing a processor to:
- generate a packet;
- insert a tag header in the packet;
- set a tag header type in a first portion of the packet to: indicate that the tag header is inserted; and identify a remaining portion of the packet, such that to enable reading the remaining portion of the packet without reading the tag header inserted in the packet.
34. The non-transitory computer-readable storage medium of claim 33, wherein said instructions, while executed, cause the processor to, when an additional tag header is inserted in the packet, set an additional tag header type in a second portion of the packet to indicate that the additional tag header is inserted;
- wherein the additional tag header type is set to identify a second remaining portion of the packet, such that to enable reading the second remaining portion of the packet without reading the additional tag header inserted in the packet.
35. The non-transitory computer-readable storage medium of claim 33, wherein said instructions, while executed, cause the processor to set a field in the remaining portion of the packet to enable controlling the processing of the packet at a receiving device.
36. The non-transitory computer-readable storage medium of claim 33, wherein the field comprises an indication of which type of network frame is encapsulated in the packet.
37. The non-transitory computer-readable storage medium of claim 33, wherein controlling the processing of the packet comprises offloading processing of the packet to a particular component of the receiving device.
Type: Application
Filed: Oct 6, 2015
Publication Date: Jan 28, 2016
Inventors: Lawrence Howard Rubin (Austin, TX), Harish Kumar Shakamuri (Austin, TX)
Application Number: 14/876,595