Silicon Interposer Sndwich Structure for ESD, EMI, and EMC Shielding and Protection

Abstract

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

Description

FIELD OF THE INVENTION

The field of the invention comprises miniaturization of electronics through 3D packaging structures incorporating integrated circuit devices protected against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC)

BACKGROUND OF THE INVENTION

Miniaturization of electronics is a continuously evolving process in devices generated today. One way of achieving this is with 3D packaging using interposers incorporating Through Silicon Vias (TSV's). The TSV's allow a variety of additional function such as capacitance, resistance, inductance, and simple circuitry to be placed close to integrated circuits. These circuits are interconnected electrically and supported structurally while allowing efficient dissipation of heat. Such 3D packaging structures incorporating integrated circuit devices need to be protected from ESD which may damage or destroy circuitry, EMI from emission sources in the nearby environment, and EMC resulting in emission from the device requiring control so as to not interfere with other devices.

As 3D packaging continues to advance in complexity, multiple integrated circuit devices present on the same interposer silicon carrier will require simple modes of separation and isolation from ESD, EMI and EMC factors. Currently available technology can achieve the necessary isolation and protection of integrated circuit function but only at the cost of loss of the desired miniaturization. Individual devices must be placed on isolated interposers and large structures must be designed to shield and protect the integrated circuit device function. These would be constructed with base plates, lids, gaskets, and device separation common in the industry for shielding and protection but this defeats the enhancement of functional proximity otherwise afforded by the interposer TSV 3D packaging.

RELATED ART

The following patents, published applications, and literature exemplify the state of the art in the field of 3D packaging:

• Barth, et al., United States Published Patent Application No. 2010/0078779;
• Morrison, et al., U.S. Pat. No. 7,709,915;
• DiBiene, et al., U.S. Pat. No. 7,245,507;
• Lim, et al., IP.COM Technical Disclosure, IPCOM000169379D, “Shielding and Interconnection Interposer Substrate”, Apr. 24, 2008;
• Pelley, et al., U.S. Pat. No. 7,777,330;
• Lin, et al., United States Published Patent Application No. 2010/0237386;
• Anthony, et al., U.S. Pat. No. 7,733,621;
• England, et al., U.S. Pat. No. 7,622,786;
• Hollingsworth, et al., U.S. Pat. No. 7,002,217;
• Neidich, et al., U.S. Pat. No. 6,780,056.

SUMMARY OF THE INVENTION

The present invention comprises structures, articles of manufacture, processes and products produced by the processes that address the foregoing needs, and provides ESD, EMI and EMC shielding and protection of integrated circuit devices in 3D packaging. Examples of these devices comprise electronic devices such as semiconductor chips, semiconductor arrays, or wafers, or IC electronic components (integrated circuits, i.e.,“IC chips”) and other components such as but not limited to micro-electro-mechanical (MEMS) components, passive filters, detector arrays, photovoltaic displays, organic light-emitting diodes (OLEDs) and the like or SiGe, a III-V electronic device, or opto-electronics.

In one embodiment, this innovative idea provides for ESD, EMI and EMC shielding and protection of integrated circuit devices in 3D packaging by creating a sandwich of interposers around the integrated circuit device in which metallized shielding and diode protective devices may be incorporated into both the top and bottom interposers. TSV's would allow interconnection of the metallized shielding to ground or voltage as required electrically, and the bottom interposer in the sandwich connecting by TSV's and solder connection to the chip carrier package, and the top interposer connecting peripherally by TSV's beyond the outline of the integrated circuit device to the bottom interposer which would then connect electrically to the chip carrier. This would provide a miniature localized cage around the device and preserve the scale of integration and miniaturization desired with this technology.

In addition, multiple integrated circuit devices, which normally would need to be isolated in much larger or even separate packages, now may be placed adjacent to one another on the same interposer with TSV's by providing one or more top interposers to isolate the sensitive devices from one another in close proximity in the miniaturized sandwich package structure.

In one embodiment , the interposer sandwich structure as shown in FIG. 1 comprises two interposers enclosing a device requiring shielding or protection. A solder bump size hierarchy may be used with smaller solder bumps attaching the integrated circuit device to the interposer on the bottom, and larger solder bumps or other interconnection structure connecting the top interposer with the bottom interposer or directly with the chip carrier. The other interconnection structure may comprise copper post bumps or equivalent metal post bumps known in the art. In another embodiment, these metal post bumps (e.g., copper) extends from either the top or the bottom interposer toward a solder bump on the bottom interposer for connecting the two by soldering. The height of the structure is substantially the same whether employing solder bumps or metal post bumps (e.g., copper). The combined height of the bumps is about 50 μm (microns), and the ratio of the heights of the larger bumps to the smaller bumps is about 3:1.

The top interposer has a blanket metal coating on the bottom or top surface and the connections to the bottom interposer or the chip carrier would be to electrical ground or bias depending on the function required. As shown in FIG. 2, one or more devices connected to the bottom interposer may be shielded with a top interposer selectively to provide the functional isolation for shielding or protection desired, for maximum miniaturization. Thermal interface material can be dispensed on the back of the integrated circuit device prior to joining the top interposer in order to provide for rapid heat dissipation from the integrated circuit device if required.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are not necessarily drawn to scale but nonetheless set out the invention, and are included to illustrate various embodiments of the invention, and together with this specification also serve to explain the principles of the invention. These drawings comprise various Figures that illustrate ESD, EMI and EMC shielding and protection of integrated circuit devices in 3D packaging.

FIGS. 1 -2 comprise side elevations in cross-section illustrating structures for ESD, EMI and EMC shielding and protection of integrated circuit devices in 3D packaging.

DETAILED DESCRIPTION OF THE INVENTION

To achieve the foregoing and other advantages, and in accordance with the purpose of this invention as embodied and broadly described herein, the following detailed description comprises disclosed examples of the invention that can be embodied in various forms.

The specific processes, compounds, compositions, and structural details set out herein not only comprise a basis for the claims and a basis for teaching one skilled in the art to employ the present invention in any novel and useful way, but also provide a description of how to make and use this invention. The written description, claims, abstract of the disclosure, and the drawings that follow set forth various features, objectives, and advantages of the invention and how they may be realized and obtained. These features, objectives, and advantages will also become apparent by practicing the invention.

As noted before, the interposer sandwich structure as shown in FIG. 1 comprises two interposers enclosing a device requiring shielding or protection. A solder or metal post bump size hierarchy may be used with smaller solder bumps attaching the integrated circuit device to the interposer on the bottom, and larger solder or metal post bumps or other interconnection structure connecting the top interposer with the bottom interposer or directly with the chip carrier. The top interposer has a blanket metal coating on the bottom or top surface, and the connections to the bottom interposer or the chip carrier would be to electrical ground or bias, depending on the function required. As shown in FIG. 2 one or more devices connected to the bottom interposer may be shielded with a top interposer selectively to provide the functional isolation for shielding or protection desired for maximum miniaturization. Thermal interface material can be dispensed on the back of the integrated circuit device prior to joining the top interposer in order to provide for rapid heat dissipation from the integrated circuit device if required.

FIG. 1, illustrates a interposer sandwich structure for ESD, EMI, and EMC shielding and protection having a top interposer 110, and interconnectors 112 and 114 comprising joined solder bumps, as described herein or metal posts capped with solder alloy. An Application Specific Integrated Circuit (ASIC) 116 is position under top interposer 110 that is operatively associated with chip ground I/O interconnection 118.

A first metal layer 120 is positioned on BEOL dielectric layer 132 and a second metal layer 122 on the bottom interposer 134. We also form a chip signal I/O interconnection 124 and a chip signal I/O interconnection 126 (substantially the same as 124) both positioned on the device as shown. A second metal layer 128 contacts the bottom interposer 134. A through-Si-Via interconnection130 forms an electrical connection to chip carrier 138 through connector 135. We position BEOL dielectric layer 132 on bottom interposer 134 which is operatively associated with second level ground I/O interconnection 136 and Chip carrier 138.

FIG. 2 illustrates top Interposer 210 with interconnectors 212 and 214 constructed of solder bumps or metal posts (Cu or Ni, or the art-known equivalents thereof) positioned above chips 216 and 220. Chip 224 and chip 228 are positioned away from the interposer to illustrate that the invention may be used in limited areas on a device or devices mounted on a chip carrier such as chip carrier 232. These chips 216, 220, 224, and 228 are operatively associated with structure 230 that comprises capacitors and wiring input/output (I/O) that is mounted on chip carrier 232.

Interconnectors 112, 114, 212, and 214 as noted comprise solder (SnPb, SnAg, SnAgCu, or the art-known equivalents thereof) bumps or metal (Cu or Ni or the art-known equivalents thereof.) posts capped with solder alloy. In those instances we employ shorter interconnectors between the chip and the lower interposer before assembly of upper interposer to the lower interposer with taller interconnectors. The shorter interconnectors are about one-third the height of the taller interconnects between the upper interposer and the lower interposer.

The interposers comprise a structure made of Si or other materials such as ceramics used in microcircuit technology (e.g., SiC) and the art-know equivalents thereof, or polymers, such as polyimides, phenolics or epoxies and the art-know equivalents thereof.

Throughout this specification, and abstract of the disclosure, the inventors have set out equivalents, of various materials as well as combinations of elements, materials, compounds, compositions, conditions, processes, structures and the like, and even though set out individually, also include combinations of these equivalents such as the two component, three component, or four component combinations, or more as well as combinations of such equivalent elements, materials, compositions conditions, processes, structures and the like in any ratios or in any manner.

Additionally, the various numerical ranges describing the invention as set forth throughout the specification also includes any combination of the lower ends of the ranges with the higher ends of the ranges, and any single numerical value, or any single numerical value that will reduce the scope of the lower limits of the range or the scope of the higher limits of the range, and also includes ranges falling within any of these ranges.

The terms “about,” “substantial,” or “substantially” as applied to any claim or any parameters herein, such as a numerical value, including values used to describe numerical ranges, means slight variations in the parameter or the meaning ordinarily ascribed to these terms by a person with ordinary skill in the art. In another embodiment, the terms “about,” “substantial,” or “substantially,” when employed to define numerical parameter include, e.g., a variation up to five per-cent, ten per-cent, or 15 per-cent, or somewhat higher.

The term “operatively associated” as used in this specification means at least two structures and/or materials or compounds or compositions connected to or aligned with one another to perform a function, such as electrical conductance, electrical shielding, electrical insulation, or heat shielding, or in some way to enhance the performance of one or the other or both.

All scientific journal articles and other articles, including internet sites, as well as issued and pending patents that this written description or applicants' Invention Disclosure Statements mention, including the references cited in such scientific journal articles and other articles, including internet sites, and such patents, are incorporated herein by reference in their entirety and for the purpose cited in this written description and for all other disclosures contained in such scientific journal articles and other articles, including internet sites as well as patents and the references cited therein, as all or any one may bear on or apply in whole or in part, not only to the foregoing written description, but also the following claims, and abstract of the disclosure.

Although the inventors have described their invention by reference to some embodiments, other embodiments defined by the doctrine of equivalents are intended to be included as falling within the broad scope and spirit of the foregoing written description, and the following claims, and abstract of the disclosure.

Claims

1. A process for providing ESD or EMI or EMC shielding or protection for an integrated circuit electronic device comprising positioning said device in a cage comprising an interposer sandwich structure comprising a top interposer and a bottom interposer enclosing said device, an attaching structure for attaching said device to said bottom interposer, and an interconnection structure connecting said top interposer to said bottom interposer.

2. The process of claim 1 wherein said attaching structure for attaching said device to said bottom interposer comprise small metal bumps and said interconnection structure comprises large metal bumps extending from said top interposer and fused with small metal bumps extending from said bottom interposer.

3. The process of claim 1 wherein said attaching structure for attaching said device to said bottom interposer comprise small solder bumps and said interconnection structure comprises large solder bumps extending from said top interposer and fused with small solder bumps extending from said bottom interposer.

4. The process of claim 1 wherein said attaching structure for attaching said device to said bottom interposer comprise small solder bumps and said interconnection structure comprises large copper bumps extending from said top interposer and fused with small solder bumps extending from said bottom interposer.

5. The process of claim 1 wherein said interposers are selected from silicon interposers, ceramic interposers and polymeric interposers and combinations thereof.

6. The process of claim 1 wherein said interposers comprise silicon interposers.

7. The process of claim 1 wherein said top interposer is also directly connected to a chip carrier.

8. The process of claim 1 wherein said top interposer includes a blanket metal coating on at least one of the bottom or top surfaces of said top interposer.

9. The process of claim 1 wherein said attaching structure for attaching said device to said bottom interposer comprises electrical connections to an electrical ground or bias.

10. The process of claim 1 wherein said top interposer comprises connections to a chip carrier.

11. The process of claim 10 wherein said connections to said chip carrier comprises connections to an electrical ground or bias.

12. The process of claim 1 comprising a plurality of said devices connected to said bottom interposer wherein said top interposer is operatively associated with less than all of said devices to provide selective functional isolation of said devices for shielding for maximum miniaturization.

13. The process of claim 1 comprising a thermal interface material operatively associated with said device to provide rapid heat dissipation from said device.

14. The process of claim 12 comprising a thermal interface material operatively associated with said devices to provide rapid heat dissipation from said devices.

15. A process for forming a cage structure to provide ESD, EMI and EMC shielding and protection of integrated circuit device in 3D packaging by forming said cage as a sandwich structure comprising interposers including top and bottom interposers around said integrated circuit device in which metallized shielding is incorporated into both said top and bottom interposers.

16. The process of claim 15 further providing TSV's for interconnection of said metallized shielding to ground or voltage as required electrically, and providing said bottom interposer in said sandwich connected by TSV's and solder connections to said chip carrier package, and said top interposer connecting peripherally by TSV's beyond the outline of said integrated circuit device to said bottom interposer to connect electrically to said chip carrier to provide said cage as a miniature localized cage around said device that preserves the scale of integration and miniaturization of said integrated circuit device.

17. The process of claim 15 further providing multiple integrated circuit devices comprising a miniaturized sandwich package structure in which multiple integrated circuit devices are placed adjacent to one another on the same interposer with TSV's in which one or more top interposers are provided to isolate ESD or EMI or EMC sensitive devices from one another in close proximity in said miniaturized sandwich package structure.

18. The process of claim 15 providing said interposer sandwich structure as a structure comprising two interposers enclosing said integrated circuit device that includes a solder bump size hierarchy with smaller solder bumps or other interconnection structure attaching said integrated circuit device to said bottom interposer, and larger solder bumps or other interconnection structure connecting said top interposer with said bottom interposer, or directly with said chip carrier, wherein said other interconnection structure comprises copper post bumps or equivalent metal post bumps.

19. The process of claim 18 further providing said metal post bumps to extend from either said top interposer or said bottom interposer toward a solder bump on the opposite interposer for connecting said top interposer and said bottom interposer by soldering.

20. The process of claim 19 further providing a structure whose height is substantially the same whether employing solder bumps or metal post bumps and the ratio of the heights of said larger bumps to said smaller bumps is about 3:1.

21. The process of claim 20 wherein the combined height of said bumps is about 50 μm (microns).

22. The process of claim 15 of providing said top interposer with a blanket metal coating on said bottom or top surface and said connections to said bottom interposer or said chip carrier is selected from an electrical ground or bias.

23. The process of claim 15 further providing one or more devices connected to said bottom interposer are provided with shielding with a top interposer selectively to provide functional isolation for shielding or protection for maximum miniaturization.

24. The process of claim 15 further providing thermal interface material dispensed on the back of said integrated circuit device prior to joining said top interposer in order to provide for rapid heat dissipation from said integrated circuit device.