NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.
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This application is based upon and claims the benefit of priority from U.S. Provisional Patent Application No. 62/132,254, filed on Mar. 12, 2015, the entire contents of which are incorporated herein by reference.
FIELDEmbodiments described herein relate generally to a nonvolatile semiconductor memory device and a method of manufacturing the nonvolatile semiconductor memory device.
BACKGROUNDRecently, in the field of NAND-type flash memories, attention has been focused on a laminated-type (three-dimensional) NAND-type flash memory as a device that can achieve high integration without being restricted by the limit of resolution of the lithography technology. This type of three-dimensional NAND-type flash memory includes a laminated body and a semiconductor layer. In the laminated body, a plurality of conductive films and interlayer insulating films are alternately laminated. The conductive film functions as word lines and selection gate lines. The semiconductor layer is formed to pass through these laminated films. This semiconductor layer functions as a body of a memory string. Between the semiconductor layer and the conductive film, a memory film that includes a charge storage film is formed.
In this three-dimensional NAND-type flash memory, the ON/OFF characteristics (selection characteristics) of selection transistors are important, and it is required to cause a flow of a sufficient cell current during selection and keep preferable characteristics of a selection gate electrode.
A nonvolatile semiconductor memory device according to embodiments described below includes a memory cell array and a wiring portion. The memory cell array includes: a memory string where a plurality of memory cells is series-coupled together; and a selection transistor coupled to one end of the memory string. The memory string is formed to extend to have the longitudinal direction in a first direction. The wiring portion is formed by alternately laminating a first conducting layer and an interlayer insulating film over a plurality of layers. The first conducting layers function as gate electrodes for the memory cells and the selection transistor. One of the selection transistors includes a plurality of the first conducting layers, and the plurality of the first conducting layers are electrically coupled in common to a second conducting layer that is a common contact formed on the sidewall of the wiring portion.
The following describes nonvolatile semiconductor memory devices according to embodiments in detail with reference to the accompanying drawings. Here, these embodiments are only examples. For example, the nonvolatile semiconductor memory device described below has a structure where a memory string extends in a straight line in the vertical direction with respect to a substrate. The similar structure is also applicable to the structure having a U shape where a memory string is folded to the opposite side in the middle. The respective drawings of the nonvolatile semiconductor memory devices used in the following embodiments are schematically illustrated. The thickness, the width, the ratio, and similar parameter of the layer are not necessarily identical to actual parameters.
Examples will be described below. This embodiment relates to a nonvolatile semiconductor memory device in a structure where a plurality of metal-oxide-nitride-oxide-semiconductor (MONOS) type memory cells (transistors) is disposed in a height direction. The MONOS type memory cell includes: a semiconductor film disposed in a columnar shape vertical to the substrate as a channel, and a gate electrode film disposed on the side surface of the semiconductor film via a charge storage layer. However, a similar structure is applicable to another type of charge storage film, for example, a semiconductor-oxide-nitride-oxide-semiconductor type (SONOS) memory cell or a floating-gate type memory cell.
First EmbodimentThe memory cell array 11 includes memory strings MS, drain-side selection transistors S1, and source-side selection transistors S2 on a semiconductor substrate (not illustrated in
As described later, the memory cell MC has the structure, where a control gate electrode (word line) is disposed on the side surface of a columnar semiconductor film, becomes a channel via a memory film including a charge storage layer. The drain-side selection transistor and the source-side selection transistor each have the structure where a selection gate electrode (selection gate line) is disposed on the side surface of a columnar semiconductor film via the memory film. For simplification of the illustration,
The word line WL is coupled in common to the adjacent memory cells along the X direction (the word-line direction) in
Furthermore, the bit lines BL are disposed to extend having the longitudinal direction in the Y direction (the bit-line direction) intersecting with the X direction (the word-line direction), and are collocated at a predetermined pitch in the X direction. The bit line BL is coupled to a plurality of the memory strings MS via the drain-side selection transistors S1. Source lines SL, which are omitted in
The word-line driving circuit 12 is a circuit that controls the voltage to be applied to the word line WL. The source-side selection-gate-line driving circuit 13 is a circuit that controls the voltage to be applied to the source-side selection gate line SGS. The drain-side selection-gate-line driving circuit 14 is a circuit that controls the voltage to be applied to the drain-side selection gate line SGD. The sense amplifier 15 is a circuit for amplifying a signal (voltage) read out from a selected memory cell to the bit line BL.
The wiring portion 20 is a wiring portion for coupling the word lines WL and the selection gate lines SGD and SGS to the contacts. The word lines WL, the selection gate lines SGS and SGD have a structure processed in a staircase pattern such that the respective upper portions can independently be coupled to the contacts.
The following describes the detail of the structure of the memory cell array 11 with reference to
As illustrated in
The conducting layer 22 can be formed of, for example, tungsten (W), tungsten nitride (WN), tungsten silicide (WSix), tantalum (Ta), tantalum nitride (TaN), tantalum silicide (TaSix), palladium silicide (PdSix), erbium silicide (ErSix), yttrium silicide (YSix), platinum silicide (PtSix), hafnium silicide (HfSix), nickel silicide (NiSix), cobalt silicide (CoSix), titanium silicide (TiSix), vanadium silicide (VSix), chrome silicide (CrSix), manganese silicide (MnSix), iron silicide (FeSix), ruthenium (Ru), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), vanadium (V), chrome (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), gold (Au), silver (Ag) or copper (Cu), or can be formed of a compound of these materials. The conducting layer 22 may be formed of polysilicon with the addition of impurities.
Semiconductor layers 23 having the longitudinal direction in the lamination direction (the Z direction) and passing through this laminated body of the interlayer insulating film 21 and the conducting layer 22 are disposed at a predetermined pitch in the XY plane. Between: the semiconductor layer 23; and the conducting layer 22 and the interlayer insulating film 21, a memory film 24 including a charge storage layer is formed. As described later, the memory film 24 can be formed by a laminated structure of: a charge storage film such as a silicon nitride film, and an oxide film such as a silicon oxide film. Depending on the storage amount of the electric charge to this charge storage film, the threshold voltage of the memory cell MC changes. The memory cell MC holds data corresponding to this threshold voltage.
The semiconductor layers 23 function as the channel regions (body) of the memory cell MC, the dummy cells DMC1 and DMC2, and the selection transistors S1 and S2 that are included in the NAND cell unit NU. These semiconductor layers 23 are coupled, on their upper ends, to the bit lines BL via contacts Cb. The bit lines BL having the longitudinal direction in the Y direction are collocated at a predetermined pitch along the X direction.
The lower end of the semiconductor layer 23 is coupled to the semiconductor substrate SB. Then, the lower end of the semiconductor layer 23 is coupled to the source line SL via this semiconductor substrate SB and a source contact LI, which is described later. The source lines SL are collocated while having their longitudinal directions in the Y direction, similarly to the bit lines BL.
Here, the laminated body of the interlayer insulating film 21 and the conducting layer 22 in the memory cell array 11 is separated by blocks as the smallest unit of data erasure. At the boundary of the separation, a trench Tb is formed. In this trench Tb, an interlayer insulating film (not illustrated) is implanted. Further, the source contact LI described above is formed passing through the interlayer insulating film. This source contact LI has a lower end coupled to the semiconductor substrate SB while having an upper end coupled to the source line SL.
In the peripheral area of this semiconductor columnar portion 102, the memory film 24 is formed to surround the semiconductor columnar portion 102. The memory film 24 includes a tunnel insulating film 103, a charge storage layer 104, and a block insulating film 105. The tunnel insulating film 103 is constituted of, for example, a silicon oxide film (SiOx), and functions as the tunnel insulating film of the memory cell MC or the dummy cell DMC. The charge storage layer 104 is constituted of, for example, a silicon nitride film (SiN), and has a function that traps electrons injected from the semiconductor columnar portion 102 via the tunnel insulating film 103 by a write operation. The block insulating film 105 can be formed of, for example, a silicon oxide film. In this example, the tunnel insulating film 103, the charge storage layer 104, and the block insulating film 105 are illustrated to be formed in the whole region of the side surface of the semiconductor columnar portion 102. This, however, should not be construed in a limiting sense. These members can be formed only on the side surface of the word line WL. The memory film 24 illustrated in
Here, the materials of the tunnel insulating film 103 and the block insulating film 105 can employ, for example, Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO other than the silicon oxide film (SiOx).
The following describes the structures of the memory cell array 11 and the wiring portion 20 further in detail with reference to
As illustrated in
This source contact LI is implanted in the trench Tb, which divides the memory cell array 11 by blocks, via the interlayer insulating film 21′. The source contact LI has the lower end in contact with the diffusion layer, which is formed on the surface of the substrate SB, and has the upper end coupled to the source line SL via upper-layer wiring.
The following describes the structure of the wiring portion 20 with reference to
The conducting layers 22 that function as the word lines WL are processed in a staircase pattern together with the interlayer insulating films 21 in this wiring portion 20. Accordingly, the respective upper portions of the word lines WL can be independently coupled to contacts Cw. The conducting layers 22 that function as the word lines WL are coupled to the word-line driving circuit 12 illustrated in
On the other hand, the conducting layers 22 that function as the drain-side selection gate line SGD are processed not in a staircase pattern, but such that their end portions have the identical length in the X direction (the longitudinal direction of the selection gate line) as illustrated in
While not illustrated, the conducting layers 22 that function as the source-side selection gate line SGS, which is formed in the lower portion of the laminated body, are also formed similarly to the drain-side selection gate line SGD. The end portions of the conducting layers 22 are processed to be aligned in the longitudinal direction. The selection gate line SGS coupled to one source-side selection transistor S2 includes a plurality of the conducting layers 22 (the first conducting layers) electrically coupled in common to a conducting layer (the second conducting layer) arranged in these end portions, similarly to the drain-side selection gate line SGD.
Here, as described in detail later, the conducting layer 22 can be formed by removing a sacrifice film by wet etching and then filling a conductive material in the void from which the sacrifice film has been removed. In the case where this wet etching is performed, the wiring portion 20 includes slit portions CC arranged at predetermined intervals as illustrated in
As apparent from this description, the removal of the sacrifice film and the film formation of the conducting layer 22 are performed by pouring the materials in the Y direction using the slit CC. On the other hand, the conducting layer 25 is formed in the end portions of the conducting layers 22 in the X direction. This does not affect the pouring of the materials in the Y direction at the time of the removal of the sacrifice film and the film formation of the conducting layer. Additionally, because the conducting layer 25 is formed from the material different from that of the sacrifice film 22′, the conducting layer 25 is not removed simultaneously when a sacrifice film 22′ is removed. Therefore, the conducting layer 25 can be formed as a film at any timing before the sacrifice film is removed, after the sacrifice film is removed and the conducting layer 22 is formed as a film, or similar timing.
Here, the conducting layer 22 constituting the word line WL may be a staircase portion that one-dimensionally expands only in the X direction as illustrated in
Next, a description will be given of a method of manufacturing the wiring portion 20 with reference to
Firstly, as illustrated in
Here, a description is given of the case where the sacrifice films 22′ are replaced by the conducting layers 22 as the metal films above. However, for example, it is possible to laminate the conducting layers, which are made of silicon doped with impurities or similar material, and the interlayer insulating films from the start, so as to form the laminated body without replacement.
The insulating layer 26 can employ various materials such as silicon nitride other than alumina described above.
EffectsAccording to the first embodiment described above, the plurality of the conducting layers 22 of the selection gate line are electrically coupled in common to the conducting layer 25, which is arranged in their end portions. This allows obtaining a nonvolatile semiconductor memory device in a three-dimensional structure having a selection transistor with high selectivity.
Second EmbodimentThe following describes a nonvolatile semiconductor memory device according to a second embodiment with reference to
Regarding the wiring portion 20 illustrated in
The method of manufacturing the wiring portion 20 according to the second embodiment is approximately identical to the manufacturing method used in the first embodiment, but is differs from the first embodiment in the phase of forming the conducting layer 25 described using
This second embodiment also allows providing effects identical to those in the first embodiment. Furthermore, in this second embodiment, the conducting layer is formed extending to the inner side of the end portion of the selection gate. This further increases the contacted area between the conducting layer and the conducting layers of the selection gate, thus reducing the resistance. This consequently provides preferable current characteristics, thus realizing excellent cell characteristics.
[Modification]A description will be given of other examples of the wiring portion with reference to
In the first and second embodiments, the plurality of the conducting layers 22 of the selection gate line are coupled in common to one conducting layer 25, which is formed in the end portion of the selection gate line aligned in the longitudinal direction. However, like
In
As illustrated in
In the above-described embodiments and modification, a description is given of the case where all the conducting layers 22 function as the gate electrodes of the selection gate lines. However, as illustrated in
As apparent from the first and second embodiments and the modification described above, it is possible to employ various shapes of the conducting layer 22 constituting the selection gate line and various arrangement methods of the conducting layer 25 arranged in the end portion of the selection gate line, depending on the usage or similar condition. In the drawings used in the above description, there are always four layers of the conducting layers 22 and there are one or two layers of the conducting layers 25. Obviously, the number of laminations of the conducting layers 22 and the number of the conducting layers 25 are not limited to these.
EffectsThe above-described nonvolatile semiconductor memory device according to the modification can also provide effects similar to those in the first and second embodiments that have been described.
[Charge Storage Layer 104]As the material of the charge storage layer 104, the silicon nitride film (SiN) is described in the above-described embodiment as an example. However, the following oxides can also be selected.
-
- SiO2, Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO
- AB2O4 (However, A and B are identical or different elements, and, are one of Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, and Ge. For example, Fe3O4, FeAl2O4, Mn1|xAl2 XO4|y, Co1|XAl2 XO4|y, and MnOx are employed.)
- ABO3 (However, A and B are identical or different elements, and, are one of Al, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, and Sn. For example, LaAlO3, SrHfO3, SrZrO3, and SrTiO3 are employed.)
As the material of the charge storage layer 104, the following oxynitrides can also be selected.
-
- SiON, AlON, YON, LaON, GdON, CeON, TaON, HfON, ZrON, TiON, LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON, and AlSiON
Further, it is also possible to employ the materials obtained by replacing a part of the oxygen elements of the oxides described above by nitrogen elements. In particular, one insulating layer and a plurality of insulating layers are each preferred to be selected from the group consisting of SiO2, SiN, Si3N4, Al2O3, SiON, HfO2, HfSiON, Ta2O5, TiO2, and SrTiO3.
In particular, regarding silicon-based insulating films such as SiO2, SiN, and SiON, the respective concentrations of the oxygen elements and the nitrogen elements can be set to be equal to or more than 1×1018 atoms/cm3. However, the barrier heights of the plurality of insulating layers are different from one another. The insulating layer can include a material including impurity atoms that forms a defect level or semiconductor/metal dots (the quantum dots).
[Others]While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims
1. A nonvolatile semiconductor memory device, comprising:
- a substrate;
- a memory cell array extending in a direction vertical to the substrate, the memory cell array including: a memory string having a plurality of series-coupled memory cells; and a selection transistor coupled to one end of the memory string;
- a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cells and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and
- a second conducting layer arranged on end portions of the plurality of first conducting layers included in the selection transistor, wherein
- the plurality of first conducting layers included in the selection transistor is electrically coupled in common to the second conducting layer.
2. The nonvolatile semiconductor memory device according to claim 1, wherein
- the plurality of first conducting layers included in the selection transistor have end portions aligned in a longitudinal direction of the first conducting layers, and
- the plurality of first conducting layers whose end portions are aligned in the longitudinal direction are electrically coupled in common to one of the second conducting layer.
3. The nonvolatile semiconductor memory device according to claim 1, wherein
- the plurality of first conducting layers included in the selection transistor have end portions forming a staircase structure,
- the staircase structure of the plurality of first conducting layers has an end portion where the second conducting layer is arranged for each step, and
- the first conducting layers having identical steps are electrically coupled in common to the second conducting layer, and the first conducting layers having mutually different steps are electrically independent from one another.
4. The nonvolatile semiconductor memory device according to claim 1, wherein
- the plurality of first conducting layers included in the selection transistor have end portions projecting in a longitudinal direction of the first conducting layers with respect to end portions of the interlayer insulating films, and
- the second conducting layer extends from the end portions of the first conducting layers to portions between the first conducting layers.
5. The nonvolatile semiconductor memory device according to claim 1, wherein
- the selection transistor includes at least one dummy cell.
6. The nonvolatile semiconductor memory device according to claim 1, wherein
- the first conducting layer and the second conducting layer are made of mutually different materials.
7. The nonvolatile semiconductor memory device according to claim 1, wherein
- the selection transistor is a drain-side selection transistor coupled to an upper end of the memory string.
8. The nonvolatile semiconductor memory device according to claim 7, further comprising
- a source-side selection transistor arranged between a lower end of the memory string and the substrate, the source-side selection transistor having the plurality of first conducting layers as gate electrodes thereof, wherein
- the first conducting layers included in the source-side selection transistor have end portions where the second conducting layer is arranged, the first conducting layers included in the source-side selection transistor being electrically coupled in common to the second conducting layer.
9. A method of manufacturing a nonvolatile semiconductor memory device, wherein
- the nonvolatile semiconductor memory device includes: a memory string having a plurality of series-coupled memory cells; and a selection transistor coupled to one end of the memory string, and
- the manufacturing method comprises:
- alternately laminating a plurality of first conducting layers and a plurality of interlayer insulating films on a substrate, the first conducting layers functioning as gate electrodes of the memory cells and the selection transistor, the interlayer insulating films being positioned between the first conducting layers in above and below directions; and
- forming a second conducting layer on end portions of the plurality of first conducting layers included in the selection transistor, such that the plurality of first conducting layers included in the selection transistor is electrically coupled in common to the second conducting layer.
10. The manufacturing method of the nonvolatile semiconductor memory device according to claim 9, further comprising:
- forming a void between the end portions of the plurality of first conducting layers by etching end portions of the interlayer insulating films between the plurality of first conducting layers; and
- forming the second conducting layer on the end portions of the first conducting layers and inside the void.
11. The manufacturing method of the nonvolatile semiconductor memory device according to claim 9, further comprising:
- forming the end portions of the plurality of first conducting layers included in the selection transistor in a staircase pattern;
- forming the second conducting layer on end portions of the plurality of first conducting layers for each step of the staircase structure; and
- electrically coupling the first conducting layers having identical steps in common to the second conducting layer, and electrically separating the first conducting layers having mutually different steps from one another.
12. The manufacturing method of the nonvolatile semiconductor memory device according to claim 9, wherein
- the selection transistor include at least one dummy cell.
13. The manufacturing method of the nonvolatile semiconductor memory device according to claim 9, wherein
- the first conducting layer is a metal film formed in a void caused by removing a sacrifice film laminated alternately with the interlayer insulating films by etching, and
- the second conducting layer is formed after the metal film is formed.
14. The manufacturing method of the nonvolatile semiconductor memory device according to claim 9, wherein
- the first conducting layer and the second conducting layer are made of mutually different materials.
15. The manufacturing method of the nonvolatile semiconductor memory device according to claim 9, wherein
- the selection transistor is a drain-side selection transistor coupled to an upper end of the memory string.
16. The manufacturing method of the nonvolatile semiconductor memory device according to claim 15, further comprising
- providing a source-side selection transistor arranged between a lower end of the memory string and the substrate, the source-side selection transistor having the plurality of first conducting layers as gate electrodes thereof, wherein
- the first conducting layers included in the source-side selection transistor have end portions where the second conducting layer is arranged, the first conducting layers being electrically coupled in common to the second conducting layer.
Type: Application
Filed: Sep 10, 2015
Publication Date: Sep 15, 2016
Applicant: Kabushiki Kaisha Toshiba (Minato-ku)
Inventor: Daigo ICHINOSE (Nagoya)
Application Number: 14/849,772