MANUFACTURING METHOD OF WAFER LEVEL PACKAGE STRUCTURE
A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.
Latest Powertech Technology Inc. Patents:
This application claims the priority benefit of Taiwan application serial no. 105104081, filed on Feb. 5, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTIONField of the Invention
The invention relates to a manufacturing method of a package structure, and particularly relates to a manufacturing method of a wafer level package structure.
Description of Related Art
In a manufacturing process of a wafer level package (e.g., fan out wafer level package (FO-WLP)), in order to support the wafer after thinning, the wafer is usually placed on a wafer support system (WSS). In this way, the wafer is able to withstand various transport in the manufacturing process and avoid wafer warpage which may cause fragmentation.
Then, as shown in
Then, as shown in
In the conventional manufacturing process, since a thickness variation of the glass supporting board 12 in different positions of the wafer support system 11 is larger, and the control of flatness and uniformity when coating the gel layer 13 has the manufacturing process limitations, the conductive pillars 24 or the RDL 40 are manufactured on the pads 23 in the conventional manufacturing process to overcome the height difference between different pads 23 after attaching the chip 20 to the wafer support system 11. However, if the flatness of the wafer support system 11 is worse, the required height of the conductive pillars 24 or the RDL 40 is higher, thereby increasing the package cost. Additionally, multiple chemical cleanings are required in the final step of removing the wafer support system 11, and a special test of the cleaning result is also required after chemical cleaning to avoid the gel layer 13 remaining on the glass supporting board 12 or the back surface 22 of the chip 20, so as to affect the subsequent manufacturing process. Thus, the process of removing the wafer support system 11 also requires a certain cost.
SUMMARY OF THE INVENTIONThe invention provides a manufacturing method of a wafer level package structure, which has a lower manufacturing cost and less process.
The manufacturing method of the wafer level package structure of the invention includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface. The back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.
According to an embodiment of the invention, before disposing the chip onto the supporting board, the manufacturing method further includes disposing the DAF to the back surface of the chip.
According to an embodiment of the invention, before disposing the chip onto the supporting board, the manufacturing method further includes disposing the DAF onto the supporting board.
According to an embodiment of the invention, after forming the RDL, the manufacturing method further includes disposing a plurality of solder balls onto the RDL.
According to an embodiment of the invention, the supporting board is a dummy silicon wafer.
According to an embodiment of the invention, after performing the wafer level exposed die molding procedure, a surface of the molding away from the supporting board is substantially flush with the active surface of the chip.
According to an embodiment of the invention, in the step of removing the supporting board and the DAF from the chip, the manufacturing method further includes removing the supporting board and the DAF from the chip by cutting or grinding.
According to an embodiment of the invention, a thickness variation of the DAF in different positions is less than 1 micrometer.
A manufacturing method of a wafer level package structure includes the following steps. A plurality of chips are disposed on a supporting board, the plurality of chips having corresponding active surfaces substantially leveled to each other. A molding is disposed on the supporting board to surround lateral sides of the plurality of chips, the active surfaces of the plurality of chips being substantially flush with a surface of the molding. A redistribution layer (RDL) is formed on the active surfaces of the plurality of chips and the surface of the molding. The plurality of chips are removed from the supporting board.
According to an embodiment of the invention, wherein disposing the plurality of chips on the supporting board is adhering the plurality of chips on the supporting board using die attach films, each of the die attach films having different thickness to compensate for difference in thickness of different parts of the supporting board.
According to an embodiment of the invention, a thickness variation of the die attach films from each other is less than 1 micrometer.
According to an embodiment of the invention, further includes a plurality of solder balls are disposed on the redistribution layer to electrically connect the plurality of chips to the solder balls.
According to an embodiment of the invention, wherein disposing a molding on the supporting board to surround lateral sides of the plurality of chips is performing a wafer level exposed die molding procedure on the plurality of chips.
According to an embodiment of the invention, wherein removing the plurality of chips from the supporting board is performing cutting or grinding to remove the plurality of chips from the supporting and reduce thickness of the plurality of chips to a preferred thickness.
According to an embodiment of the invention, the supporting board is a dummy silicon wafer
Based on the above, in the manufacturing method of the wafer level package structure of the invention, by using the supporting board composed of the dummy silicon wafer, and fixing the chip to the supporting board through the DAF, the thickness variation of the supporting board composed of the dummy silicon wafer and the DAF in different positions is small. Thereby, the flat platform is provided for supporting the chip. Also, after the chip is disposed on the supporting board, the height variation of the pads is small. Thus, when manufacturing the molding, the wafer level exposed die molding procedure can be used, so that the pads are exposed out of the molding. That is, it is not required to additionally dispose the conductive pillars on the chip. Also, it is not required to grind the molding after manufacturing the molding so as to save multiple processes. Additionally, in the step of removing the supporting board and the DAF from the chip of the manufacturing method of the wafer level package structure of the invention, removing the supporting board and the DAF only by using the method of grinding is more simple and with lower cost in comparison with using the method of chemical cleaning. Also, it can make sure the cleanliness of the supporting board and the cleanliness of the back surface of the chip.
In order to make the aforementioned features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
Then, as shown in
Then, as shown in
Since the supporting board 130 and the DAF 120 provide a flat platform for the chip 110, after the chip 110 is disposed on the supporting board 130, the height variation of pads 116 of different chips 110 is small to none. Thus, the height of the molding 140 may be precisely controlled when forming the molding 140. Therefore, the pads 116 may be exposed through the molding 140. That is, after the chip 110 is disposed on the supporting board 130, since the height variation of different pads 116 is small, the conventional steps to compensate for the height difference is no longer needed. The conventional steps may consist of additionally manufacturing the conductive pillars on the pads 116 of the chip 110 to gain height, disposing the molding whose height is higher than the height of the chip 110 and the conductive pillars, and grinding the molding and the conductive pillars.
Then, as shown in
Then, as shown in
Lastly, as shown in
Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.
Claims
1-8. (canceled)
9. A manufacturing method of a wafer level package structure, comprising:
- disposing a plurality of chips on a supporting board by adhering the plurality of chips on the supporting board using die attach films, the plurality of chips having corresponding active surfaces substantially leveled to each other, and each of the die attach films having different thickness to compensate for difference in thickness of different parts of the supporting board;
- disposing a molding on the supporting board to surround lateral sides of the plurality of chips, the active surfaces of the plurality of chips being substantially flush with a surface of the molding;
- forming a redistribution layer (RDL) on the active surfaces of the plurality of chips and the surface of the molding; and
- removing the plurality of chips from the supporting board.
10. (canceled)
11. The method of claim 9, wherein a thickness variation of the die attach films from each other is less than 1 micrometer.
12. The method of claim 9, further comprising:
- disposing a plurality of solder balls on the redistribution layer to electrically connect the plurality of chips to the solder balls.
13. The method of claim 9, wherein disposing a molding on the supporting board to surround lateral sides of the plurality of chips is performing a wafer level exposed die molding procedure on the plurality of chips.
14. The method of claim 9, wherein removing the plurality of chips from the supporting board is performing cutting or grinding to remove the plurality of chips from the supporting and reduce thickness of the plurality of chips to a preferred thickness.
15. The method of claim 9, wherein the supporting board is a dummy silicon wafer.
Type: Application
Filed: Nov 10, 2016
Publication Date: Aug 10, 2017
Applicant: Powertech Technology Inc. (Hsinchu County)
Inventor: Chia-Hang Chang (Hsinchu County)
Application Number: 15/347,805